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The document outlines examination details for the Analog Microelectronics course at BMS College of Engineering, including instructions for answering questions from various units. Each unit contains multiple questions covering topics such as transistor configurations, MOSFET operations, feedback circuits, and amplifier classifications. The exams span different semesters, indicating a comprehensive assessment of students' understanding of analog electronic circuits.

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0% found this document useful (0 votes)
14 views18 pages

15ES3GCAMC (1)-merged (1)

The document outlines examination details for the Analog Microelectronics course at BMS College of Engineering, including instructions for answering questions from various units. Each unit contains multiple questions covering topics such as transistor configurations, MOSFET operations, feedback circuits, and amplifier classifications. The exams span different semesters, indicating a comprehensive assessment of students' understanding of analog electronic circuits.

Uploaded by

tejaravi1611
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 18

U.S.N.

BMS College of Engineering, Bangalore-560019


(Autonomous Institute, Affiliated to VTU, Belgaum)

December 2016 Semester End Main Examinations


Course: Analog Microelectronics Duration: 3 hrs
Course Code: 15ES3GCAMC Max Marks: 100
Date: 17.12.2016

Instructions: Answer any Five full questions choosing one from each unit
UNIT 1
1. a. Assuming ideal diode in the circuits shown below, draw the output voltages for the 6
given input signal.

Fig.1.a
b. With relevant circuit derive an expression for operating points using exact analysis 7
for a voltage divide bias circuit.

c. Determine the value of re, RE, R1 and R2 for a voltage divider bias, using 7
approximate analysis. Given Vcc = 20V, ICQ = 10ma, VCEQ = 8V, β= 80.
Assume VE = 0.1VCC

OR
2. a. Determine vo for the (dc restorer circuit) network shown. 6

Fig.2a
b. Analyze the circuit of Fig.2.b) to determine the voltage at all nodes and the currents 8
through all branches. Assume β = 100.
Fig.2.b
c. Draw the high frequency hybrid- π model and derive the relation unity gain 6
bandwidth fT.
UNIT 2
3. a. Draw the physical structure of the enhancement type of N-MOS transistor and 10
explain its operation with no Gate Voltage.
b. Mention all types of biasing in MOS amplifier circuits available. Also identify given 10
Figure biasing type and hence compute RG, ID, VD. The circuit operate at a dc drain
current 0.5mA, assume VDD = 5V, kn'W/L=1mA/V2, Vi=1V and λ=0.
UNIT 3
4. a. Draw the small signal equivalent circuit model for the given circuit configuration 10
and evaluate the gm.

b. Determine voltage gain, input impedance and output impedance for the 10
common‐source (CS) MOS amplifier without Rs.
OR
5. a. With necessary equations explain the working of MOSFET as a constant current source 10
and mention its applications.
b. Draw the circuit diagram of the Wilson current mirror. Analyze the circuit to 10
determine Io/IREF (Wilson current transfer ratio).
UNIT 4
6. a. Mention the advantages of negative feedback circuit and Show different types of 10
feedback connection with neat sketches.
b. Derive voltage gain, input impedance and output impedance for the Voltage Series 10
Feedback topology.
UNIT 5
7. a. Derive conversion efficiency for class A series fed power amplifiers. 6
b. Explain with relevant sketches how power amplifiers are classified? Also derive the 8
expression for the conversion efficiency of a push pull class B amplifier.
c. Calculate the harmonic distortion components for an output signal having 6
fundamental amplitudes of 2.1V, second harmonic amplitude of 0.3V, third
harmonic component of 0.1V and fourth harmonic component or 0.05V. Also
calculate the total harmonic distortion.

*******
U.S.N.

B.M.S. College of Engineering, Bengaluru-560019


Autonomous Institute Affiliated to VTU

July / August 2019 Supplementary Examinations


Programme: B.E. Semester : III
Branch : TELECOMMUNICATION ENGINEERING Duration: 3 hrs.
Course Code: 15ES3GCAMC Max Marks: 100
Course Title: ANALOG MICROELECTRONICS Date: 29.07.2019

Instructions: 1. Answer any FIVE full questions, choosing one full question from each unit.

UNIT - I
Important Note: Completing your answers, compulsorily draw diagonal cross lines on the remaining blank pages.

1 a) Derive an expression for voltage gain, input impedance and output 08


impedance of a Transistor CE configuration using re model (Without
Bypass Capacitor).
b) Identify a suitable electronic circuit to shifting input reference voltage level 06
to dc level of (-80V) for an input signal with domestic supply frequency
with a peak of 100V. Design the same. Write suitable input and output
waveform (assume diode is ideal).
c) Discuss the effect of CS, CC & CE on low frequency of CE amplifier circuit 06
with voltage divider bias arrangement.

OR
Revealing of identification, appeal to evaluator will be treated as malpractice.

2 a) Obtain a suitable circuit to obtain the transfer characteristics as shown 05


below. Also write input and output wave form for a triangular input wave
with peak of ±20V. Indicate slope on the graph.

b) Find the Quiscent base current, collector current and VCE for a voltage 05
divider bais circuit with 𝛽=80 for a silicon transistor, with RE=680Ω , RC =
3.9KΩ, R1=62KΩ, R2=9.1KΩ, CC=10μF each on input and output, CE =
50μF, VCC=16V
i) Repeat for 𝛽=150
ii) Plot the dc load line and locate the operating points
corresponding to 𝛽=80 and 𝛽=150
c) Write Hybrid 𝜋 model of a CE amplifier and How do you arrive at low 05
frequency hybrid model from the same.
d) For the amplifier shown in the circuit. Calculate VCC for a voltage gain of 05
Av = - 200, given β=90 and R0=∞𝛺

UNIT - II
3 a) Obtain the expression for drain current equation for an ‘n’ channel 06
MOSFET operating in
i) triode region
ii) Saturation region
b) Explain channel length modulation effect and derive an expression for 08
iD(Drain current) considering the same.
c) Design the circuit shown in fig 3.c. to obtain a drain current of 80𝜇A. Find 06
the value required for RD and find the dc voltage VD .
Given Vt = 0.6V
𝜇 n CoX = 200𝜇A/V2
L=0.8𝜇𝑀 and W=4𝜇M
λ=0

UNIT - III
4 a) Explain Wilson current Mirror circuit and determine the current transfer 06
ratio.
b) Draw the small signal equivalent model for the given circuit configuration 10
and evaluate gm.

c) A MOSFET is to operate at ID = 0.1mA and is to have gm = 1mA/V. If 04


K’n = 50mA/V2. Find the required W/L and over drive voltage.
OR
5 a) Write the circuit of a CS amplifier bias by using a current source. Write its 10
small signal model and derive expressions for AV, Ri and RO.
b) An NMOS Transistor has μn CoX = 60μA/V2 , W/L = 40, Vt = 1V and 06
VA= 15V. Find gm and ro when
(a) The bias voltage VGS = 1.5V and
(b) The bias current ID = 0.5mA
c) Sketch the T equivalent circuit model of MOSFET. 04

UNIT - IV
6 a) Using the block diagram of a voltage shunt feed back amplifier derive the 06
expressions for its transfer gain with feedback.
b) Analyze an emitter follower circuit using a suitable BJT Model. Obtain the 10
expressions for AVf , Rif and Rof.
c) Calculate the gain in decibels of a negative feedback amplifier having 04
A=1000; If the feedback factor is 10%.

UNIT - V
7 a) Derive the expression for a class A transformer coupled amplifier 07
efficiency for maximum signal consideration.
b) A class B push pull amplifier operating with VCC = 25V provides a 22V 10
peak signal to an 8Ω load. Find.
i) RMS and peak output current
ii) RMS and peak collector current
iii) Current drawn from the supply
iv) Input power
v) Output power
vi) % Efficiency
vii) Power dissipation in the transistor
c) What maximum power can Silicon transistor dissipate into free air at an 03
ambient temperature of 80oC.
The junction temperature should not exceed 200oC assuming
ӨJA=40oC/W (Note : Transistor operates with out Heat sink)
*****
U.S.N.

B.M.S. College of Engineering, Bengaluru-560019


Autonomous Institute Affiliated to VTU

September / October 2023 Supplementary Examinations


Programme: B.E. Semester: III
Branch: ES Cluster (EEE/TCE/ECE/EIE/MD) Duration: 3 hrs.
Course Code: 19ES3CCAEC Max Marks: 100
Course: Analog Electronic Circuits Date: 13.09.2023

Instructions: 1. Answer any FIVE full questions, choosing one full question from each unit.
2. Missing data, if any, may be suitably assumed.

UNIT - I
1 a) For the circuit shown in Fig.1, determine the transfer characteristics and 06
Important Note: Completing your answers, compulsorily draw diagonal cross lines on the remaining blank pages.

sketch the output waveform.

Fig.1
Revealing of identification, appeal to evaluator will be treated as malpractice.

b) For the voltage divider configuration shown below , Use approximate analysis 07
and calculate
a)VB
b)IC and IB
c) VE and VCE. Assume silicon transistor with β =110

c) Derive the equations for voltage gain , current gain, input impedance and 07
output impedance for a CE ,Voltage divider configuration using re model

OR
2 a) Determine I , V 1 , V 2 , and V o for the series dc configuration shown 04

b) Design a suitable circuit for the block shown below which has input and output 05
waveforms as indicated

c) Derive an equation for IB and VCE for a voltage divider Bias using exact 05
analysis.
d) For the network of Fig. 2 , determine: 06
a. r e , b. Z i , c. Z o ( ro =∞Ω). , d. Av (ro =∞Ω) .

Fig.2
UNIT - II
3 a) Derive equation for Miller effect induced input and output capacitance for an 06
inverting amplifier
b) Identify the amplifier shown and enumerate its properties, 09
c) Calculate gain, feedback factor, gain with feedback and voltage gain with 05
feedback for the circuit shown in Fig 3

Fig3
UNIT - III
4 a) With a neat circuit diagram, waveforms, explain the working of 08
complementary symmetry class B amplifier. Also, Derive an expression for
conversion efficiency.
b) For a class B amplifier providing a 20V peak signal to a 16Ω load speaker 06
and a power supply of Vcc = 30V, determine the input power, output power
and circuit efficiency.
c) For a harmonic distortion reading of D2 = 0.1, D3 = 0.02, and D4 = 0.01, 06
with I1 = 4 A and RC = 8 Ω, calculate the total harmonic distortion,
fundamental power component, and total power.

UNIT - IV
5 a) Derive an expression for iD when the n-channel e-MOSFET operates in 07
(a)Triode region.
(b)Saturation region
b) Use the expression for operation in the triode region to show that n channel 05
MOSFET operated with an override voltage Vov=VGS-Vt and having a small
VDS across it behaves approximately as a linear resistance rDS . Calculate the
value of rDSobtained for a device having kn’=100µA/v2 and w/L= 10 when
operated with an overdrive voltage of 0.5V
c) Discuss the different methods of biasing a N channel enhancement MOSFET. 08

UNIT - V
6 a) Derive an expression for transconductance and voltage gain for small signal 06
operation of the enhancement MOSFET amplifier
b) Derive expression for input resistance, output resistance, voltage gain and 08
overall voltage gain of a common gate MOSFET amplifier
c) Explain with equations the basic MOSFET as current source. 06
OR
7 a) Obtain the three different relationships for determining gm of a MOSFET 06
b) Derive expression for input resistance, output resistance, voltage gain and 08
overall voltage gain of a common source MOSFET amplifier
c) Discuss the Wilson MOS mirror with neat circuit and relevant equations. . 06

******
U.S.N.

B.M.S. College of Engineering, Bengaluru-560019


Autonomous Institute Affiliated to VTU

June / July 2024 Semester End Make-Up Examinations

Programme: B.E. Semester: III


Branch: Electronics and Communication Engineering Duration: 3 hrs.
Course Code: 23EC3PCAEC Max Marks: 100
Course: Analog Electronic Circuits

Instructions: 1. Answer any FIVE full questions, choosing one full question from each unit.
2. Missing data, if any, may be suitably assumed.

UNIT - I CO PO Marks
Important Note: Completing your answers, compulsorily draw diagonal cross lines on the remaining

1 a) Determine the levels of ICQ and VCEQ for the voltage divider bias CO 2 PO 1 6
circuit shown in the figure 1
blank pages. Revealing of identification, appeal to evaluator will be treated as malpractice.

Figure 1
b) Analyze the circuit shown in Figure 2 and sketch the input and CO3 PO2 06
ouput voltage waveform assuming an ideal diode. (Vi =20sinꙍt )

.
Figure 2
c Draw the re model for a voltage divider bias configuration and CO2 PO1 08
derive expressions for input impedance, output impedance and
voltage gain.

OR
2 a For the transfer characteristics shown in figure3 identify and CO2 PO2 06
analyze the circuit also obtain the output voltage waveform if the
input voltage is 50sinwt, (consider ideal diodes)
Figure 3
b For the circuit shown in the figure 4. determine the following CO3 PO2 10
parameters if r0 = ∞ and for r0 =50KΩ
i) re ii) Zi iii)Z0 iv)Av

Figure 4
CO2 PO1 04
c Determine output voltage vo for the network of Figure. 5 for the
input indicated, sketch the input and output voltage waveform.

Figure 5

UNIT - II
3 a) With a neat block diagram derive the expressions for gain with CO2 PO1 08
feedback, input impedance and output impedance for current
series feedback configuration
b) Calculate gain, input and output admittance for current series CO2 PO1 06
feedback amplifier with A= -300, Ri= 1.5KΩ, RO= 50KΩ and
feedback fraction β= -1/15
c) Derive an expression for miller effect induced input and output CO2 PO1 06
capacitance for an inverting amplifier
UNIT - III
4 a) A class B power amplifier output stage is required to deliver an CO3 PO2 10
average power of 100W into a 16 Ω load. The power supply
should be 4V greater than the corresponding peak sine-wave
output voltage. Determine the power supply voltage required (to
the nearest volt in the appropriate direction), the peak current from
each supply, the total supply power, and the power conversion
efficiency. Also determine the maximum possible power
dissipation in each transistor for a sinewave input.
b) With a neat circuit diagram, explain the working of class B push CO1 - 06
pull power amplifier
c) Calculate the total harmonic distortion for an output signal CO2 PO1 04
having fundamental amplitude of 2.5V, second harmonic
amplitude of 0.25V, third harmonic amplitude of 0.1V and fourth
harmonic amplitude of 0.05V.

UNIT - IV
5 a) The NMOS transistors in the circuit of Fig. 5 have Vt, == 1 V, CO3 PO2 10
µnCox == 120 µA/v2, λ= 0, and L1= L2 = 1 µm. Find the required
values of gate width for each of Q1 and Q2, and the value of R, to
obtain the voltage and current values indicated.

Figure 5
b) Derive an expression for the drain current of NMOS transistor CO2 PO1 10
operating in (i) Triode region and (ii) Saturation region
UNIT - V
6 a) Derive an expression for transconductance of the NMOS transistor CO2 PO1 10
2ID
and show that the transconductance 𝑔𝑚 = 2𝑉𝑜𝑣
b) Derive the terminal parameters for the amplifier circuit which does CO3 PO2 10
not produce phase reversal at the output
OR
7 a) Derive an expression for i) input impedance ii)output impedance CO2 PO1 10
iii)voltage gain and overall voltage gain for a common source
amplifier with source resistance
b) Identify the circuit shown in the figure 9, explain its significance CO3 PO2 10
in biasing the MOS amplifier

Figure 9

******

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