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Week 7 Lecture Material_watermark.pdf

The document provides an overview of sequential circuits, specifically focusing on registers and shift registers, including their structure, operation, and applications. It explains various types of registers, such as standard and universal shift registers, and their uses in data transfer and pseudo-random number generation. Additionally, it discusses counters, particularly asynchronous ripple counters and decade counters, detailing their functioning and timing diagrams.
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0% found this document useful (0 votes)
12 views99 pages

Week 7 Lecture Material_watermark.pdf

The document provides an overview of sequential circuits, specifically focusing on registers and shift registers, including their structure, operation, and applications. It explains various types of registers, such as standard and universal shift registers, and their uses in data transfer and pseudo-random number generation. Additionally, it discusses counters, particularly asynchronous ripple counters and decade counters, detailing their functioning and timing diagrams.
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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SR to D

EL
PT
D to SR

EL
PT
JK to T

EL
PT
Sequential circuit example
A0

EL
2-to-1 SET
MUX
D Q

A1

CLR Q

Clock

1 2 3 4 5 6 7 8 9 10
Clock

PT
A0

A1

D
Q
Sequential circuit example

EL
SET
D Q

CLR Q

Clock

1 2 3 4 5 6 7 8 9 10
Clock

Q’

Q
PT
Registers

EL
• A collection of 2 or more D flip flops with a common clock
• Registers are often used to store a collection of related bits
(e.g. a byte of data in a computer)

Clear

CLK
Clr
D Q

IN1
PT
OUT1

Clr
D Q

IN2
OUT2

Clr
D Q

IN3
OUT3

Clr
D Q

IN4
OUT4

6
A “standard” 4-bit register IC

EL
PT
7
A “standard” 8-bit register IC

EL
PT
8
Registers with 3-state outputs

EL
PT
(a) Symbol (b) Functional Diagram

9
A “standard” 8-bit register with 3-state outputs

EL
PT
10
Registers with clock enable

EL
Out 0 D Out0
In0 1
8 CE
Q
Q CK
ClrN Clr ClrN
CE D 0
In1 D Out1
1

PT
8 Q
Load Clk In CK

(a) Symbol
0 D Out7
In7 1 Q
Clk CK

11
A standard 8 bit register with clock
enable (= “gated” clock)

EL
PT
12
Registers application: Data Transfers

EL
PT
13
Shift Registers

EL
• It is a register that stores input values in sequence. At each clock tick
the values stored are shifted from one flip flop to the adjacent

PT
14
Shift Registers (cont’d)

EL
PT
15
Shift Registers (cont’d)

EL
PT
16
Shift registers (cont’d)

EL
PT
17
Universal shift register

EL
– serial or parallel inputs
– serial or parallel outputs
– permits shift left or right
– shift in new values from left or right
clear sets the register contents
output and output to 0

clear
left_out
left_in
s0
s1 PT Universal
Shift Register

input
right_out
right_in
clock
s1 and s0 determine the shift function

s0
0
0
1
1
s1
0
1
0
1
function
hold state
shift right
shift left
load new input

18
EL
Shift Register Applications

PT
Applications

EL
Ring counters
Johnson counters
Pseudo-random binary sequences and encryption
Ready-made shift registers are available as integrated circuits, such as the ’165

Conversion of data from serial to parallel and vice versa

PT
Large-scale devices such as ‘universal asynchronous receiver transmitters’
(UARTs) are based on shift registers
Same functions available in microcontrollers (‘shift’ and ‘rotate’ instructions)
Basic shift register
A basic shift register is simply a chain of D flip-flops with a common clock.

EL
serial D Q D Q D Q D Q serial
input output
A B C D
clock

Each flip-flop transfers its D input to its Q output at a clock transition.

PT
• The effect is to transfer data along the register, one flip-flop per clock cycle.

This type of register is called a serial input-serial output (SISO).


Timing for a shift register
clock

EL
input

QA

QB

QC
QD PT tpd
Pattern in successive flip-flops moves to the right with each clock cycle to shift the pattern into and out of the register.
Timing for a shift register
clock

EL
input

QA

QB
QC

QD PTtpd
input
0
1
1
QA
0
1
1
QB
0
0
1
QC
0
0
0
QD
0
0
0
1 1 1 1 0
0 0 1 1 1
Applications of a basic shift register
1. Delay line — N stages delay the signal by N clock cycles

EL
2. Multiplication and division by powers of 2, because this just requires a shift of the binary
number (like multiplication or division by 10 in decimal)
Example: decimal 3 x 4 = 12 becomes 11 x 100 = 1100 in binary The arithmetic logic
unit (ALU) of a computer processor uses a shift register for this purpose.
Warning: the ‘sense’ of a shift — left or right — is usually based on its effect on binary

PT
numbers written in the usual way. For example,
11 → 1100 is called a left shift. This is clearer if both numbers are written with 8-bits as
00000011 → 00001100. Similarly, dividing by 2 such as 00010110 → 00001011 is a right
shift.
Pseudo-random number generator
A ring counter with feedback through an exclusive-or gate makes a simple pseudo-random
number generator.

EL
D Q D Q D Q D Q output

• Pseudo-random sequences of 1s and 0s have many applications, notably in encryption.


They appear to be random over ‘short’ times but the sequence eventually repeats, hence

PT
the more accurate term ‘pseudo-random’.
• Also, they can be reproduced perfectly if you know both:
• the method used to generate the sequence
• the state in the sequence at which to start
• This is an important feature! — see next sheet.
• The circuit above has a period of 24 – 1 = 15 (the missing state is 0000 —why?).
Pseudo-random binary sequences and encryption
your data (plain text) pseudo-random binary sequence

EL
sender exclusive or

transmit data over looks like binary


insecure link ‘noise’ — apparently
random

receiver
PT ?
Pseudo-random binary sequences and encryption
your data (plain text) pseudo-random binary sequence

EL
sender exclusive or

transmit data over looks like binary


insecure link ‘noise’ — apparently
random

receiver
PT ?
same pseudo-random binary sequence

exclusive or

your data in plain text again


if you exclusive-or a bit
with the same value (0 or
1) twice, you get the initial
value back again.
Transmission of data — serial format
Data often has to be transmitted from one computer to another, or from a computer to peripheral equipment
(printer, modem, …). This can be done in:

EL
• serial format, one bit at a time
• parallel format, several bits at a time (e.g. byte at a time, 8 bits)

Serial format is most commonly used because it is simpler. Only a few wires are needed:
• traditional serial ‘COM’ ports (RS-232) need only 3 wires (transmitted data, received data and ground
— but more may be used for control)

bit stream
PT
• universal serial bus (USB, common on modern computers) uses 4 wires (two for differential data
plus power and ground)

Traditional serial transmission was slow but modern systems use much faster rates (USB version 1 up
to 12 Mbits per second, FireWire 1 up to 400 Mbits per second), version 2 of both even faster.
simple serial 1 0 0 1 1 0 1 1 0 1 0 1
Parallel data

EL
Where higher speed is required, several bits (usually a small number of bytes, each
of 8 bits) may be moved at once. More complicated connections are needed — more
wires. Common applications include:
• inside the processor itself, e.g. our microcontroller handles bytes
• inside a computer system on the bus (e.g. PCI) and interfaces to disk drives

PT
(e.g. e.g. SCSI or IDE)— but these are now mainly serial

Interfaces have changed to serial because it is hard to ensure that all bits on a
parallel bus arrive at the same time at the high speed of modern systems.
Parallel data
Where higher speed is required, several bits (usually a small number of bytes, each of 8 bits) may be moved
at once. More complicated connections are needed — more wires. Common applications include:

EL
• inside the processor itself, e.g. our microcontroller handles bytes
• inside a computer system on the bus (e.g. PCI) and interfaces to disk drives (e.g. e.g. SCSI or
IDE)— but these are now mainly serial

Interfaces have changed to serial because it is hard to ensure that all bits on a parallel bus arrive at the same
time at the high speed of modern systems.

PT
How do you interface a serial device to a computer?
How do we interface an external device that transmits serially with the bus of a computer that transfers one
byte (8 bits) at a time?
• Use a shift register.
In practice this would almost certainly be buried inside a larger circuit called a UART (universal asynchronous
receiver transmitter) or something similar.
Use of shift register to serialize data
parallel data in

EL
parallel load
D Q D Q D Q D Q serial
output
A B C D
Extra logic is added to the basic shift register so that all the flip-flops can be loaded in parallel

PT
(simultaneously), controlled by a shift/load input.
Once the data have been loaded, the clock is enabled and the values are shifted once per clock cycle. This
causes the input data to be transferred to the output, one bit at a time — serial output (PISO).
The opposite process is used to read in serial data, fill up the shift register, and transfer it in parallel to a bus
when the register is full (SIPO).
The register can also be parallel input – parallel output (PIPO).
EL
Asynchronous and Synchronous Counters

PT
32
Counters

EL
* Counters are important digital electronic circuits.
* They are Sequential logic circuits because timing is obviously
important and they need a memory characteristic.
* Digital counters have the following important characteristics,
1. Maximum number of count
2.
3.
4. PT
Up-Down Count
Asynchronous or Synchronous Operation
Free-Running or Self-Stopping

33
Asynchronous/Ripple Counter

EL
• Asynchronous counters are commonly referred to as ripple counter because
the effect of the input clock pulse is first “felt” by first flip-flop (FF0).
• Cannot get to the second flip-flop (FF1) immediately because of the
propagation delay through FF0.
• So the effect of an input clock pulse “ripples” through the counter, taking some

PT
time, due to propagation delays, to reach the last flip-flop.

Only the first FF receive clock pulse from the source ( clock genarator), others FFs
receive clock pulse from either Q or Q’ of prior FF

34
Asynchronous/Ripple Counter

EL
Propagation delays in a 3-bit asynchronous (ripple-clocked) binary counter.

PT
35
Asynchronous/Ripple Counter
Three-bit asynchronous binary counter and its timing diagram for one cycle.

EL
Clk pulse Q2 Q1 Q0

0 0 0 0

1 0 0 1

2 0 1 0

3 0 1 1

PT
4 1 0 0

5 1 0 1

6 1 1 0

7 1 1 1

8 (REPEAT) 0 0 0

36
Asynchronous/Ripple Counter
Four-bit asynchronous binary counter and its timing diagram. CLK Q3 Q2 Q1 Q0

EL
PLUSE

0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1

PT
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
16 0 0 0 0
REPEAT

37
Asynchronous Decade Counter

EL
• The Modulus of a counter is the number of unique states that the counter will sequence
through.
• Counter can also be designed to have a number of states in their sequence that is less
than the maximum of 2n.
• Counters with the states in their sequence are called decade counters.


PT
To obtain a truncated sequence, it is necessary to force the counter to recycle before
going through all of its possible states.
One way to make the counter recycle after the count of nine (1001) is to decode count
ten (1010) with a NAND gate and connect the output of the NAND gate to the clear (CLR)
inputs of the flip-flops. The inputs the NAND gate are from the Q output from FF1 and
FF3 ( from 1010 -- FF3FF2FF1FF0)

38
Asynchronous Decade Counter CLK Q3 Q2 Q1 Q0
An asynchronously clocked decade counter with asynchronous recycling. PLUSE

0 0 0 0 0

EL
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0

PT
9 1 0 0 1
10 GLITCH 0 0 0 0

11 0 0 0 1
12 0 0 1 0
13 0 0 1 1
14 0 1 0 0
15 0 1 0 1
16 0 1 1 0

39
Synchronous binary Counter
The term Synchronous refers to events that have a fixed time relationship with each other

EL
AND receive cllock pulse from a common source
2-bit synchronous binary counter.

PT
40
Synchronous binary Counter

EL
Clk pulse Q2 Q1 Q0
A 3-bit synchronous binary counter.
0 0 0 0

1 0 0 1

2 0 1 0

3 0 1 1

PT
4 1 0 0

5 1 0 1

6 1 1 0

7 1 1 1

8 (REPEAT) 0 0 0

41
Synchronous binary Counter CLK Q3 Q2 Q1 Q0

EL
PLUSE

0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
A 4-bit 7 0 1 1 1

PT
synchronous 8 1 0 0 0
binary counter 9 1 0 0 1
and timing 10 1 0 1 0
diagram. Points 11 1 0 1 1
where the AND 12 1 1 0 0
gate outputs are 13 1 1 0 1

HIGH are 14 1 1 1 0

indicated by the 15 1 1 1 1

shaded areas. 16 0 0 0 0
REPEAT

42
Synchronous Counter Design

EL
Several methods are available that follow arbitrary sequence.
Here we will learn one common method using JK flip-Flops.
In synchronous counters all the FF’s are clocked at the same time.

PT
J-K Excitation Table
Before begin the designing we must know the operation of the
J-K FF, let us analysis Truth table for 74LS76 IC (JK flip-flop) and its excitation table.

43
JK FF Excitation Table:

EL
PRESENT NEXT J K

0 0 0 X

0 1 1 X

PT
1

1
0

1
X

X
1

44
Synchronous Counter Design

EL
J-K Excitation Table
TRANSITION PRESENT NEXT STATE
AT OUTPUT STATE Q(N) Q(N+1) J K

0 0 0 0 0 X
0 1 0 1 1 X

PT
1 0 1 0 X 1
1 1 1 1 X 0

0 to 0 TRANSITION; FF’s Present status is 0 and it should remain in 0 when a clock pulse is applied.
That can be either J=K=0 status or J=0,K=1.
That mean J=0 and K=0 or 1. That is, J=0 and K=X(don’t care)

45
Synchronous Counter Design

EL
PT
46
Synchronous Counter Design

EL
Design Procedure
Given a Counter sequence, C B A
0 0 0
0 0 1
0 1 0

PT 0
1
0
0
1
0
0
0
etc.
1
0
0
1

47
Synchronous Counter Design / Example (1)

EL
STEP -1
Draw the state transition diagram showing all the possible states, including those that are
not part of the desired counting sequence

PT
48
Synchronous Counter Design / Example (1) ….cont.

EL
STEP -2
Use the state transition diagram to set up a table that lists all PRESENT states and their NEXT
states Present state Next state
C B A C B A
1 0 0 0 0 0 1
2 0 0 1 0 1 0

PT 3
4
5
6
7
8
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0

49
Synchronous Counter Design / Example (1) ….cont.
STEP -3

EL
Add a column to this table for each J and K input. For each PRESENT state, indicate the
level required at each J and K input in order to produce the transition to the NEXT state.
Present state Next state
C B A C B A jC kC jB kB jA kA
1 0 0 0 0 0 1 0 X 0 X 1 X
2 0 0 1 0 1 0 0 X 1 X X 1
3
4
5
6
7
8
0
0
1
1
1
1
PT 1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
1
X
X
X
X
X
X
1
1
1
1
X
X
0
0
X
X
0
1
X
X
1
1
1
X
0
X
0
X
X
1
X
1
X
1

50
Synchronous Counter Design / Example (1) ….cont.

EL
STEP- 4
Design the logic expression to generate the level required at each J and K, using K-maps.

Present state
A A
C B A jA kA A A
0 0 0 1 X BC 1 X
BC
0 0 1 X 1
X 1

PT
0 1 0 1 X BC 0 X BC X 1
0 1 1 X 1 0 X BC X X
1 0 0 0 X
BC
BC X 1
1 0 1 X 1 BC 1 X
1 1 0 0 X kA = 1
1 1 1 X 1 jA= C

51
Synchronous Counter Design / Example (1) ….cont.

EL
STEP- 4 …..cont.
Present state
C B A jB kB
0 0 0 0 X
A A 0 0 1 1 X
BC 0 1 0 1 0 X 0
BC 0 0 0 1 1 X 1 A

PT
A
BC X X 1 0 0 X X BC X X
BC X X 1 0 1 X X
1 1 0 X 1
BC X X
jB = A C 1 1 1 X 1 BC 1 1
BC 0 1
kB = A+C

52
Synchronous Counter Design / Example (1) ….cont.

EL
STEP- 4
…..cont. Present state
C B A jC kC
0 0 0 0 X A A
A A 0 0 1 0 X
BC
0 1 0 0 X
X X
BC 0 0
0 1 1 1 X BC 1 1

PT
BC X X BC 1 1
1 0 0 0 1
BC X X 1 0 1 X 1 BC X X
BC 0 1 1 1 0 0 1
1 1 1 X 1 kC = 1
jC = AB

53
Synchronous Counter Design / Example (1) ….cont.
SETP -5

EL
Finally to implement the final expressions.

PT
54
Synchronous Counter Design / Example (2)

EL
Design a JK synchronous counter that has the following
sequence:000,010,101,110 and repeat. The undesired states 001,011,100
and 111 must always go to 000 on the next clock pulse.

STEP -1 :State Transition Diagram

PT
55
Synchronous Counter Design / Example (2) ….cont.

EL
STEP- 2 : Table to list PRESENT and NEXT status

PT
56
Synchronous Counter Design / Example (2) ….cont.

EL
STEP- 3 : Table indicate the Level required at each J and K inputs in order to produce
the transition to the NEXT

PT
57
Synchronous Counter Design / Example (2) ….cont.

EL
STEP- 4 :Design the logic circuits to generate the levels required at each J and K
inputs

PT
58
Synchronous Counter Design / Example (2) ….cont.

EL
STEP- 5 :Simplify the SOP expression using K-maps

PT
59
Synchronous Counter Design / Example (2) ….cont.

EL
PT
60
Synchronous Counter Design / Example (3)

EL
? Design a JK synchronous counter that has the following
sequence:000,010,101,110 and repeat. For undesired states their NEXT
states can be DON’T CARES.
STEP -1 :State Transition Diagram

PT
61
Synchronous Counter Design / Example (3) ….cont.

EL
STEP- 2 : Table to list PRESENT and NEXT status

PT
62
Synchronous Counter Design / Example (3) ….cont.

EL
STEP- 3 : Table indicate the Level required at each J and K inputs in order to produce
the transition to the NEXT

PT
63
Synchronous Counter Design / Example (3) ….cont.

EL
STEP- 4 :Design the logic circuits to generate the levels required at each J and K
inputs

PT
64
Synchronous Counter Design / Example (3) ….cont.

EL
STEP- 5 :Simplify the SOP expression using K-maps

PT
65
Synchronous Counter Design / Example (3) ….cont.

EL
PT
66
Synchronous Counter Design / Example (4) ….cont.

EL
Objective:
To design a 3 bit counter (D FF) with the following count sequence 7,6,5,4,1. All unwanted stages go to 7.
Output sequence 7,6,5,4,1
In 3 bits format: 111,110, 101, 100, 001
State transition diagram:

PT
000
010

011
111
110

001 100 101

67
Synchronous Counter Design / Example (4) ….cont.

EL
D Flip Flop Excitation Table:

PRESENT NEXT D

0 0 0

PT
0 1 1
1 0 0
1 1 1

68
Synchronous Counter Design / Example (4) ….cont.

EL
OUTPUT INPUT
PRESENT STATE NEXT STATE C B A
C B A C B A DC DB DA

0 0 0 1 1 1 1 1 1
0 0 1 1 1 1 1 1 1

PT
0 1 0 1 1 1 1 1 1
0 1 1 1 1 1 1 1 1
1 0 0 0 0 1 0 0 1
1 0 1 1 0 0 1 0 0
1 1 0 1 0 1 1 0 1
1 1 1 1 1 0 1 1 0

69
Synchronous Counter Design / Example (4) ….cont.

EL
K- Map

A A A A A
A
CB 1 1
CB 1 1
CB 1 1
CB 1 1
CB 1 1
CB 1 1
CB 1 1

PT
CB 0 1
CB 0 1 CB 1 0
CB 0 0 1 0
DC =A+ CB
C’ + B DB = AB + C’ DA = A’ + C’

70
Synchronous Counter Design (T Flip Flop based design / Example (5) ….cont.

EL
T Flip Flop Excitation Table:

PRESENT NEXT T

PT
0 0 0

0 1 1

1 0 1

1 1 0

71
Synchronous Counter Design / Example (5) ….cont.

EL
T Flip Flop Input Function Table

OUTPUT INPUT
PRESENT STATE NEXT STATE C B A
C B A C B A TC TB TA
0 0 0 1 1 1 1 1 1
0 0 1 1 1 1 1 1 0

PT
0 1 0 1 1 1 1 0 1
0 1 1 1 1 1 1 0 0
1 0 0 0 0 1 1 0 1
1 0 1 1 0 0 0 0 1
1 1 0 1 0 1 0 1 1
1 1 1 1 1 0 0 0 1

72
Synchronous Counter Design / Example (5) ….cont.

EL
K- Map

A
A A A
A
A
1 1 1 1 1 0
CB CB CB
CB 1 1 CB 0 0 1 0
CB

PT
CB 0 0 CB 1 0
CB 1 1
CB 1 0 CB 0 0
CB 1 1
TC =A’B’ + TB = B’C’ +
C’ A’BC TA = A’ +
C

73
Ring Counter

EL
PT
Johnson Counter

EL
• Also known as the twisted-ring counter.
• Same as the ring counter except that the
inverted output of the last FF is connected to
the input of the first FF.

PT
• Counting sequence:
000100110111011001000
• A MOD-6 counter (twice the number of FFs)
MOD-6 Johnson Counter

EL
PT
State Transition Diagram

EL
PT
Binary Counter with Parallel Load

EL
PT
EL
Finite State Machine

PT Santanu Chattopadhyay
Electronics and Electrical Communication Engineering
Finite State Machine

EL
• An electronic machine which has
– external inputs
– externally visible outputs

PT
– internal state
• Output and next state depend on
– inputs
– current state
Abstract Model of FSM

EL
Machine is M = ( S, I, O,  )
S: Finite set of states
I: Finite set of inputs

PT
O: Finite set of outputs
: State transition function
• Next state depends on present input and present
state
Automata Model

EL
Registers
Current State Comb. Output
Logic
Input Next State

PT
CLK

– inputs from external world


– outputs to external world
– internal state
– combinational logic
FSM Example
down/on down/on
input/output up/off

EL
start
A B
state state

Legend up/off down/off


up/off
C D

PT
Input: up or down
Output: on or off
States: A, B, C, or D
down/off up/off
FSM Example
i0i1i2…/o0o1o2… 0/0 1/1 1/1

EL
00 01
S1S0 S1S0
Legend 0/0 0/0
0/0

PT
10 11

Input: 0=up or 1=down 1/0 1/0


Output: 1=on or 0=off
States: 00=A, 01=B, 10=C, or 11=D
Mealy Machine

EL
Registers
Current State
Comb. Output
Logic
Input Next State

PT
• Outputs and next state depend on both
current state and input
Moore Machine

EL
Comb.

Registers
Current State Logic Output
Comb.
Input Logic Next State

• PT
Outputs depend only on current state
Moore Machine FSM Example
up down down
input

EL
A B
state start off on
out out

Legend up down
up
C D

PT
Input: up or down
Output: on or off
States: A, B, C, or D
off
down
off
up
Mealy Machine FSM Example
down/on
input/output up/off down/on

EL
start
A B
state state

Legend up/off down/off


up/off
C D

PT
Input: up or down
Output: on or off
States: A, B, C, or D
down/off
up/off
Create a Logic Circuit for a Serial Adder
• Add two infinite input bit streams

EL
– streams are sent with least-significant-bit (lsb) first
…10110
…01111 …00101
– How many states are needed to represent FSM?

PT
– Draw and Fill in FSM diagram
Strategy:
(1) Draw a state diagram (e.g. Mealy Machine)
(2) Write output and next-state tables
(3) Encode states, inputs, and outputs as bits
(4) Determine logic equations for next state and outputs
Another look at D latch/flip-flop

EL
qold D qnew

PT
0 0 0
0 1 1 This is an example of a state diagram
more specifically a Moore machine
1 0 0
1 1 1 qnew = D
Another example - 2-bit counter

EL
Counter starts at 0 (green) and increments
each time the clock cycles, until it gets to
3 and then overflows back to 0.

Only input is the clock, we don’t show

PT
that. H L H Lnew
old old new
0 0 0 1
0 1 1 0
1 0 1 1
1 1 0 0
2-bit counter

EL
Hold Lold Hnew Lnew
0 0 0 1
0 1 1 0
1 0 1 1
1 1

PT 0 0

Lnew = Hold’Lold’ + HoldLold’ = Lold’

Hnew = Hold’Lold + HoldLold’


2-bit counter with reset

EL
R Hold Lold Hnew Lnew
0 0 0 0 1
0 0 1 1 0

PT
0 1 0 1 1
0 1 1 0 0
1 x x 0 0
Lnew = R’Hold’Lold’ + R’HoldLold’ Hnew = R’Hold’Lold + R’HoldLold’
= R’Lold’ = (R + Lold)’ = R’(Hold’Lold + HoldLold’)
2-bit counter with reset

EL
PT
Counter with 7-segment display

EL
Each segment in the display can be lit independently
to allow all 10 decimal digits to be displayed (also hex)

2-bit counter will need to display digits 0-3,

PT
so will output a 1 for each segment to be lit
for a given state
Counter with output functions

EL
R Ho Lo Hn Ln A B C D E F G
0 0 0 0 1 1 1 1 1 1 1 0
0 0 1 1 0 0 1 1 0 0 0 0
0 1 0 1 1 1 1 0 1 1 0 1

PT
0 1 1 0 0 1 1 1 1 0 0 1
1 x x 0 0 0 0 0 0 0 0 0
A = D = R’Ho’Lo’+R’HoLo’+R’HoLo = R’(Ho’Lo)’ B = R’ C = R’(HoLo’)’
E = R’Lo’ F = R’Ho’Lo’ = (R+Ho+Lo)’ G = R’Ho
7-segment output logic

EL
PT
Example - 101 lock

EL
B Ho Lo Hn Ln X
Combination lock with 101
being the combination 0 0 0 0 0 0
0 0 1 1 0 0
0 1 0 0 0 0
0 1 1 0 0 1

PT
B is input signal to the lock,
X is output signal to unlock
1
1
1
1
0
0
1
1
0
1
0
1
0
0
1
0
0
1
1
1
0
0
1
0
101 combination lock

EL
X = HoLo

Hn = B’Ho’Lo + BHoLo’

Ln = BHo’Lo + BHoLo’ + BHoLo


= BHo’Lo + BHoLo + BHoLo’ + BHoLo

PT
= BLo + BHo

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