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Characterization and Failure Analysis of Silicon Devices

The document discusses the challenges and techniques involved in the characterization and failure analysis of silicon devices, highlighting the complexities introduced by small feature sizes, new materials, and intricate device structures. It outlines various failure site location methods such as IDDQ testing, liquid crystal microscopy, and emission microscopy, as well as advanced imaging techniques like picosecond imaging circuit analysis and voltage contrast. The summary emphasizes the need for improved characterization tools to address the evolving landscape of integrated circuits.

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0% found this document useful (0 votes)
14 views

Characterization and Failure Analysis of Silicon Devices

The document discusses the challenges and techniques involved in the characterization and failure analysis of silicon devices, highlighting the complexities introduced by small feature sizes, new materials, and intricate device structures. It outlines various failure site location methods such as IDDQ testing, liquid crystal microscopy, and emission microscopy, as well as advanced imaging techniques like picosecond imaging circuit analysis and voltage contrast. The summary emphasizes the need for improved characterization tools to address the evolving landscape of integrated circuits.

Uploaded by

munnizza64
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Characterization and Failure Analysis

of Silicon Devices
Current and Future

Dieter K. Schroder
Dept. of Electrical Engineering
Arizona State University
Tempe, AZ

Introduction
„ Background
„ Failure site location
‹ IDDQ testing
‹ Liquid crystal
‹ Emission microscopy
‹ Picosecond imaging circuit analysis
‹ Voltage contrast
‹ Optical beam induced resistance change
„ Physical Analysis
‹ High resolution TEM
‹ Microprobing
Failure Analysis I’m trying to dig
up a defect
„ Physical analysis difficult
‹ Small feature size
‹ Complex device structure
‹ New materials
„ Failure site location
Where is the
‹ IC ⇒ circuit block ⇒ circuit element
defect?
⇒ contact/gate
„ Failure site location difficult
‹ Device complexity
‹ Reduced accessibility
z Flip-chip
z Increasing metal layers
z Dummy metal for chemical/
mechanical polishing
‹ Solution: back side localization Once the defect
is found, how to
Lgate = 60 nm analyze it?

Defect Density Trends


Defect Density (cm-2)

One defect
in 20 cm2!

Year
Courtesy of IC Knowledge, www.icknowledge.com
Failure Site Location
„ IDDQ testing
„ Liquid crystal
„ Emission microscopy
„ Picosecond imaging
circuit analysis
„ Voltage contrast
„ Optical beam induced
resistance change
„ Microprobing

IDDQ Testing
IDDQ
„ Quiescent drain current flowing
from power supply to ground
„ Device in quiescent state
Metal
„ 10-9 A range in quiescent state Bridging
Short
„ Increases due to defects
„ Mainly detects physical defects, VDD
is supplemental to logic testing Source-Drain
Short

Gate Oxide
Short

R. Rajsuman, Iddq Testing for CMOS VLSI, Proc. IEEE 88, 544-566, April 2000;
L.C. Wagner, Failure Analysis of Integrated Circuits, Kluwer, Boston, 1999
IDDQ Testing
„ Bridging shorts and gate oxide shorts are
detectable with IDDQ
„ Opens are more difficult or impossible to detect

Gate oxide short Metal bridging defect


⇒360 µA IDDQ ⇒5 µA IDDQ

Poly-poly short Large area defect


⇒5 mA IDDQ (28 transistors)
⇒620 µA IDDQ

Micrographs courtesy of IBM

Liquid Crystal Microscopy


„ Chip heated slightly below liquid crystal (LC) clearing
temperature Tc
„ LC is transparent below Tc , black above Tc
„ For ROCE 1510 (Hoffmann La Roche): Tc = 48°C
„ Chip voltage is pulsed for easier detection
Observer

Analyzer Polarizer

Lamp
Nematic
Liquid Phase
IC Crystal Isotropic Hot Spot
Phase
Heater

L.C. Wagner, Failure Analysis of Integrated Circuits, Kluwer, Boston, 1999


Liquid Crystal Microscopy

Hot spot due to


2.2 mW power
dissipation

3.5 mW
2.65 mW
2.2 mW
1.75 mW

Bipolar Junction Transistor


Poly-Si bridge causes hot spot
Courtesy of C.G.C. De Kort, Courtesy of N. Nenadovic,
Philips Research Laboratories DIMES, Delft University

Emission Microscopy (EMMI)


„ Image of circuit is
taken in ordinary light
„ Image of circuit is
taken in the dark with
circuit powered up;
defects appear as
bright spots
„ The two images
are superimposed,
showing defect
locations on the
circuit

C.G.C. de Kort, “Integrated Circuit Diagnostic Tools: Underlying


Physics and Applications,” Philips J. Res. 44, 295-327, 1989.
Emission Microscopy
„ Problem: latch-up of CMOS circuit
„ Frontside emission microscopy
gave light spots at the metal edge;
actual latch-up spot likely
somewhere under the metal
„ Device was thinned to 50-100 µm;
light emission was measured from
the back of the wafer ⇒ latch-up
initiation site

I = 30 mA (no latch-up) 50 mA (no latch-up) 70 mA (latch-up)

T. Kessler, F.W. Wulfert, and T. Adams, Diagnosing Latch-up


with Backside Emission Microscopy,” Semicond. Int. July 2000.

Picosecond Imaging Circuit Analysis


„ PICA utilizes light emission to analyze
device/circuit performance
‹ Can measure thousands of gates
simultaneously or observe one gate
‹ Non invasive, contactless
‹ No external excitation
„ Hot electron light emission is
coincident with MOSFET switching
„ During CMOS switching,
transient current flows Inverters
#1 #9
on time scale of ps 508 ps
Intensity

Each snapshot in this


shift register lasts 34 ps !

9.6 10.0 10.4 10.8


Time (ns)

Photos: www.research.ibm.com/topics/popups/serious/chip/html/pica.html
Picosecond Imaging Circuit Analysis
„ Problem: incorrect timing
at one particular output
pin; switched too slow
„ Was it transistor 25, gate 1,
gate 3 or interconnect
short or open ?
‹ Time-integrated emission
and optical waveform from
problem T25
‹ Time-integrated emission
and optical waveform from
good transistor
„ Localized the defect to T25

T. Lundquist and M. McManus, “Characterize Gate-Level Transistor


Performance with PICA,” Semicond. Int. 8, 249-254, July 2001.

Voltage Contrast
„ The electron beam is the probe
‹ Small, can contact very narrow lines
‹ No damage to lines; no capacitive loading
‹ Fast, can be programmed to probe entire chip
‹ Chip can be at wafer level or packaged (cover
removed)
‹ Can measure through insulator by capacitive coupling
‹ Can be used for visual inspection - SEM mode

„ Can measure
‹ Node voltages - mV range
‹ Voltage waveforms - subnanosecond time resolution
‹ Voltage contrast - can look at a portion of the chip and
by using stroboscopic techniques, can watch circuit
operation
Voltage Contrast
„ Voltage contrast: modulation of secondary electron
yield by voltages on conductors
„ SE yield is influenced by: θ E-beam
‹ Local electric field
‹ Topography - SE yield ~ 1/cos(θ)
‹ Material density
‹ Material work function

Retarding
Grid
Primary
Beam Detector
Secondary
Electrons

0V 0V 0V 0V +5 V 0V

Courtesy Siemens Corp.


M. Vallet and P. Sardin, “Electrical Testing for Failure Analysis:
E-Beam Testing”, Microelectron. Eng. 49, 157-167, 1999.

Voltage Contrast

x-y Defect Circuit timing


location information

y t
1 ns

x x
Courtesy of T.D. McConnell, Intel Corp.

Open via in contact chain


B. Fiordalice and D.W. Price, KLA-Tencor
Optical Beam Induced Resistance Change
„ Current I flows through line
„ Scanned laser irradiates the line Shorts
„ Heat leads to resistance ± ∆R
„ Current changes by ∆I = (∆R/R)I
„ ∆I is detected and displayed in
synchronism with laser scan

IR Laser Increased R

TV
Display
Metal line defects

I±∆I ∆I = (∆R / R )I ; ∆R ~ ∆T
I
Leakage current path

http://usa.hamamatsu.com/sys-failureanalysis/microamos/default.htm

OBIRCH
„ DRAM, VDD to ground
leakage path failure 5 µm

„ “Leakage” line is dark line


„ Short circuit is bright spot

Micrographs courtesy of Hamamatsu Photonics


Probe Diameter

Electrons

Ions

X-Rays

Light

Probes

1 10 100 1,000Å 1 10 100µm 1mm 1cm

Analytical Diameter

Physical Failure Analysis Challenges


„ Reduced feature size
„ Smaller defects
‹ Field- emission SEM
‹ Transmission electron microscopy Single dislocation
‹ Confocal microscopy
‹ Scanning probe microscopy

„ New materials – new failure mechanisms?


‹ Al⇒ Cu
‹ SiO2 ⇒ low K
‹ SiO2 ⇒ high K

Gate
Source Drain

Depletion
region Na
Substrate Images courtesy of T.J. Shaffner, NIST
Imaging of Single Bi Atoms in Si
„ The best TEM has resolution of 0.8 Å
„ Can see individual impurity atoms
Z=31 Z=33
E Beam
Scanning
Probe
Bi

EELS
EELS
Spectrometer
Spectrometer Courtesy of G. Duscher, North Carolina State University

Conductive Atomic Force Microscopy


„ C-AFM measures sample topography and current
„ Allows current-voltage measurements

Field Gate
Oxides

AFM Topograph Tunnel current image,


1 µm scan, 0.5 pA
current scale

Image courtesy A. Olbrich, Infineon


Scanning Probe Microscopy
„ Scanning probes can have 0.13 µm Technology
atomic resolution
„ Conductive atomic force
microscopy (C-AFM)
‹ Sample flatness
‹ Current-voltage
„ Scanning capacitance probe AFM Topograph
‹ Doping profiles
„ Micro spreading resistance
I≠0
‹ Doping profiles Contact B

I=0
AFM Current
High resistance
layer

J.C. Lee and J.H. Chuang, Microelectr. Rel. 43, 1687 (2003)

Summary
„ Failure analysis made difficult by today’s ICs
‹ 6 - 8 metal layers
‹ Small feature size: < 0.1x0.1 µm2 gates, vias
‹ Thin insulators: 10 - 20 Å
„ New materials
‹ Low K dielectrics; Cu metallization
‹ Silicon-on-insulator: tSi = 200 - 500 Å
‹ Strained Si: composition, stress
„ Push existing characterization tools to the limit
„ Develop new tools
‹ High resolution TEM
‹ Probe microscopy
‹ Picosecond emission microscopy

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