SiC476, SiC477, SiC478, SiC479

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4.5 V to 55 V Input, 3 A, 5 A, 8 A, 12 A
microBUCK® DC/DC Converter
FEATURES
• Versatile
- Single supply operation from 4.5 V to 55 V
input voltage
- Adjustable output voltage down to 0.8 V
- Scalable solution 3 A (SiC479), 5 A (SiC478),
8 A (SiC477), 12 A (SiC476)
- Output voltage tracking and sequencing with
pre-bias start up
- ± 1 % output voltage accuracy at -40 °C to +125 °C
• Internal compensation
• Highly efficient
LINKS TO ADDITIONAL RESOURCES - 98 % peak efficiency
- 4 μA supply current at shutdown
- 156 μA operating current not switching
Design Tool Evaluation
Boards
Design Tools • Highly configurable
- Adjustable switching frequency from 100 kHz to 2 MHz
DESCRIPTION - Adjustable soft start and selectable preset 100 %, 75 %,
The SiC47x is a family of wide input voltage high efficiency and 50 % current limit
synchronous buck regulators with integrated high side and - 2 modes of operation, forced continuous conduction or
power save mode
low side power MOSFETs. Its power stage is capable of
• Robust and reliable
supplying high continuous current at up to 2 MHz switching - Output over voltage protection
frequency. This regulator produces an adjustable output - Output under voltage / short circuit protection with auto
voltage down to 0.8 V from 4.5 V to 55 V input rail retry
to accommodate a variety of applications, including - Power good flag and over temperature protection
computing, consumer electronics, telecom, and industrial. - Supported by Vishay PowerCAD online design
simulation
SiC47x’s architecture delivers ultrafast transient response • Material categorization: for definitions of compliance
with minimum output capacitance and tight ripple regulation please see www.vishay.com/doc?99912
at very light load. The device is internally compensated and
is stable with any capacitor. No external ESR network is APPLICATIONS
required for loop stability purpose. The device also • Industrial and automation
incorporates a power saving scheme that significantly • Home automation
• Industrial and server computing
increases light load efficiency. The regulator integrates a full • Networking, telecom, and base station power supplies
protection feature set, including over current protection • Wall transformer regulation
(OCP), output overvoltage protection (OVP), short circuit • Robotics
protection (SCP), output undervoltage protection (UVP) and • High end hobby electronics: remote control cars, planes,
and drones
thermal shutdown (OTP). It also has UVLO for input rail and • Battery management systems
a user programmable soft start. • Power tools
The SiC47x family is available in 3 A, 5 A, 8 A, 12 A pin • Vending, ATM, and slot machines
compatible 5 mm by 5 mm lead (Pb)-free power enhanced
Axis Title
MLP55-27L package. 100 10000
VIN = 24 V, VOUT = 12 V
TYPICAL APPLICATION CIRCUIT 98
96
94
eff - Efficiency (%)

Input CBOOT 1000

EN

PGOOD

BOOT

VCIN 92
4.5 VDC to 60 VDC Phase VOUT
2nd line
1st line
2nd line

VIN = 48 V, VOUT = 12 V
VIN SW
SiC476 90
VDD SiC477 VIN = 24 V, VOUT = 5 V
CIN SiC478 VOUT
VDRV SiC479 88
SS NC Rup 100
VFB COUT 86
ILIMIT

Css
MODE NC Rdown 84
AGND
PGND
fSW

VIN = 48 V, VOUT = 5 V
82
RMODE
Rfsw 80 10
0 1 2 3 4 5 6 7 8
IOUT - Output Current (A)
Fig. 1 - Typical Application Circuit Fig. 2 - SiC477 Efficiency vs. Output Current

S21-1151-Rev. F, 06-Dec-2021 1 Document Number: 77113

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PIN CONFIGURATION

27 MODE

27 MODE
23 AGND

23 AGND
20 VOUT

20 VOUT
26 VDD
25 ILIM
24 fSW

26 VDD
22 VFB
21 NC

22 VFB

25 ILIM
21 NC

24 fSW
VCIN 1 IJ 19 SS 1 VCIN
SS 19
28 AGND
PGOOD 2 28 AGND 18 NC NC 18 2 PGOOD
17 PGND PGND 17
EN 3 3 EN
16 VDRV VDRV 16
BOOT 4 15 GL GL 15 4 BOOT

30 14 SW SW 14 29
PHASE 5 VIN 29 PGND 30 PGND VIN 5 PHASE
13 SW SW 13
PHASE 6 ķ ķ 6 PHASE
12 SW SW 12

PGND 11
PGND 10
PGND 9

VIN 8

VIN 7
VIN 7

VIN 8

PGND 9
PGND 10
PGND 11

Fig. 3 - Pin Configuration

PIN DESCRIPTION
PIN NUMBER SYMBOL DESCRIPTION
Supply voltage for internal regulators VDD and VDRV. This pin should be tied to VIN, but can also be
1 VCIN
connected to a lower supply voltage (> 5 V) to reduce losses in the internal linear regulators
Open-drain power good indicator - high impedance indicates power is good. An external pull-up
2 PGOOD
resistor is required
Enable pin. Tie high / low to enable / disable the IC accordingly. This is a high voltage compatible pin,
3 EN
can be tied to 55 V
4 BOOT High side driver bootstrap voltage
5, 6 PHASE Return path of high side gate driver
7, 8, 29 VIN Power stage input voltage. Drain of high side MOSFET
9, 10, 11, 17, 30 PGND Power ground
12, 13, 14 SW Power stage switch node
15 GL Low side MOSFET gate signal
Supply voltage for internal gate driver. When using the internal LDO as a bias power supply, VDRV is
16 VDRV
the LDO output. Connect a 4.7 μF decoupling capacitor to PGND
18, 21 NC No connection internally
Set the soft start ramp by connecting a capacitor to AGND. An internal current source will charge the
19 SS
capacitor
20 VOUT Output voltage sense point for internal ripple injection components
Feedback input for switching regulator used to program the output voltage - connect to an external
22 VFB
resistor divider from VOUT to AGND
23, 28 AGND Analog ground
24 fSW Set the on-time by connecting a resistor to AGND
25 ILIMIT Set the current limit by connecting ILIMIT pin to AGND, float or VDD
26 VDD Bias supply for the IC. VDD is an LDO output, connect a 1 μF decoupling capacitor to AGND
27 Mode Set various operation modes by connecting a resistor to AGND. See specification table for details

S21-1151-Rev. F, 06-Dec-2021 2 Document Number: 77113

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ORDERING INFORMATION
PART NUMBER PACKAGE MARKING CODE
SiC476ED-T1-GE3 PowerPAK® MLP55-27L SiC476
SiC476EVB-D Reference board
SiC477ED-T1-GE3 PowerPAK® MLP55-27L SiC477
SiC477EVB-D Reference board
SiC478ED-T1-GE3 PowerPAK® MLP55-27L SiC478
SiC478EVB-E Reference board
SiC479ED-T1-GE3 PowerPAK® MLP55-27L SiC479
SiC479EVB-E Reference board

PART MARKING INFORMATION

= pin 1 indicator
P/N = part number code
P/N = Siliconix logo
= ESD symbol
LL F = assembly factory code
Y = year code
FYWW WW = week code
LL = lot code

ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)

ELECTRICAL PARAMETER CONDITIONS LIMITS UNIT
VCIN, VIN Reference to PGND -0.3 to 60
EN Reference to PGND -0.3 to 55
SW / PHASE Reference to PGND -0.3 to 60
SW / PHASE (AC) 100 ns -10 to 66
VDRV Reference to PGND -0.3 to 6
V
VDD Reference to AGND -0.3 to VDRV + 0.3
BOOT -0.3 to VPHASE + VDRV
AGND to PGND -0.3 to 0.3
VOUT Reference to PGND 30
All other pins Reference to AGND -0.3 to VDD + 0.3
Temperature
Junction temperature TJ -40 to +150
°C
Storage temperature TSTG -65 to +150
Power Dissipation
Thermal resistance from junction to ambient 12
°C/W
Thermal resistance from junction to case 2
ESD Protection
Human body model, JESD22-A114 2000
Electrostatic discharge protection V
Charged device model, JESD22-A101 500

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating/conditions for extended periods may affect device reliability.

S21-1151-Rev. F, 06-Dec-2021 3 Document Number: 77113

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RECOMMENDED OPERATING CONDITIONS (all voltages referenced to GND = 0 V)

PARAMETER MIN. TYP. MAX. UNIT
Input voltage (VIN) 4.5 - 55
Control input voltage (VCIN) (1) 4.5 - 55
Enable (EN) 0 - 55
V
Bias supply (VDD) 4.75 5 5.25
Drive supply voltage (VDRV) 4.75 5.3 5.55
Output voltage (VOUT) 0.8 - 15
Temperature
Recommended ambient temperature -40 to +105
°C
Operating junction temperature -40 to +125
Note
(1) For input voltages below 5 V, provide a separate supply to V
CIN of at least 5 V to prevent the internal VDD rail UVLO from triggering

ELECTRICAL SPECIFICATIONS (VIN = VCIN = 48 V, TJ = -40 °C to +125 °C, unless otherwise stated)
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Power Supplies
VIN = VCIN = 6 V to 55 V,
4.7 5 5.3
VEN = 5 V, not switching
VDD supply VDD V
VIN = VCIN = 5 V,
4.7 5 -
VEN = 5 V, not switching
VDD dropout VDD_DROPOUT VIN = VCIN = 5 V, IVDD = 1 mA - 150 - mV
VDD UVLO threshold, rising VDD_UVLO 3.75 4 4.25 V
VDD UVLO hysteresis VDD_UVLO_HYST - 150 - mV
Input current IVCIN Non-switching, VFB > 0.8 V - 156 200
μA
Shutdown current IVCIN_SHDN VEN = 0 V - 4 8
Controller and Timing
TJ = 25 °C 796 800 804
Feedback voltage VFB m/V
TJ = -40 °C to +125 °C (1) 792 800 808
VFB input bias current IFB - 2 - nA
Minimum on-time tON_MIN. - 45 100 ns
tON accuracy tON_ACCURACY -10 - 10 %
On-time range tON_RANGE 100 - 8000 ns
Minimum off-time tOFF_MIN. - 250 - ns
Soft start current ISS 2 5 7 μA
Zero crossing detection point ZCD LX-PGND -3 - 3 mV

S21-1151-Rev. F, 06-Dec-2021 4 Document Number: 77113

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ELECTRICAL SPECIFICATIONS (VIN = VCIN = 48 V, TJ = -40 °C to +125 °C, unless otherwise stated)
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Fault Protections
ILM tied to VDD - 13 -
SiC476 valley current limit ILM is not connect - 9.75 -
ILM tied to AGND - 6.5 -
ILM tied to VDD - 10 -
SiC477 valley current limit ILM is not connect - 7.5 -
ILM tied to AGND - 5 -
IOCP A
ILM tied to VDD - 6 -
SiC478 valley current limit ILM is not connect - 4.2 -
ILM tied to AGND - 3 -
ILM tied to VDD - 4 -
SiC479 valley current limit ILM is not connect - 3 -
ILM tied to AGND - 2 -
Output OVP threshold OVP - 20 -
VFB with respect to 0.8 V reference %
Output UVP threshold UVP - -80 -
OTPR Rising temperature - 150 -
Over temperature protection °C
OTPHYST Hysteresis - 35 -
Power Good
VFB_RISING_VTH_OV VFB rising above 0.8 V reference - 20 -
Power good output threshold %
VFB_FALLING_VTH_UV VFB falling below 0.8 V reference - -10 -
Power good hysteresis PGOOD_HYST 30 40 55 mV
Power good on resistance RON_PGOOD - 6 15 Ω
Power good delay time tDLY_PGOOD 15 25 35 μs
EN / MODE / Threshold
EN logic high level VEN_H 1.39 1.4 1.43
V
EN logic low level VEN_L 1.17 1.2 1.24
EN logic hysteresis VEN_HYS 153 200 244 mV
EN pull down resistance REN - 6 - MΩ
Mode pull up current IMODE - 5 - μA
Power save mode enabled, VDD, VDRV
Mode 1 - 2 -
Pre-reg on
Power save mode disabled, VDD, VDRV
Mode 2 - 301 -
Pre-reg on
RMODE kΩ
Power save mode disabled, VDRV Pre-reg
Mode 3 - 499 -
off, VDD Pre-reg on, provide external VDRV
Power save mode enabled, VDRV Pre-reg off,
Mode 4 - 1000 -
VDD Pre-reg on, provide external VDRV
Note
(1) Guaranteed by design

S21-1151-Rev. F, 06-Dec-2021 5 Document Number: 77113

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FUNCTIONAL BLOCK DIAGRAM

VCIN BOOT VIN

Sync.
VDRV
rectifier
Regulator
VDD
VDD UVLO HS UVLO

EN Enable

fSW ton
On time
generator min. toff
VDD HS
driver
5 μA
PHASE

MODE
MODE SW
Control
VOUT logic VDRV
PHASE Ramp
PWM
Comp

VDD LS
0.8 V driver
5 μA Reference
PHASE Zero
crossing GL
SS OTA

PGOOD

VFB Over voltage

under voltage
VFB Power
ILIMIT Over Over good
PHASE current temperature

AGND PGND

Fig. 4 - Functional Block Diagram

OPERATIONAL DESCRIPTION
Device Overview • Dedicated enable pin for easy power sequencing
SiC47x is a high efficiency synchronous buck regulator • Power good open drain output
family capable of delivering up to 12 A continuous current. • This device is available in MLP55-27L package to deliver
The device has programmable switching frequency of high power density and minimize PCB area
100 kHz to 2 MHz. The control scheme is based on voltage
mode constant on time. It delivers fast transient response Power Stage
and minimizes external components. Thanks to the internal SiC47x integrates a high performance power stage with a
current ramp information, no high ESR output bulk or virtual n-channel high side MOSFET and a n-channel low side
ESR network is required for the loop stability. This device MOSFET optimized to achieve up to 98 % efficiency.
also incorporates a power saving feature by enabling diode The power input voltage (VIN) can go up to 55 V and down
emulation mode and frequency fold back as the load as low as 4.5 V for power conversion.
decreases.
SiC47x has a full set of protection and monitoring features:
• Over current protection in pulse-by-pulse mode
• Output overvoltage protection
• Output undervoltage protection with device going into
hiccup mode
• Over temperature protection with hysteresis

S21-1151-Rev. F, 06-Dec-2021 6 Document Number: 77113

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Control Scheme Power-Save Mode and Mode Pin Operation
SiC47x employs a voltage - mode COT control mechanism To improve efficiency at light-loads, SiC47x provides a set
in conjunction with adaptive zero current detection which of innovative implementations to eliminate LS re-circulating
allows for power saving in discontinuous conduction mode current and switching losses. The internal zero crossing
(DCM). The switching frequency, fSW, is set by an external detector (ZCD) monitors SW node voltage to determine
resistor Rfsw connected from fsw pin to ground. The SiC47x when inductor current starts to flow negatively. In power
operates between 200 kHz to 2 MHz depending on VIN and saving mode, as soon as inductor valley current crosses
VOUT conditions. zero, the device first deploys diode emulation mode by
turning off the LS FET. If load further decreases, switching
V OUT
R fsw = --------------------------------------------
- frequency is reduced proportional to the load condition to
-12
f sw × 190 × 10 save switching losses while keeping output ripple within
Note, that there is no VIN dependency on fSW as long as VIN tolerance.
and VCIN are connected to the same supply. To improve the converter efficiency, the user can choose to
SiC47x employs an advanced voltage - mode COT control disable the internal VDRV regulator by picking either mode 3
mechanism. or mode 4 and connecting a 5 V supply to the VDRV pin. This
During steady-state operation, feedback voltage (VFB) is reduces power dissipation in the SiC47x by eliminating the
compared with internal reference (0.8 V typ.) and the VDRV linear regulator losses.
amplified error signal (VCOMP) is generated at the internal The mode pin supports several modes of operation as
comp node. An internally generated ramp signal and VCOMP shown in table 1. An internal current source is used to set
feed into a comparator. Once VRAMP crosses VCOMP, an the voltage on this pin using an external resistor:
on-time pulse is generated for a fixed time. During the
on-time pulse, the high side MOSFET will be turned on. TABLE 1 - OPERATION MODES
Once the on-time pulse expires, the low side MOSFET will POWER SAVE INTERNAL VDRV
MODE RANGE (kΩ)
be turned on after a dead time period. The low side MOSFET MODE REGULATOR
will stay on for a minimum duration equal to the minimum 1 0 to 100 Enabled ON
off-time (tOFF_MIN.) and remains on until VRAMP crosses 2 298 to 304 Disabled ON
VCOMP. The cycle is then repeated. 3 494 to 504 Disabled OFF (1)
Fig. 5 illustrates the operation as described above. 4 900 to 1100 Enabled OFF (1)
Note
(1) Connect a 5 V (± 5 %) supply to the V
DRV pin
VRAMP
The mode pin is not latched to any state and can be
changed on the fly.
VCOMP

PWM
Fixed on-time

Fig. 5 - Operational Principle

OUTPUT MONITORING AND PROTECTION FEATURES

Output Over-Current Protection (OCP) pin is floating, the valley current OCP is 75 %. Connecting
SiC47x has cycle by cycle current limiting. The inductor to GND, the valley current OCP is 50 %.
valley current is monitored during LS FET turn-on period
through RDS(on) sensing. After a pre-defined blanking time,
the valley current is compared with an internal threshold. If OCPthreshold
monitored current is higher than threshold, high side
MOSFET is kept off until the inductor current falls below Iload
OCP threshold. Iinductor

OCP is enabled immediately after VDD passes UVLO rising

threshold.
There are 3 settings for the valley current OCP namely 50 %, GH
75 % and 100 %. The selection can be chosen by
connecting the ILIMIT pin either to VDD, float or GND. Fig. 6 - Over-Current Protection Illustration
Connecting to VDD will select 100 % of the preset valley
current OCP corresponding to the SiC47x being used. If the

S21-1151-Rev. F, 06-Dec-2021 7 Document Number: 77113

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Output Undervoltage Protection (UVP) During soft-start period, OCP is activated. Short circuit
UVP is implemented by monitoring output through VFB pin. protection is not active until soft-start is complete.
If the voltage level at VFB goes below 0.16 V (VOUT is 20 % Pre-Bias Start-Up
of VOUT set point) for more than 25 μs a UVP event is
In case of pre-bias startup, if the sensed voltage on FB is
recognized and both HS and LS MOSFETs are turned off.
higher than the internal soft-start ramp value, control logic
After a time-out period equal to 20 soft start cycles, the IC
prevents HS and LS FET from switching to avoid negative
attempts to re-start by going through a soft start cycle. If the
output voltage spike and excessive current sinking through
fault condition still exists, the above cycle will be repeated.
LS FET.
UVP is only active after the completion of soft-start
sequence.
Output Over Voltage Protection (OVP)
For OVP implementation, output is monitored through FB
pin. After soft start, if the voltage level at FB is above 0.96 V
(typ.) (VOUT is 120 % of VOUT set point), OVP is triggered with
both the HS and LS MOSFETs turned off. Normal operation
is resumed once FB voltage drops back to 0.96 V.
OVP is active immediately after VDD passes UVLO level.
Over Temperature Protection (OTP)
SiC47x has internal thermal monitor block that turns off both
HS and LS FETs when junction temperature is above 150 °C
(typ). A hysteresis of 35 °C is implemented, so when junction
Fig. 7 - Pre-Bias Start-Up
temperature drops below 115 °C, the device restarts by
initiating soft-start sequence again. Power Good
In order to improve the efficiency at light load condition, OTP SiC47x’s power good is an open-drain output. Pull PGOOD
is disabled when the inductor current is discontinued. pin high up to 5 V through a 10K resistor to use this signal.
Power good window is shown in the Fig. 8. If voltage level
Sequencing of Input / Output Supplies
on FB pin is out of this window, PG signal is de-asserted by
SiC47x has no sequencing requirements on any of its pulling down to GND. To prevent false triggering during
input / output (VIN, VDRV, VDD, VCIN, EN) supplies or enables. transient events, PGOOD has a 25 μs blanking time.
Enable
The SiC47x has an enable pin to turn the part on and off.
Driving this pin high enables the device, while grounding it
VFB_Rising_Vth_OV
turns it off. (typ. = 0.96 V) VFB_Falling_Vth_OV
The SiC47x enable has a weak pull down to prevent (typ. = 0.91 V)
Vref (0.8 V)
unwanted turn on due to a floating GPIO.
VFB_Falling_Vth_UV
There are no sequencing requirements with respect to other VFB (typ. = 0.72 V) VFB_Rising_Vth_UV
input / output supplies. (typ. = 0.77 V)

Soft-Start
Pull-high
During soft start time period, inrush current is limited and the PG
output voltage is ramped gradually. The following control
scheme is implemented:
Once the VDD voltage reaches the UVLO trip point, an Pull-low

internal “Soft start Reference” (SR) begins to ramp up. The Fig. 8 - PGOOD Window and Timing Diagram
SR ramp rate is determined by the external soft start
capacitor. There is an internal 5 μA current source tied to the
soft start pin which charges the external soft start cap.
The internal SR signal is being used as a reference voltage
to the loop error amplifier (see functional block diagram).
The control scheme guarantees that the output voltage
during the soft start interval will ramp up coincidently with
the SR signal. voltage. The speed of the internal soft start
ramp can SiC47x soft-start time is adjustable by selecting a
capacitor value from the following equation.

C ext x 0.8 V
SS time = --------------------------------
5 μA

S21-1151-Rev. F, 06-Dec-2021 8 Document Number: 77113

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SiC47x microBUCK FAMILY SCHEMATIC

EN

R_ EN _ H R_ EN _ L
Heading
560K DNP

3.3
R_ boot
NC PG

C_ boot

0.1 μF
R_ PGD
Notes in small 102K CSS 33 nF
black text near

18

19
3

2
6

5
component
EN

Rmode

PHASE 2

PHASE 1
values refer to 27

BOOT

PGOOD

SS
NC
Vishay SiC46x Mode
1 2K
spreadsheet V CIN CDD
calcualtor 29 26
V IN-PAD V DD
references
7 1 μF
V IN 1
+VIN 25
8 I LIMIT
V IN 2
6 V to 55 V CIN_D R_ fsw
0.1μF 28 24
A GND-PAD SiC476 fSW
30 SiC477 52 .3K
PGND-PAD SiC478
23
9 P SiC479 A GND
GND 1
10 R_ FB_ L
PGND 2
22
11 V FB
PGND 3
10 K
CIN 17 21
PGND NC
47 μF
SW 1

SW 2

SW 3
V DRV

OUT
GL

20 V

A GND
15

12

14
16

13

52 .3 K R_ FB_ H

Analog ground
(AGND), and power +VOUT = 5 V
CDRV L
ground (PGND) 0.1 μF 64 μF 64 μF
are tied internally 4.7 μF
in the SiC46x COUT_D COUT_C COUT_B

PGND

Fig. 9 - SiC477 Configured for 6 V to 55 V Input, 5 V Output at 8 A, 500 kHz Operation with Power Save Mode Enabled
all Ceramic Output Capacitance Design

S21-1151-Rev. F, 06-Dec-2021 9 Document Number: 77113

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EXTERNAL COMPONENT SELECTION FOR THE SiC47x
This section explains external component selection for and capacitance. The maximum ESR requirement is
the SiC47x family of regulators. Component reference controlled by the output ripple voltage requirement and the
designators in any equation refer to the schematic shown in DC tolerance. The output voltage has a DC value that is
Fig. 9. equal to the valley of the output ripple plus half of the
peak-to-peak ripple. A change in the output ripple voltage
The online simulation tool PowerCAD helps to make external
will lead to a change in DC voltage at the output. The
component calculation simple. The user simply needs to
relationship between output voltage ripple, output
enter required operating conditions. capacitance and ESR of the output capacitor is shown by
Output Voltage Adjustment the following equation:
If a different output voltage is needed, simply change the
V RIPPLE = I RIPPLE ( MAX. ) x  -------------------------------- 
1
value of VOUT and solve for R_FB_H based on the following  8 x C x f - + ESR (1)
formula: o sw

Where VRIPPLE is the maximum allowed output ripple

R _FB_L ( V OUT - V FB ) voltage; IRIPPLE(MAX.) is the maximum inductor ripple current;
R _FB_H = ----------------------------------------------------
-
V FB fsw is the switching frequency of the converter; Co is the total
Where VFB is 0.8 V for the SiC47x. R_FB_L should be a output capacitance; ESR is the equivalent series resistance
of the total output capacitors.
maximum of 10 kΩ to prevent VOUT from drifting at no load.
In addition to the output ripple voltage requirement, the
Switching Frequency Selection output capacitors need to meet transient requirements. A
The following equation illustrates the relationship between worst case load release condition (from maximum load to no
on-time, VIN, VOUT, and Rfsw value: load at the exact moment when inductor current is at the
peak) determines the required capacitance. If the load
V OUT release is instantaneous (load changes from maximum to
R _fsw = --------------------------------------------
-
– 12 zero within 1 μs), the output capacitor must absorb all the
f sw × 190 × 10
energy stored in the inductor. The peak voltage on the
Inductor Selection capacitor, VPK, under this worst case condition can be
calculated by following equation:
The choice of inductor is specific to each application and
2
L x  I OUT + --- x I RIPPLE(MAX.)
quickly determined with the following equations: 1
2 (2)
V OUT C OUT_MIN. = --------------------------------------------------------------------------------
t ON = ------------------------------------
- 2 2
V IN_max. x f sw ( V PK ) - ( V OUT )

and During the load release time, the voltage across the inductor
is approximately -VOUT. This causes a down-slope or falling
( V IN - V OUT ) x t ON di/dt in the inductor. If the load di/dt is not much faster than
L = --------------------------------------------------
I OUT_MAX. x K the di/dt of the inductor, then the inductor current will tend
to track the falling load current. This will reduce the excess
Where K is a percentage of maximum output current ripple inductive energy that must be absorbed by the output
required. The designer can quickly make a choice of capacitor; therefore a smaller capacitance can be used. The
inductor if the ripple percentage is decided, usually no more following can be used to calculate the required capacitance
than 30 % however higher or lower percentages of IOUT can for a given diLOAD/dt.
be acceptable depending on application. This device allows Peak inductor current, ILPK, is shown by the next equation:
choices larger than 30 %.
1
Other than the inductance the DCR and saturation current I LPK = I MAX. + --- x I RIPPLE(MAX.)
2
parameters are key values. The DCR causes an I2R loss
which will decrease the system efficiency and generate di LOAD
The slew rate of load current = -------------------
heat. The saturation current has to be higher than the dt
maximum output current plus ½ of the ripple current. In an
over current condition the inductor current may be very high. I LPK I MAX.
L x -------------- - ------------------- x dt
All this needs to be considered when selecting the inductor. V OUT dI LOAD
C OUT_MIN. = I LPK x --------------------------------------------------------------- (3)
Output Capacitor Selection 2 ( V PK - V OUT )
The SiC47x is stable with any type of output capacitors by
choosing the appropriate VRAMP components. This allows Based on application requirement, either equation (2) or
equation (3) can be used to calculate the ideal output
the user to choose the output capacitance based on the
capacitance to meet transition requirement. Compare this
best trade off of board space, cost and application
calculated capacitance with the result from equation (1) and
requirements.
choose the larger value to meet both ripple and transition
The output capacitors are chosen based upon required ESR requirement.

S21-1151-Rev. F, 06-Dec-2021 10 Document Number: 77113

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Enable Pin Voltage
The EN pin has an internal pull down resistor and only
requires an enable voltage. This needs to be greater than
1.4 V. An input voltage or a resistor connected across VIN
and EN can be used. The internal pull down resistance is
5 MΩ.
Input Capacitance
In order to determine the minimum capacitance the input
voltage ripple needs to be specified; VCINPKPK ≤ 500 mV is a
suitable starting point. This magnitude is determined by the
final application specification. The input current needs to be
determined for the lowest operating input voltage,

I CIN ( RMS ) =

V OUT 2
D x ( 1 – D ) + ------ ×  ------------------------------------- × ( 1 – D ) × D
1 2
I OUT x
12  L × ƒ sw × I OUT 

The minimum input capacitance can then be found,

D x (1 - D)
C IN_min. = I OUT x -----------------------------------------
V CINPKPK x f sw

If high ESR capacitors are used, it is good practice to also

add low ESR ceramic capacitance. A 4.7 μF ceramic input
capacitance is a suitable starting point.
Care must be taken to account for voltage derating of the
capacitance when choosing an all ceramic input
capacitance.

S21-1151-Rev. F, 06-Dec-2021 11 Document Number: 77113

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ELECTRICAL CHARACTERISTICS (VIN = 48 V, VOUT = 5 V, fsw = 300 kHz, SiC476 (12 A), unless otherwise noted)

100 100
VIN = 12 V, L = 3.3 μH VIN = 12 V, L = 3.3 μH
98 97

96 94

94 91

92 88

Efficiency (%)
Efficiency (%)

VIN = 24 V, L = 4.7 μH
90 85
VIN = 24 V, L = 4.7 μH
88 VIN = 36 V, L = 4.7 μH 82
VIN = 36 V, L = 4.7 μH
86 79 VIN = 48 V, L = 4.7 μH
VIN = 48 V, L = 4.7 μH
84 76

82 73

80 70
0 1 2 3 4 5 6 7 8 9 10 11 12 0.01 0.1 1

Output Current, IOUT (A) Output Current, IOUT (A)

Fig. 10 - SiC476 Efficiency vs. Output Current, Fig. 13 - SiC476 Efficiency vs. Output Current - Light Load,
VOUT = 5 V VOUT = 5 V

100 100

98 97

96 94

94 VIN = 24 V, L = 6.8 μH 91
VIN = 24 V, L = 6.8 μH
VIN = 36 V, L = 8.2 μH
92 88
Efficiency (%)

Efficiency (%)

VIN = 36 V, L = 8.2 μH
90 85
VIN = 48 V, L = 10 μH VIN = 48 V, L = 10 μH
88 82

86 79

84 76

82 73

80 70
0 1 2 3 4 5 6 7 8 9 10 11 12 0.01 0.1 1

Output Current, IOUT (A) Output Current, IOUT (A)

Fig. 11 - SiC476 Efficiency vs. Output Current, Fig. 14 - SiC476 Efficiency vs. Output Current - Light Load,
VOUT = 12 V VOUT = 12 V

Axis Title Axis Title

100 10000 100 10000

90 90
TC - Case Temperature (°C)

TC - Case Temperature (°C)

80 80
1000 1000
70 70
2nd line

2nd line
2nd line

2nd line
1st line

1st line

60 60

50 50
100 100
40 40

30 30

20 10 20 10
0 1 2 3 4 5 6 7 8 9 10 11 12 0 1 2 3 4 5 6 7 8 9 10 11 12
IOUT - Output Current (A) IOUT - Output Current (A)

Fig. 12 - SiC476 Load Current vs. Case Temperature, Fig. 15 - SiC476 Load Current vs. Case Temperature,
VIN = 48 V, VOUT = 5 V VIN = 48 V, VOUT = 12 V

S21-1151-Rev. F, 06-Dec-2021 12 Document Number: 77113

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ELECTRICAL CHARACTERISTICS (VIN = 48 V, VOUT = 5 V, fsw = 300 kHz, SiC477 (8 A), unless otherwise noted)

100 100
VIN = 12 V, L = 5.6 μH VIN = 12 V, L = 5.6 μH
98 97

96 94
VIN = 24 V, L = 6.8 μH
94 91

88

Efficiency (%)
92 VIN = 24 V, L = 6.8 μH
Efficiency (%)

90 85
VIN = 36 V, L = 8.2 μH

88 82
VIN = 36 V, L = 8.2 μH
VIN = 48 V, L = 8.2 μH
86 79
VIN = 48 V, L = 8.2 μH
84 76

82 73

80 70
0 1 2 3 4 5 6 7 8 0.01 0.1 1

Output Current, IOUT (A) Output Current, IOUT (A)

Fig. 16 - SiC477 Efficiency vs. Output Current, Fig. 19 - SiC477 Efficiency vs. Output Current - Light Load,
VOUT = 5 V VOUT = 5 V

100 100
VIN = 24 V, L = 10 μH
98 97

96 94

94 VIN = 24 V, L = 10 μH 91

92 VIN = 36 V, L = 15 μH 88
Efficiency (%)

Efficiency (%)

VIN = 36 V, L = 15 μH
90 VIN = 48 V, L = 15 μH 85

88 82 VIN = 48 V, L = 15 μH

86 79

84 76

82 73

80 70
0 1 2 3 4 5 6 7 8 0.01 0.1 1

Output Current, IOUT (A) Output Current, IOUT (A)

Fig. 17 - SiC477 Efficiency vs. Output Current, Fig. 20 - SiC477 Efficiency vs. Output Current - Light Load,
VOUT = 12 V VOUT = 12 V

Axis Title Axis Title

100 10000 100 10000

90 90
TC - Case Temperature (°C)

TC - Case Temperature (°C)

80 80
1000 1000
70 70
2nd line

2nd line
2nd line

2nd line
1st line

1st line

60 60

50 50
100 100
40 40

30 30

20 10 20 10
0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8
IOUT - Output Current (A) IOUT - Output Current (A)

Fig. 18 - SiC477 Load Current vs. Case Temperature, Fig. 21 - SiC477 Load Current vs. Case Temperature,
VIN = 48 V, VOUT = 5 V VIN = 48 V, VOUT = 12 V

S21-1151-Rev. F, 06-Dec-2021 13 Document Number: 77113

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ELECTRICAL CHARACTERISTICS (VIN = 48 V, VOUT = 5 V, fsw = 300 kHz, SiC478 (5 A), unless otherwise noted)

100 100
VIN = 12 V, L = 10 μH
98 97 VIN = 12 V, L = 10 μH

96 94

94 91 VIN = 24 V, L = 15 uH

92 88
Efficiency (%)

Efficiency (%)
VIN = 24 V, L = 15 μH
VIN = 36 V, L = 15 μH
90 85

88 82 VIN = 36 V, L = 15 μH
VIN = 48 V, L = 15 μH
86 79
VIN = 48 V, L = 15 μH
84 76

82 73

80 70
0 1 2 3 4 5 6 0.01 0.1 1

Output Current, IOUT (A) Output Current, IOUT (A)

Fig. 22 - SiC478 Efficiency vs. Output Current, Fig. 25 - SiC478 Efficiency vs. Output Current - Light Load,
VOUT = 5 V VOUT = 5 V

100 100
VIN = 24 V, L = 15 μH
98 97

96 94
VIN = 24 V, L = 15 μH
94 VIN = 36 V, L = 22 μH 91
Efficiency (%)

92
Efficiency (%)

88 VIN = 36 V, L = 22 μH
VIN = 48 V, L = 22 μH
90 85
VIN = 48 V, L = 22 μH
88 82

86 79

84 76

82 73

80 70
0 1 2 3 4 5 6 0.01 0.1 1

Output Current, IOUT (A) Output Current, IOUT (A)

Fig. 23 - SiC478 Efficiency vs. Output Current, Fig. 26 - SiC478 Efficiency vs. Output Current - Light Load,
VOUT = 12 V VOUT = 12 V

Axis Title Axis Title

100 10000 100 10000

90 90
TC - Case Temperature (°C)

TC - Case Temperature (°C)

80 80
1000 1000
70 70
2nd line

2nd line
2nd line

2nd line
1st line

1st line

60 60

50 50
100 100
40 40

30 30

20 10 20 10
0 1 2 3 4 5 0 1 2 3 4 5
IOUT - Output Current (A) IOUT - Output Current (A)

Fig. 24 - SiC478 Load Current vs. Case Temperature, Fig. 27 - SiC478 Load Current vs. Case Temperature,
VIN = 48 V, VOUT = 5 V VIN = 48 V, VOUT = 12 V

S21-1151-Rev. F, 06-Dec-2021 14 Document Number: 77113

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ELECTRICAL CHARACTERISTICS (VIN = 48 V, VOUT = 5 V, fsw = 300 kHz, SiC479 (3 A), unless otherwise noted)

100 100
VIN = 12 V, L = 10 μH
98 97 VIN = 12 V, L = 10 μH

96 94 VIN = 24 V, L = 15 μH

94 91

92 88
Efficiency (%)

Efficiency (%)
VIN = 24 V, L = 15 μH
90 85
VIN = 36 V, L = 15 μH
88 82 VIN = 36 V, L = 15 μH

86 VIN = 48 V, L = 15 μH 79
VIN = 48 V, L = 15 μH
84 76

82 73

80 70
0 1 2 3 4 0.01 0.1 1

Output Current, IOUT (A) Output Current, IOUT (A)

Fig. 28 - SiC479 Efficiency vs. Output Current, Fig. 31 - SiC479 Efficiency vs. Output Current - Light Load,
VOUT = 5 V VOUT = 5 V

100 100
VIN = 24 V, L = 15 μH
98 97
96 94
94 VIN = 24 V, L = 15 μH 91
VIN = 36 V, L = 22 μH
Efficiency (%)

92
Efficiency (%)

88
VIN = 36 V, L = 22 μH
90 VIN = 48 V, L = 22 μH
85
VIN = 48 V, L = 22 μH
88 82
86 79
84 76
82 73
80 70
0 1 2 3 4 0.01 0.1 1
Output Current, IOUT (A) Output Current, IOUT (A)

Fig. 29 - SiC479 Efficiency vs. Output Current, Fig. 32 - SiC479 Efficiency vs. Output Current - Light Load,
VOUT = 12 V VOUT = 12 V

Axis Title Axis Title

100 10000 100 10000

90 90
TC - Case Temperature (°C)

TC - Case Temperature (°C)

80 80
1000 1000
70 70
2nd line

2nd line
2nd line

2nd line
1st line

1st line

60 60

50 50
100 100
40 40

30 30

20 10 20 10
0 1 2 3 0 1 2 3
IOUT - Output Current (A) IOUT - Output Current (A)

Fig. 30 - SiC479 Load Current vs. Case Temperature, Fig. 33 - SiC479 Load Current vs. Case Temperature,
VIN = 48 V, VOUT = 5 V VIN = 48 V, VOUT = 12 V

S21-1151-Rev. F, 06-Dec-2021 15 Document Number: 77113

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ELECTRICAL CHARACTERISTICS (VIN = 48 V, VOUT = 5 V, fsw = 300 kHz, SiC477 (8 A), unless otherwise noted)

Axis Title Axis Title

1.04 10000 1.04 10000
1.03
1.03
1.02
1.02 1.01
Normalized Efficiency

Normalized Efficiency
1000 1000
1.01 1.00

2nd line

2nd line
1st line

1st line
2nd line

2nd line
0.99
1.00
0.98
0.99 0.97
100 100
0.98 0.96
0.95
0.97
0.94
0.96 10 0.93 10
0 100 200 300 400 500 600 700 800 900 0 200 400 600 800 1000 1200
fsw - Switching Frequency (kHz) fsw - Switching Frequency (kHz)

Fig. 34 - SiC476 Efficiency vs. Switching Frequency Fig. 37 - SiC477 Efficiency vs. Switching Frequency

Axis Title Axis Title

1.04 1.04 10000
1.03 1.03
4000
1.02 1.02
Normalized Efficiency
Normalized Efficiency

1.01 1.01
1000
1.00 1.00
2nd line

2nd line
1st line

1st line
2nd line
2nd line

0.99 0.99
200
0.98 0.98
100
0.97 0.97
0.96 0.96
0.95 0.95
0.94 10 0.94 10
0 200 400 600 800 1000 1200 0 200 400 600 800 1000 1200
fsw - Switching Frequency (kHz) fsw - Switching Frequency (kHz)

Fig. 35 - SiC478 Efficiency vs. Switching Frequency Fig. 38 - SiC479 Efficiency vs. Switching Frequency

Axis Title Axis Title

2.00 10000 808 10000
RDS(on) - Normalized On-State Resistance

1.80 806
VFB - Voltage Reference (mV)

1.60
804
1.40
1000 1000
1.20 802
2nd line
2nd line
2nd line

1st line
1st line

2nd line

1.00 800
0.80 798
100 100
0.60
796
0.40
0.20 794

0 10 792 10
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
T - Temperature (°C) T - Temperature (°C)

Fig. 36 - RDS(ON) vs. Temperature Fig. 39 - Voltage Reference vs. Temperature

S21-1151-Rev. F, 06-Dec-2021 16 Document Number: 77113

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ELECTRICAL CHARACTERISTICS (VIN = 48 V, VOUT = 5 V, fsw = 300 kHz, SiC477 (8 A), unless otherwise noted)

Axis Title Axis Title

0.8 10000 0.8 10000

0.6 0.6

0.4 0.4

Load Regulation (%)

Line Regulation (%)

1000 1000
0.2 0.2

2nd line

2nd line
1st line

1st line
2nd line

2nd line
0 0

-0.2 -0.2
100 100
-0.4 -0.4

-0.6 -0.6

-0.8 10 -0.8 10
0 6 12 18 24 30 36 42 48 54 60 0 1 2 3 4 5 6
VIN - Input Voltage (V) IOUT - Output Current (A)

Fig. 40 - Line Regulation Fig. 43 - Load Regulation

Axis Title Axis Title

IVCIN_SHDN + IVIN_SHDN - Shutdown Current (µA)

8 10000
IVCIN_SHDN + IVIN_SHDN - Shutdown Current (µA)
8 10000

7 7

6 6
1000 1000
5 5
2nd line

2nd line
2nd line

1st line

2nd line

1st line
4 4

3 3
100 100
2 2

1 1

0 10 0 10
0 6 12 18 24 30 36 42 48 54 60 -60 -40 -20 0 20 40 60 80 100 120 140
VCIN / VIN - Input Voltage (V) T - Temperature (°C)

Fig. 41 - Shutdown Current vs. Input Voltage Fig. 44 - Shutdown Current vs. Junction Temperature

Axis Title Axis Title

190 10000 220 10000
180
200
IVCIN + IVIN - Input Current (µA)

IVCIN + IVIN - Input Current (µA)

170
180
160
1000 1000
150 160
2nd line

2nd line
1st line

1st line
2nd line

2nd line

140 140
130
120
100 100
120
100
110
100 80

90 10 60 10
0 6 12 18 24 30 36 42 48 54 60 -60 -40 -20 0 20 40 60 80 100 120 140
VCIN / VIN - Input Voltage (V) T - Temperature (°C)

Fig. 42 - Input Current vs. Input Voltage Fig. 45 - Input Current vs. Junction Temperature

S21-1151-Rev. F, 06-Dec-2021 17 Document Number: 77113

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ELECTRICAL CHARACTERISTICS (VIN = 48 V, VOUT = 5 V, fsw = 300 kHz, SiC477 (8 A), unless otherwise noted)

Axis Title Axis Title

2.4 10000 1.2 10000
VEN = 5.0 V
2.1 1.1
VEN - EN Logic Threshold (V)

EN Current, IEN (µA)

1.8 1.0
1000 1000

2nd line
VIH_EN
1.5 0.9

2nd line

2nd line
1st line

1st line
2nd line

1.2 0.8
VIL_EN
0.9 0.7
100 100
0.6 0.6

0.3 0.5

0 10 0.4 10
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
T - Temperature (°C) T - Temperature (°C)

Fig. 46 - EN Logic Threshold vs. Junction Temperature Fig. 49 - EN Current vs. Junction Temperature

Fig. 47 - Load Transient (3 A to 6 A), Time = 100 μs/div Fig. 50 - Line Transient (8 V to 48 V), Time = 10 ms/div

Fig. 48 - Start-Up with EN, Time = 1 ms/div Fig. 51 - Start-up with VIN, Time = 5 ms/div

S21-1151-Rev. F, 06-Dec-2021 18 Document Number: 77113

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ELECTRICAL CHARACTERISTICS (VIN = 48 V, VOUT = 5 V, fsw = 300 kHz, SiC477 (8 A), unless otherwise noted)

Fig. 52 - Output Ripple 2 A, Time = 5 μs/div Fig. 54 - Output Ripple 300 mA, Time = 5 μs/div

Fig. 53 - Output Ripple PSM, Time = 10 ms/div

S21-1151-Rev. F, 06-Dec-2021 19 Document Number: 77113

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PCB LAYOUT RECOMMENDATIONS
Step 1: VIN/GND Planes and Decoupling Step 3: VSWH Plane

VIN plane

Snubber
PGND plane

VSWH

Fig. 57
PGND plane
VSWH
1. Connect output inductor to SiC47x with large plane to
Fig. 55 lower the resistance
1. Layout VIN and PGND planes as shown above 2. If any snubber network is required, place the
components on the bottom side as shown above
2. Ceramic capacitors should be placed between VIN and
PGND, and very close to the device for best decoupling
effect Step 4: VDD/VDRV Input Filter
3. Different values / packages of ceramic capacitors should
be used to cover entire decoupling spectrum e.g. 1210
and 0603
4. Smaller capacitance values, placed closer to device’s
VIN pin(s), is better for high frequency noise absorbing

Step 2: VCIN Pin AGND

P
G
N
D
VCIN decouple
cap

AGND plane

Fig. 58

1. CVDD cap should be placed between pin 26 and pin 23

(the AGND of driver IC) to achieve best noise filtering
Fig. 56
2. CVDRV cap should be placed close to VDRV (pin 16) and
PGND (pin 17) to reduce effects of trace impedance and
1. VCIN (pin 1) is the input pin for both internal LDO and tON provide maximum instantaneous driver current for low
block. tON time varies based on input voltage. It is side MOSFET during switching cycle
necessary to put a decoupling capacitor close to this pin
2. The connection can be made through a via and the cap
can be placed at bottom layer

S21-1151-Rev. F, 06-Dec-2021 20 Document Number: 77113

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Step 5: BOOT Resistor and Capacitor Placement Step 6: Signal Routing

AGND
plane

PGND

V
o
u
t

s
i
g
n
a
l

Fig. 60

Fig. 59 1. Separate the small analog signal from high current path.
As shown above, the high current paths with high dv/dt,
1. These components need to be placed very close di/dt are placed on the left side of the IC, while the small
to SiC47x, right between PHASE (pin 5, 6) and BOOT control signals are placed on the right side of the IC. All
(pin 4) the components for small analog signal should be
2. In order to reduce parasitic inductance, it is placed closer to IC with minimum trace length
recommended to use 0402 chip size for the resistor and 2. Pin 23 is the IC analog ground, which should have a
the capacitor single connection to power ground. The AGND ground
plane connected with pin 23 helps keep AGND quiet and
improve noise immunity
3. Feedback signal can be routed through inner layer. Make
sure this signal is far away from VSWH node and shielded
by inner ground layer

S21-1151-Rev. F, 06-Dec-2021 21 Document Number: 77113

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Step 7: Adding Thermal Relief Vias and Duplicate Power Step 8: Ground Layer
Path Plane

AGND plane

VIN plane

PGND plane

PGND plane

VSWH
Fig. 62
Fig. 61
1. It is recommended to make the entire inner layer (next to
1. Thermal relief vias can be added on the VIN and PGND top layer) ground plane
pads to utilize inner layers for high current and thermal 2. This ground plane provides shielding between noise
dissipation source on top layer and signal trace within inner layer.
2. To achieve better thermal performance, additional vias 3. The ground plane can be broken into two sections as
can be put on VIN and PGND plane. Also, it is necessary PGND and AGND
to duplicate the VIN and ground planes at bottom layer to
maximize the power dissipation capability from PCB.
3. VSWH pad is a noise source and not recommended to put
vias on this pad.
4. 8 mil drill for pads and 10 mils drill for plane are optional
via sizes. The vias on pads may drain solder during
assembly and cause assembly issues. Please consult
with the assembly house for guidelines

S21-1151-Rev. F, 06-Dec-2021 22 Document Number: 77113

For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 SiC476, SiC477, SiC478, SiC479
www.vishay.com
Vishay Siliconix

PRODUCT SUMMARY
Part number SiC476 SiC477 SiC478 SiC479
12 A, 4.5 V to 55 V input, 8 A, 4.5 V to 55 V input, 5 A, 4.5 V to 55 V input, 3 A, 4.5 V to 55 V input,
100 kHz to 2 MHz, 100 kHz to 2 MHz, 100 kHz to 2 MHz, 100 kHz to 2 MHz,
Description
synchronous microBUCK synchronous microBUCK synchronous microBUCK synchronous microBUCK
regulator regulator regulator regulator
Input voltage min. (V) 4.5 4.5 4.5 4.5
Input voltage max. (V) 55 55 55 55
Output voltage min. (V) 0.8 0.8 0.8 0.8
Output voltage max. (V) 15 15 15 15
Continuous current (A) 12 8 5 3
Switch frequency min. (kHz) 100 100 100 100
Switch frequency max. (kHz) 2000 2000 2000 2000
Pre-bias operation (yes / no) Yes Yes Yes Yes
Internal bias reg. (yes / no) Yes Yes Yes Yes
Compensation Internal Internal Internal Internal
Enable (yes / no) Yes Yes Yes Yes
PGOOD (yes / no) Yes Yes Yes Yes
Overcurrent protection Yes Yes Yes Yes
OVP, OCP, UVP/SCP, OVP, OCP, UVP/SCP, OVP, OCP, UVP/SCP, OVP, OCP, UVP/SCP,
Protection
OTP, UVLO OTP, UVLO OTP, UVLO OTP, UVLO
Light load mode Power save Power save Power save Power save
Peak efficiency (%) 97 98 98 98
Package type PowerPAK MLP55-27L PowerPAK MLP55-27L PowerPAK MLP55-27L PowerPAK MLP55-27L
Package size (W, L, H) (mm) 5 x 5 x 0.75 5 x 5 x 0.75 5 x 5 x 0.75 5 x 5 x 0.75
Status code 1 1 1 1
microBUCK (step down microBUCK (step down microBUCK (step down microBUCK (step down
Product type
regulator) regulator) regulator) regulator)
Computing, consumer, Computing, consumer, Computing, consumer, Computing, consumer,
Applications industrial, healthcare, industrial, healthcare, industrial, healthcare, industrial, healthcare,
networking networking networking networking

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?77113.

S21-1151-Rev. F, 06-Dec-2021 23 Document Number: 77113

For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 Legal Disclaimer Notice
www.vishay.com
Vishay
Disclaimer

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Revision: 01-Jan-2022 1 Document Number: 91000