EE276 – Digital Electronic Circuits

Counters
 Introduction: Counters

• In digital logic and computing, a counter is a device which

stores (and sometimes displays) the number of times a
particular event or process has occurred, often in relationship
to a clock signal.

001 010 011

000 3-bit up-counter 100

111 110 101

Example
• In electronics, counters can be implemented quite easily using
register-type circuits such as the flip-flop, and a wide variety of
classifications exist:

1. Asynchronous (ripple) counter – changing state bits are used as

clocks to subsequent state flip-flops
2. Synchronous counter – all state bits change under control of a
single clock
3. Decade counter – counts through ten states per stage
4. Up/down counter – counts both up and down, under command of a
control input

5. Ring counter – formed by a shift register with feedback connection

in a ring

6. Johnson counter – a twisted ring counter

7. Cascaded counter
Modulus of a counter
The modulus (MOD number) of a counter is the number of different
logic states it goes through before it comes back to the initial state
to repeat the count sequence.

An n-bit counter that counts through all its natural states and does
not skip any of the states has a modulus of 2n

Example: If the desired modulus is 10

Smallest integer greater than or equal to 10 and which is also an integral
power of 2 is 16.
number of flip-flops in this case would be 4

2N - 1 + 1 ≤ modulus ≤ 2N

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 Ripple counter
• A ripple counter is a cascaded arrangement of flip-flops
where the output of one flip-flop drives the clock input
of the following flip-flop,
– The clock input is applied only to the first flip-flop, also called the
input flip-flop, in the cascaded arrangement.
– The clock input to any subsequent flip-flop comes from the output of
its immediately preceding flip-flop

Fig: Generalized block schematic of n-bit binary ripple counter

Four-bit binary ripple counter

f
1
0
1

1
0
f/2

f/4

1
0
1
1

0
f/8

1
0
0
0
0

f/16
1
0
0
0
0
CONTD….

Fig: Four‐bit binary ripple counter with T flip-flops

Fig: Four‐bit binary ripple counter with D flip-flops

 Excercise
1. A four-bit binary ripple counter of the type shown in Fig. is initially in the 0000 state
before the clock input is applied to the counter. The clock pulses are applied to the
counter at some time instant t11 and then again removed some time later at another
time instant t2. The counter is observed to read 0011. How many negative-going clock
transitions have occurred during the time the clock was active at the counter input?

Solution: It is not possible to determine the number of clock edges

2. It is desired to design a binary ripple counter of the type shown in Fig that is capable of
counting the number of items passing on a conveyor belt. Each time an item passes a
given point, a pulse is generated that can be used as a clock input. If the maximum
number of items to be counted is 6000, determine the number of flip-flops required
Solution:
2N -1≥ 6000

N ≥ log 6001/log 2 ≥ 3.778/0.3010 ≥ 12.55

the minimum number of flip-flops required=13

Binary Ripple Counters with a Modulus of Less than 2N

The counter thus always

counts from 0000 to 0110
and resets back to 0000
MOD-7 Counter

Exercise
If the NAND gate used in the
counter arrangement of Fig. is a
two-input NAND and its inputs
are from the Q1 and Q3 outputs,
the counter will go through 0000
to ?

Answer: 1001
 Steps in designing binary ripple counterts
1. Determine the minimum number of flip-flops N so that 2N ≥ X
Connect these flip-flops as a binary ripple counter. If 2N = X, do
not go to steps 2 and 3.
2. Identify the flip-flops that will be in the logic HIGH state at the
count whose decimal equivalent is X. Choose a NAND gate with
the number of inputs equal to the number of flip-flops that
would be in the logic HIGH state.
As an example, if the objective were to design an MOD-12
counter, then, in the corresponding count, that is, 1100, two
flip-flops would be in the logic HIGH state. The desired NAND
gate would therefore be a two-input gate.
3. Connect the Q outputs of the identified flip-flops to the inputs
of the NAND gate and the NAND gate output to asynchronous
clear inputs of all flip-flops
 Excercise
1. Refer to the binary ripple counter of Fig.. Determine the modulus of the counter and
also the frequency of the flip-flop Q3 output.

Solution: The counter counts in the natural sequence from 0000 to 1011
Modulus of the counter = 12
frequency of the Q3 output waveform = 1.2 × 103/12 = 100 kHz

.
 Excercise
Design a binary ripple counter that counts 000 and 111 and skips the remaining six
states, that is,001, 010, 011, 100, 101 and 110. Use presentable, clearable negative
edge-triggered J-K flip-flops with active LOW PRESET and CLEAR inputs. Also, draw
the timing waveforms and determine the frequency of different flip-flop outputs for
a given clock frequency, fc

Solution:
 Exercise count

0
Q8

0
Q4

0
Q2

0
Q1

0
Design a BCD Ripple Counter 1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
Solution:
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1

• Q1 changes state after each clock pulse.

• Q2 complements every time Q1 goes from 1 to 0, as

long as Q8 = 0. When Q8 becomes 1, Q2 remains
at 0.

• Q4 complements every time Q2 goes from 1 to 0.

• Q8 remains at 0 as long as Q2 or Q4 is 0. When

both Q2 and Q4 become 1, Q8 complements when
Q1 goes from 1 to 0. Q8 is cleared on the next
transition of Q1
 Synchronous counter
• In a synchronous counter, all flip-flops in the counter are
clocked simultaneously in synchronism with the clock, and
as a consequence all flip-flops change state at the same
time.
– The propagation delay in this case is independent of the number
of flip-flops used.

Count sequence of a four bit binary counter

count Q3 Q2 Q1 Q0 count Q3 Q2 Q1 Q0
0 0 0 0 0 8 1 0 0 0
1 0 0 0 1 9 1 0 0 1
2 0 0 1 0 10 1 0 1 0
3 0 0 1 1 11 1 0 1 1
4 0 1 0 0 12 1 1 0 0
5 0 1 0 1 13 1 1 0 1
6 0 1 1 0 14 1 1 1 0
7 0 1 1 1 15 1 1 1 1
Four-bit synchronous counter
 Example
Design Four‐bit synchronous binary counter
 UP/DOWN Counters
upward count sequence synchronous counter. Reverse or downward count sequence synchronous
counter.
count Q2 Q1 Q0 count Q2 Q1 Q0
0 0 0 0 0 0 0 0
1 0 0 1 1 1 1 1
2 0 1 0 2 1 1 0
3 0 1 1 3 1 0 1
4 1 0 0 4 1 0 0
5 1 0 1 5 0 1 1
6 1 1 0 6 0 1 0
7 1 1 1 7 0 0 1

3-bit UP/DOWN Counter

 Example
Design three- bit up/down counter

Up=1: upward counter

Down=0: reverse count
Designing Counters with Arbitrary Sequences
Design MOD-6 synchronous counter design, which follows the count sequence
000, 010, 011, 001, 100, 110, 000, 010,
Steps to be followed
1. Determine the number of flip-flops required for the purpose. Identify the undesired
states. In the present case, the number of flip-flops required is 3 and the undesired
states are 101 and 111
2. Draw the state transition diagram showing all possible states including the ones
that are not desired. The undesired states should be depicted to be transiting to any
of the desired states. It is important to include the undesired states to ensure that,
if the counter accidentally gets into any of these undesired states owing to noise or
power-up, the counter will go to a desired state to resume the correct sequence on
application of the next clock pulse. Figure shows the state transition diagram
 Contd…

3. Draw the excitation table for the counter, listing the present states, the next states
corresponding to the present states and the required logic status of the flip-flop
inputs
 Contd…
4. Design the logic circuits for generating JA, KA, JB, KB, JC and KC inputs from
available A, A, B, B, C and C

KA
JA
 Contd…
4. Design the logic circuits for generating JA, KA, JB, KB, JC and KC inputs from
available A, A, B, B, C and C

KB

JB
 Contd…
4. Design the logic circuits for generating JA, KA, JB, KB, JC and KC inputs from
available A, A, B, B, C and C

KC

JC
Contd…
 UP/DOWN Counters
upward count sequence synchronous counter. Reverse or downward count sequence synchronous
counter.

count Q3 Q2 Q1 Q0 count Q3 Q2 Q1 Q0 count Q3 Q2 Q1 Q0 count Q3 Q2 Q1 Q0

0 0 0 0 0 8 1 0 0 0 0 0 0 0 0 8 1 0 0 0

1 0 0 0 1 9 1 0 0 1 1 1 1 1 1 9 0 1 1 1

2 0 0 1 0 10 1 0 1 0 2 1 1 1 0 10 0 1 1 0

3 0 0 1 1 11 1 0 1 1 3 1 1 0 1 11 0 1 0 1

4 0 1 0 0 12 1 1 0 0 4 1 1 0 0 12 0 1 0 0

5 0 1 0 1 13 1 1 0 1 5 1 0 1 1 13 0 0 1 1

6 0 1 1 0 14 1 1 1 0 6 1 0 1 0 14 0 0 1 0

7 0 1 1 1 15 1 1 1 1 7 1 0 0 1 15 0 0 0 1
 Shift Register Counters
▪ Shift register counter: a shift register with the serial
output connected back to the serial input.
▪ They are classified as counters because they give a
specified sequence of states.
▪ Two common types: the Johnson counter and the Ring
counter.

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 Ring Counters
▪ One flip-flop (stage) for each state in the sequence.
▪ The output of the last stage is connected to the D input of the
first stage.
▪ An n-bit ring counter cycles through n states.
▪ No decoding gates are required, as there is an output that
corresponds to every state the counter is in.

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 Ring Counters
▪ Example: A 6-bit (MOD-6) ring counter.
PRE
Q0 Q1 Q2 Q3 Q4 Q5
D Q D Q D Q D Q D Q D Q

CLR
CLK

Clock Q0 Q1 Q2 Q3 Q4 Q5 100000
0 1 0 0 0 0 0
000001 010000
1 0 1 0 0 0 0
2 0 0 1 0 0 0
3 0 0 0 1 0 0 000010 001000
4 0 0 0 0 1 0
5 0 0 0 0 0 1 000100

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 Johnson Counters

▪ The complement of the output of the last stage is

connected back to the D input of the first stage.
▪ Also called the twisted-ring counter.
▪ Require fewer flip-flops than ring counters but more flip-
flops than binary counters.
▪ An n-bit Johnson counter cycles through 2n states.
▪ Require more decoding circuitry than ring counter but
less than binary counters.

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 Contd..

▪ Example: A 4-bit (MOD-8) Johnson counter.

A B C
D Q D Q D Q D Q
Q'
D'
CLR
CLK

Clock A B C D 0000
0 0 0 0 0
0001 1000
1 1 0 0 0
2 1 1 0 0
3 1 1 1 0 0011 1100
4 1 1 1 1
5 0 1 1 1 0111 1110
6 0 0 1 1
7 0 0 0 1 1111

CS1104-13 Johnson Counters 30

Contd..

▪ Decoding logic for a 4-bit Johnson counter.

Clock A B C D Decoding A'
0 0 0 0 0 A'.D' State 0
D'
1 1 0 0 0 A.B'
2 1 1 0 0 B.C' A
3 1 1 1 0 C.D' State 1
B'
4 1 1 1 1 A.D
5 0 1 1 1 A'.B B
State 2
6 0 0 1 1 B'.C C'
7 0 0 0 1 C'.D
C
State 3
D'
B' A
State 6 State 4
C D
C' A'
State 7 State 5
D B

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