Experiment.

What is a Master-Slave Flip Flop?

Basically, this type of flip flop can be designed with two JK FFs by connecting in series. One of these FFs,
one FF works as the master as well as another FF works as a slave. The connection of these FFs can be
done like this, the master FF output can be connected to the inputs of the slave FF. Here slave FF’s
outputs can be connected to the inputs of the master FF.

In this type of FF, an inverter is also used addition to two FFs. The inverter connection can be done in
such a way that where the inverted CLK pulse can be connected to the slave FF. In other terms, if CLK
pulse is 0 for a master FF, then CLK pulse will be 1 for a slave FF. Similarly, when CLK pulse is 1 for master
FF, then CLK pulse will be 0 for slave FF.

Master-Slave FF Working

o When the clock pulse is true, the slave flip flop will be in the isolated state, and the system's
state may be affected by the J and K inputs. The "slave" remains isolated until the CP is 1. When
the CP set to 0, the master flip-flop passes the information to the slave flip flop to obtain the
output.

o The master flip flop responds first from the slave because the master flip flop is the positive
level trigger, and the slave flip flop is the negative level trigger.

o The output Q'=1 of the master flip flop is passed to the slave flip flop as an input K when the
input J set to 0 and K set to 1. The clock forces the slave flip flop to work as reset, and then the
slave copies the master flip flop.

o When J=1, and K=0, the output Q=1 is passed to the J input of the slave. The clock's negative
transition sets the slave and copies the master.

o The master flip flop toggles on the clock's positive transition when the inputs J and K set to 1. At
that time, the slave flip flop toggles on the clock's negative transition.

o The flip flop will be disabled, and Q remains unchanged when both the inputs of the JK flip flop
set to 0.
1. Master-Slave Flip Flop

X1

U1 U4 U7 U9 U10 2.5V
1
Key = Space
NAND3 NAND2 NAND2 NAND2

U2 X2
1
Key = Space U8 U12 U11 2.5V
U6
U3
1 NAND2 NAND2 NAND2
Key = Space NAND3

U13

NOT
2. SR Latch
S1 Q
reset
X1
Key = A
U1 2.5V

V1
5V NOR2

X3
S2 U2
2.5V
Q'
Key = A
set NOR2

3. Gates SR Flip Flop.

X1
Q
S1
U3 2.5V
Set U1
Key = A
NAND2
NAND2

S2
Enable
Key = A
V1
12V
X2 Q'

U2 2.5V
U4
S3
NAND2
NAND2
Key = A
Reset
Experiment.

Study of 3x8, 4x10, 4x16 decoder.

1. Study of 3x8 decoder

X1

U1 2.5V

S1 X2
U9 AND3
Key = A 2.5V
U2
NOT
V1 S2
12V
X3
AND3
U10
Key = A
U3 2.5V
S3 NOT
X4
Key = A AND3
U11
U4 2.5V

NOT
X5
AND3

U5 2.5V

X6
AND3

U6 2.5V

X7
AND3

U7 2.5V

X8
AND3

U8 2.5V

AND3
2. 8 to 3-line Encoder
The logical expression of the term A0, A1, and A2 are as follows:

A2=Y4+Y5+Y6+Y7
A1=Y2+Y3+Y6+Y7
A0=Y7+Y5+Y3+Y1
3. Study of 4 to 16 decoder
 4. 16 to 4 encoders.
Logical expression O0, O1, O2 and O3 using truth table.

O3 = Σ(8, 9, A, B, C, D, E, F)

O2 = Σ(4, 5, 6, 7, C, D, E, F)

O1 = Σ(2, 3, 6, 7, A, B, E, F)
O0 = Σ(1, 3, 5, 7, 9, B, D, F
Experiment
1. 1-Bit Magnitude Comparator.
X1
U1 A<B
U3 2.5V
A'
S1
A NOT X3
AND2
Key = A 2.5V
A=B
U5

NOR2
V1 S2 U2
12V
X2
Key = A
NOT B A>B
U4 2.5V
B

AND2

2. 4- Bit comparator.

U14 U6
U1
S1 U5

A3 NOT AND2 X1 A<B

NOR2
Key = A U7 AND2
U15
S2 U28 2.5V
U22
AND2
B3
Key = A NOT
U16 U8 AND2
S3 OR4
U2
U23
A2
NOT AND2 X2 A>B
Key = A
S4 U17 U9 NOR2
AND3
U29 2.5V
B2
Key = A NOT AND2 U24
S5
U18
A1 OR4
U10 AND3
Key = A
S6 U3 U25
NOT
B1 U19 AND2
U11
Key = A NOR2
V1 S7
12V AND4
U26
NOT AND2
A0 U20
A=B
Key = A X3
S8 U12
NOT U4 AND4
B0 U27 2.5V
Key = A U21
AND2
U13
NOR2
NOT AND4
AND2
 Experiment.
Multiplexer
1. 8 to 1 Line Multiplexer.

U13 U2
0
Key = Space
U14 AND4
U1
0
Key = Space
AND4
U15 U3 X1
0 U9
Key = Space 2.5 V
U16 AND4
U4
0
Key = Space
U17 OR8
0 AND4
U5
Key = Space
U18
0 AND4
U6
Key = Space
U19
0 AND4
U7
Key = Space

U20 AND4
U8
0
Key = Space

AND4
U10
U12 U11
NOT
NOT NOT

B C
A
U21
U22 U23
0
1 0
Key = Space
Key = Space Key = Space
s

2. 1×8 De-multiplexer
3. 1 x 16 De-multiplexer
4 Bit Binary Parallel Adder.

S1

Key = A X3
X1 X2 X4
V1 S2
12V 2.5V
2.5V 2.5V 2.5V
Key = A
U1
S3 1 15
A4 S4
3 A3 S3 2
8 A2 S2 6
10 A1 S1 9
Key = A X5
16 B4 C4 14
4 B3
7
S4 11
B2
B1 2.5V
13 C0
Key = A 7483N
S5

Key = A

S6

Key = A

S7

Key = A
S8

Key = A

7 Segments.

S1
U1
Key = A 7 A OA 13
VCC
1 B OB 12
2 C OC 11
6 10 5.0V
S2 D OD
9
3
OE
15
U3
~LT OF
5 ~RBI OG 14 CA
4 ~BI/RBO
Key = A
74LS47D
S3
A B C D E F G

Key = A
S4
VCC
5.0V
Key = A
Half Adder

S1

Key = A

X1
S2
2.5V
Key = A U1

5V XOR2 X2

2.5V
U2

AND2

V1