Unit-1

Introduction to
COA

Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
Computer Organisation and Architecture

BCS302
Unit-1: Introduction to Computer Organisation

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
KCS-302: Computer Organisation and Architecture
Introduction: Functional units of digital system and
their interconnections, buses, bus architecture, types
of buses and bus arbitration. Register, bus and
I
memory transfer. Processor organisation, general
registers organisation, stack organisation and
addressing modes.

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
Functional units of digital system and their interconnections

Functional Units

Input ALU

Memory
Output Control

I/O CPU

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
Input Devices
Input unit:
• Send data to function properly and be able to solve
problems.
• Feeds data and programs
• Eg: keyboard, a mouse, scanner .

Output Devices
Output unit:
• Receives both data & program statements to function
properly and be able to solve problems.
• Receive data and programs
• Eg: VDU .

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
Memory Unit
Stores programs and data.
There are Two classes of storage
• Primary storage
Fast
Program must be stored in memory while they are being
executed
Large number of semiconductor storage cells
Processed in words
There is byte addressing.
Memory access time.
Memory hierarchy - cache, main memory.
• Secondary storage - larger and cheaper.
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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
Arithmetic and Logic Unit (ALU)

Most of the operation are executed in ALU.

Performs all arithmetic calculations and take logical decisions.

Control Unit
All computer operations are controlled by the control Unit.
The control section directs the flow of traffic (Operations) and data. It
also maintains order within the computer.

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
 Types of Buses in Computer Architecture
Inside computer, there are many internal components. In order for
these components to communicate with each other they make use of
wires that are known as “Bus”.
A bus is a common pathway through which information flows from
one computer component to another. This pathway is used for
communication purpose and it is established between two or more
computer components.
There are different computer bus architecture:
Address bus

Data bus

CPU Control bus

RAM ROM I/O Other

Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad Next Slide
 Functions of Buses in Computers
Summary of functions of buses in computers
Data Sharing: All types of buses found in a computer transfer data
between the computer peripherals connected to it.
The buses transfer or send data in either serial or parallel method of data
transfer. This allows for the exchange of 1, 2, 4 or even 8 bytes of data
at a time. Buses are classified depending on how many bits they can
move at the same time, which means that we have 8-bit, 16-bit, 32-bit
or even 64-bit buses.
Addressing: A bus has address lines, which match those of the processor.
This allows data to be sent to or from specific memory locations.
Power: A bus supplies power to various peripherals connected to it.
Timing: The bus provides a system clock signal to synchronise the
peripherals attached to it with the rest of the system.
The expansion bus facilitates easy connection of more or additional
components and devices on a computer such as a TV card or sound
card.
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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
 Computer have two major types of buses:
System bus:- This is the bus that connects the CPU to main
memory on the motherboard. The system bus is also called the
front-side bus, memory bus, local bus, or host bus.
A number of I/O Buses, (I/O is an acronym for input/output),
connecting various peripherals devices to the CPU. These devices
connect to the system bus via a ‘bridge’ implemented in the
processor chipset. Other names for the I/O bus include “expansion
bus”, “external bus” or “host bus”.
Expansion Bus Types
These are some of the common expansion bus types that have ever
been used in computers:
ISA - Industry Standard Architecture
EISA - Extended Industry Standard Architecture
MCA - Micro Channel Architecture
VESA - Video Electronics Standards Association
PCI - Peripheral Component Interconnected
PCMCIA - Peripheral Computer Memory Card Industry Association (Also called PC bus)
SCSI - Small Computer Systems Interface.
AGP - Computer
Accelerated Graphics Port
Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
 Bus Arbitration
The device that is allowed to initiate data transfers on the bus at any
given time is called the bus master.

In a computer system there may be more than one bus master such as
processor, DMA controller etc.
They share the system bus. When current master provides control of
the bus, another bus master can acquire the control of the bus.
Bus arbitration is the process by which the next device to become the
bus master is selected and bus mastership is transferred to it.

The selection of bus master is usually done on the priority basis.

There are two approaches of bus arbitration: Centralised and

Distributed.

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
1. Centralised arbitration

In centralised bus arbitration, a single bus arbiter performs the

required arbitration.

The bus arbiter may be the processor or a separate controller

connected to the bus.
There are three different arbitration schemes that use the centralised
bus arbitration approach.

There schemes are:

a) Daisy chaining
b) Polling method
c) Independent request

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
 a) Daisy chaining
Master 1 Master 2 Master N
Bus access Bus access … Bus access
logic logic logic

Bus grant
Bus request
Controller
Bus busy

Figure: The system connections for Daisy chaining method.

It is simple and cheaper method. All masters make use of the same line
for bus request. In response to the bus request the controller sends a bus
grant if the bus is free.
The bus grant signal serially propagates through each master until it
encounters the first one that is requesting access to the bus. This master
blocks the propagation of the bus grant signal, activities the busy line
and gains control of the bus.
Therefore any other requesting module will not receive the grant signal
and hence cannot get the bus access.
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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
 b) Polling Method
Master 1 Master 2 Master N
Bus grant
Bus access Bus access … Bus access
logic logic logic

Controller
Bus request
Bus busy
Figure: The system connections for Polling Method.

In this the controller is used to generate the addresses for the master.
Number of address line required depends on the number of master
connected in the system.
For example, if there are 8 masters connected in the system, at least
three address lines are required.
In response to the bus request controller generates a sequence of master
address. When the requesting master recognises its address, it activated
the busy line and begins to use the bus. Next Slide
Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
 c) Independent Request
Master 1 Master 2 Master N
Bus access Bus access … Bus access
logic logic logic
Bus grant 1
Bus request 1
Bus grant 2
Bus request 2
Controller ..
.. Bus grant N
Bus request N
Bus busy
Figure: The system connections for the independent request scheme

In this scheme each master has a separate pair of bus request and bus
grant lines and each pair has a priority assigned to it.

The built in priority decoder within the controller selects the highest
priority request and asserts the corresponding bus grant signal.

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
2. Distributed arbitration
In distributed arbitration, all devices participate in the selection of the
next bus master.
In this scheme each device on the bus is assigned a 4-bit identification
number.

The number of devices connected on the bus when one or more

devices request for the control of bus, they assert the start-arbitration
signal and place their 4-bit ID numbers on arbitration lines, ARB0
through ARB3.

More than one device can place their 4-bit ID number to indicate that
they need to control of bus.

When two or more devices place their ID number on bus lines then it
is necessary to identify the highest ID number on bus lines.

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
Consider that two devices A and B, having ID number 1 and 6,
respectively are requesting the use of the bus.
Device A puts the bit pattern 0001, and device B puts the bit pattern
0110. Inverter buffers code seen by both devices is 0111.
Each device compares the code formed on the arbitration line to its
own ID, starting from the most significant bit. If it finds the difference
at any bit position, it disables its drives at that bit position and for all
lower-order bits.

In our example, device detects a different on line ARB2 and hence it

disables its drives on line ARB2, ARB1 and ARB0.

The decentralised arbitration offers high reliability because operation of

the bus is not dependent on any single device.

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
 Register Bus and Memory Transfers (Page:97)
A typical digital computer has many registers, and paths must be
provided to transfer information from one register to another.
The number of wires will be excessive if separate lines are used
between each register and all other registers in the system.
A more efficient scheme for transferring information between
registers in a multiple-register configuration is a common bus
system.
A bus structure consists of a set of common lines, one for each bit
of a register, through which binary information is transferred one
at a time.
Control signals determine which register is selected by the bus
during each particular register transfer.
One way of constructing a common bus system is with
multiplexers. The multiplexers select the source register whose
binary information is then placed on the bus.
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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
The construction of a bus system for four registers is shown following Figure.
4-line
common
S1 bus
S0

4x1 4x1 4x1 4x1

MUX 3 MUX 2 MUX 1 MUX 0

3210 3210 3210 3210

S1 S0 RS
D2 C2 B2 A2 D1 C1 B1 A1 D0 C0 B0 A0
0 0 A
0 1 B
1 0 C
D2 D1D0 C2 C1 C0 B2 B1 B0 A2 A1 A0 1 1 D

3210 3210 3210 3210

Register D Register C Register B Register A

Figure: Bus System for 4- register Next Slide

Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
Each register has four bits, numbered 0 through 3.
The bus consists of four 4 x 1 multiplexers each having four data
inputs, 0 through 3, and two selection inputs, S1 and S0.
In order not to complicate the diagram with 16 lines crossing each
other, we use labels to show the connections from the outputs of
the registers to the inputs of the multiplexers.
For example, output 1 of register A is connected to input 0 of MUX
1 because this input is labeled A1.
The diagram shows that the bits in the same significant position in
each register are connected to the data inputs of one multiplexer to
form one line of the bus.
Thus MUX 0 multiplexes the four 0 bits of the registers, MUX 1
multiplexes the four 1 bits of the registers, and similarly for the
other two bits.

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
The two selection lines S1 and S0 are connected to the selection
inputs of all four multiplexers.
The selection lines choose the four bits of one register and transfer
them into the four-line common bus.
When S1S0 = 00, the 0 data inputs of all four multiplexers are
selected and applied to the outputs that form the bus.
This causes the bus lines to receive the content of register A since
the outputs of this register are connected to the 0 data inputs of the
multiplexers.
Similarly, register B is selected if S1S0 = 01, and so on.

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
In general, a bus system will multiplex k registers of n bits each to
produce an n-line common bus.
The number of multiplexers needed to construct the bus is equal to
n, the number of bits in each register.
The size of each mult plexer must be k x 1 since it multiplexes k
data lines.
For example, a common bus for eight registers of 16 bits each
requires 16 multiplexers, one for each line in the bus.

Each multiplexer must have eight data input lines and three
selection lines to multiplex one significant bit in the eight registers.

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
i­
The transfer of information from a bus into one of many
destination registers can be accomplished by connecting the bus
lines to the inputs of all destination registers and activating the
load control of the particular destin tion register selected.
The symbolic statement for a bus transfer may mention the bus or
its presence may be implied in the statement.
When the bus is includes in the statement, the register transfer is
symbolised as follows:
BUS ← C, R1 ← BUS
The content of register C is placed on the bus, and the content of
the bus is loaded into register R1 by activating its load control
input.
If the bus is known to exist in the system, it may be convenient just
to show the direct transfer. R1 ← C,
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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
a­
S1
S0

4x1 4x1 4x1 4x1

MUX 3 MUX 3 MUX 3 MUX 3

3210 3210 3210 3210

D2 C2 B2 A2 D1 C1 B1 A1 D0 C0 B0 A0

D2 D1D0 C2 C1 C0 B2 B1 B0 A2 A1 A0

3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0
LD LD LD LD
Register D Register C Register B Register A

d0
2x4
d1 Decoder
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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
 A ← C can be represented as:

BUS ← C Then
A ← BUS
Step 1: put S1 S0 = 10

Step 2: put d1 d0 = 00

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
 Bus System using Three-State BUS buffer (Page: 100)
Three state BUS buffer
A bus system can be constructed with three-state gates instead of
multiplexers.
A three-state gate is a digital circuit that exhibits three states.
Two of the states are signals equivalent to logic 1 and 0 as in a
conventional gate.
The third state is a high-impedance state.
The high-impedance state behaves like an open circuit, which
means that the output is disconnected and does not have a logic
signi icance.

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
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 Normal input A Output Y = A if C = 1
High-impedance if C = 0
Control input C
Figure: Graphics symbols for three-state buffer

Bus line for bit 0

A0
B0
C0
D0

S1 0
Select
S0
2x4 1
Decoder2
Enable E 3

Figure: Bus line with three state-buffers.

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
❴
 A0
B0 A1
C0 B1 A2
D0 B2 A3
C1
C2 B3
D1
D2 C3
D3

S0
2x4 S0
S1
Decoder 2x4 S0
S1
Decoder 2x4 S0
S1
Decoder 2x4
S1
Decoder

S S0 R
C3 C2 C1 C0 B3 B2 B1 B0 A3 A2 A1 A0
10 0 S
A
D3 D2 D1 D0

Register D Register C Register B Register A 0 1 B

1 0 C
1 1 D
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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
 Register Transfer Language

A digital system is an interconnection of digital hardware module

that accomplish a specific information-processing task.
A digital system is an interconnection of digital hardware module
that accomplish a specific information-processing task.
Digital systems vary in size and complexity from a few integrated
circuits to a complex of interconnected and interacting digital
computers.
Digital system design invariably uses a modular approach.
The modules are constructed from such digital components as
registers, decoders, arithmetic elements, and control logic.

The various modules are interconnected with common data and

control paths to from a digital computer system.

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
Digital modules are best defined by the registers they contain and
the operations that are performed on the data stored in them.
The operations executed on data stored in registers are called
micro operations.
A micro operation is an elementary operation performed on the
information stored in one or more registers.
The result of the operation may replace the previous binary
information of a register or may be transferred to another register.

Examples of micro operations are shift, count, clear, and load.

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
 Some of the digital co ponents are registers that implement
micro-operations.
For example, a counter with parallel load is capable of performing
the micro-operations increment and load.
A bidirectional shift register is capable of performing the shift right
and shift left micro-operations.
The internal hardware organisation of a digital computer is best
defined by specifying:
1. The set of registers it contains and their function.
2. The sequence of micro-operations performed on the binary
information stored in the registers.
3. The control that initiates the sequence of micro-operations.

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
m­
RTL: The symbolic notation used to describe the micro-operation
transfers among registers is called a register transfer
language.

Computer registers are designated by capital letters (sometimes

followed by numerals) to denote the function of the register.

For example, the register that holds an address for the memory unit
is usually called a memory address register and is designated by
the name MAR.

Other designations for registers are PC (for program counter), IR

(for instruction register), and R1 (for processor register).

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
The individual flip-flops in an n-bit register are numbered in
sequence from 0 through n-1, starting from 0 in the rightmost
position and increasing the numbers toward the left.
R1 7 6 5 4 3 2 1 0
a) Register R b) Showing individual bits

15 0 15 87 0
R2 PC(H) PC(L)

c) Numbering of bits d) Divided into two parts

The name of the 16-bit register is PC . The symbol PC(0-7) or

PC(L) refers to the low-order byte and PC(8-15) or PC(H) to the
high-order byte.

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
 Register Transfer:
Information transfer from one register to another is designated in
sy bolic form by means of a replacement operator. The statement
R2← R1
denotes a transfer of the content of register R1 into register R2. It
designates a replacement of the content of R2 by the content of Rl.
The content of the source register R1 does not change after the
transfer.
Normally, we want the transfer to occur only under a
predetermined control condition. This can be shown by means of
an if-then statement.
If(P = 1) then (R2←R1)
P : R2←R1

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
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Example:

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
Registers are denoted by capital letters, and numerals may follow
the letters.
Parentheses are used to denote a part of a register by specifying the
range of bits or by giving a symbol name to a portion of a register.
The arrow denotes a transfer of information and the direction of
transfer.

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
A comma is used to separate two or more operations that are
executed at the same time. The statement:
T: R2 ← R1, R1 ← R2

The above statement denotes an operation that exchanges the

contents of two registers during one common clock pulse provided
that T=1.
This simultaneous operation is possible with registers that have
edge-triggered flip-flops.

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
 Memory Transfer:
The transfer of information from a memory word to the outside
environment is called a read operation.
The transfer of new information to be stored into the memory is
called a write operation.
A memory word will be symbolised by the letter M .

The particular memory word among the many available is selected

by the memory address during the transfer.

It is necessary to specify the address of M when writing memory

transfer operations.

This will be done by enclosing the address in square brackets

following the letter M.
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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
Consider a memory unit that receives the address from a register,
called the address register, symbolised by AR.
The data are transferred to another register, called the data register,
symbolised by DR. The read operation can be stated as follows:

Read: DR ←M[AR]
This causes a transfer of information into DR from the memory
word M selected by the address in AR.
The write operation transfers the content of a data register to a
memory word M selected by the address.
Assume that the input data are in register Rl

Write: M[AR]← R1

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
General Register Organisation (Chapter-8, Page-243)

Register
set

Control

Arithmetic
Logic Unit
Major components of CPU
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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
 Clock
Register set with common ALU Input

R1
R2
R3
R4
R5
R6
R7

Load
(7 lines)

3x8 { MUX-A MUX-B }

decoder
SELA SELB

SELD OPR
{ Arithmetic Logic Unit
(ALU)
3 3 3 5
Output
SELA SELB SELD OPR

Block diagram Control word

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
 When a large number of registers are included in the CPU, it is most
efficient to connect them through a common bus system.
The registers comm nicate with each other not only for direct data
transfers, but also while perfor ing various micro-operations. Hence
it is necessary to provide a common unit that can perform all the
arithmetic, logic, and shift micro-operations in the processor.
A bus organisation for seven CPU registers is shown in Figure. The
output of each register is connected to two multiplexers (MUX) to
form the two buses A and B.
The selection lines in each multiplexer select one register or the input
data for the particular bus.
The A and B buses form the inputs to a common arithmetic logic unit
(ALU).
The operation selected in the ALU dete mines the arithmetic or logic
micro-operation that is to be performed.
The result of the micro-operation is available for output data and also
goes into the inputs of all the registers.
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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
u­
m­
r­
 The register that receives the information from the output bus is
selected by a decoder.
The decoder activates one of the register load inputs, thus providing a
transfer path between the data in the output bus and the inputs of the
selected destination register.
The control unit that operates the CPU bus system directs the
information flow through the registers and ALU by selecting the
various components in the system. For example, to perform the
operation
R1 ← R2 +R3
the control must provide binary selection variables to the following
selector inputs:
1. MUX A selector (SELA): to place the content of R2 into bus A.
2. MUX B selector (SELB): to place the content of R3 into bus B.
3. ALU operation selector (OPR): to provide the arithmetic addition A + B.
4. Decoder destination selector (SELD): to transfer the content of the output
bus into R1.
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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
 Control Word

Encoding of Register Selection

Binary Fields
SELA SELB SELD
Code
000 Input Input None
001 R1 R1 R1
010 R2 R2 R2
011 R3 R3 R3
100 R4 R4 R4
101 R5 R5 R5
110 R6 R6 R6
111 R7 R7 R7

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
 Encoding of ALU Operations
OPR
Operation Symbol
Select
00000 Transfer A TSFA
00001 Increment A INCA
00010 Add A + B ADD
00101 Subtract A - B SUB
00110 Decrement A DECA
01000 AND A and B AND
01010 OR A and B OR
01100 XOR A and B XOR
01110 Complement A COMA
10000 Shift right A SHRA
11000 Shift left A SHLA

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
 Examples of Microoperations for the CPU
Symbolic Designation
Microoperation Control Word
SELA SELB SELD OPR
R1 ← R2 - R3 R2 R3 R1 SUB 010 011 001 00101
R4 ← R4 ∨ R5 R4 R5 R4 OR 100 101 100 01010
R6 ← R6 + 1 R6 — R6 INCA 110 000 110 00001
R7 ← R1 R1 — R7 TSFA 001 000 111 00000
Output ← R2 R2 — None TSFA 010 000 000 00000
Output ← Input Input — None TSFA 000 000 000 00000
R4 ← shl R4 R4 — R4 SHLA 100 000 100 11000
R5 ← 0 R5 R5 R5 XOR 101 101 101 01100

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
 Stack Organisation
A useful feature that is included in the CPU of most computers is a
stack or last-in, first-out (LIFO) list. A stack is a storage device that
stores information in such a manner that the item stored last is the first
item retrieved.

The stack in digital computers is essentially a memory unit with an

address register that can count only (after an initial value is loaded
into it).

The register that holds the address for the stack is called a stack
pointer (SP) because its value always points at the top item in the
stack.

The register that holds the address for the stack is called a stack
pointer (SP) because its value always points at the top item in the
stack.
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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
 Register Stack
EMTY 63 A stack can be placed in a portion of a large memory or it can
be organised as a collection of a finite number of memory
words or registers.
FULL
Figure shows the organisation of a 64-word register stack.
The stack pointer register SP contains a binary number whose
4 value is equal to the address of the word that is currently on
SP C 3
2
top of the stack.
B
A 1 Three items are placed in the stack: A, B, and C, in that order.
0
Item C is on top of the stack so that the content of SP is now 3.
DR To remove the top item, the stack is popped by reading the
Block diagram of a 64-word memory word at address 3 and decrementing the content of
stack.
SP.
Item B is now on top of the stack since SP holds address 2.
To insert a new item, the stack is pushed by incrementing SP and writing a word in
the next-higher location in the stack.
Note that item C has been read out but not physically removed.
This does not matter because when the stack is pushed, a new item is written in its place.
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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
In a 64-word stack, the stack pointer contains 6-bits because 26 = 64.

Since SP has only six bits, it cannot exceed a number greater than 63
(111111 in binary).

When 63 is incremented by 1, the result is 0 since 111111 + 1 =

1000000 in binary, but SP can accommodate only the six least
significant bits.

Similarly, when 000000 is decremented by 1, the result is 111111.

The one-bit register FULL is set to 1 when the stack is full, and the
one-bit register EMTY is set to 1, when the stack is empty of items.

DR is the data register that holds the binary data to be written into or
read out of the stack.

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
 Push in Register Stack
Initially, SP is cleared to 0, EMTY is set to 1, and FULL is cleared to
0, so that SP points to the word at address 0 and the stack is marked
empty and not full.
If the stack is not full (if FULL = 0), a new item is inserted with a
push operation.
The push operation is implemented with the following sequence of
micro operations;
SP ← SP +1 Increment Stack Pointer
M[SP] ← DR Write Item on TOS
If (SP = 0) then (FULL ← 1) Check if stack is full
EMTY ← 0 Mark the stack not empty

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
The stack pointer is incremented so that it points to the address of the
next-higher word.
A memory write operation inserts the word from DR into the top of
the stack.
Note that SP holds the address of the top of the stack and that M[SP]
denotes the memory word specified by the address presently available
in SP.
The first item stored in the stack is at address L The last item is stored
at address 0.
If SP reaches 0, the stack is full of items, so FULL is set to 1.
This condition is reached if the top item prior to the last push was in
location 63 and, after incrementing SP, the last item is stored in
location 0.
Once an item is stored in location 0, there are no more empty registers
in the stack.
If an item is written in the stack, obviously the stack cannot be empty,
so EMTY is cleared to 0. Next Slide
Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
 POP in Register Stack
A new item is deleted from the stack if the stack is not empty (if
EMTY = 0). The pop operation consists of the following sequence of
micr -operations:

DR ← M[SP] Read item from the top of stack

SP ← SP - 1 Decrement stack pointer
If (SP = 0) then (EMTY ← 1) Check if stack is empty
FULL ← 0 Mark the stack not full
The top item is read from the stack into DR.
The stack pointer is then decremented. If its value reaches zero, the
stack is empty, so EMTY is set to 1.
This condition is reached if the item read was in location 1.
Once this item is read out, SP is decremented and reaches the value 0,
which is the initial value of SP.

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
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Note that if a pop operation reads the item from location 0 and then
SP is decremented, SP changes to 111111, which is equivalent to
decimal 63.
In this configuration, the word in address 0 receives the last item in
the stack.
Note also that an erroneous operation will result if the stack is pushed
when FULL = 1 or popped when EMTY = 1

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
 Memory Stack
Memory unit Address The implementation is done by assigning a
1000 portion of memory to a stack operation and
PC Program using a processor register as a stack pointer.
(instructions)
Portion of computer memory partitioned
into three segments: program, data, and
AR 2000 stack.
Data The program counter PC points at the
(operands) address of the next instruction in the
program.
3000
The address register AR points at an array
Stack of data. The stack pointer SP points at the
top of the stack.
3997 PC is used during the fetch phase to read an
SP 3998 instruction.
3999 The three registers are connected to a
4000 common address bus, and either one can
4001 provide an address for memory.
AR is used during the execute phase to read
an operand.
DR
Computer memory with program, data SP is used to push or pop items into or from
and stack segments. the stack. Next Slide
Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
 PUSH in Memory Stack
We assume that the items in the stack communicate with a data
register DR.
A new item is inserted with the push operation as follows:
SP ← SP - 1
M[SP] ← DR
The stack pointer is decremented so that it points at the address of the
next word.
A memory write operation inserts the word from DR into the TOS.
POP in Memory Stack
A new item is deleted with a pop operation as follows:
DR ← M[SP]
SP ← SP + 1
The top item is read from the stack into DR . The stack pointer is then
incr mented to point at the next item in the stack.
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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
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 Stack Limits
Most computers do not provide hardware to check for stack overflow
(full stack) or underflow (empty stack).
The stack limits can be checked by using two processor registers: one
to hold the upper limit (3000 in this case), and the other to hold the
lower limit (4001 in this case).
After a push operation, SP is compared with the upper-limit register
and after a pop operation, SP is co pared with the lower-limit
register.
The two micro-operations needed for either the push or pop are :
1. an access to memory through SP
2. updating SP
Which of the two micr operations is done first and whether SP is
updated by incrementing or decr menting depends on the organisation
of the stack.

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
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In memory-Stack, stack grows by decreasing the memory address.
The stack may be constructed to grow by increasing the memory
address as in Register-Stack.
In such a case, SP is incremented for the push operation and
decremented for the pop operation.
A stack may be constructed so that SP points at the next empty
location above the top of the stack.
In this case the sequence of micro-operations must be interchanged.
A stack pointer is loaded with an initial value. This initial value must
be the bottom address of an assigned stack in memory.
SP is automa ically decremented or incremented with every push or
pop operation.
The advantage of a memory stack is that the CPU can refer to it
without having to specify an address, since the address is always
available and automatically updated in the stack pointer.

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
 Reverse Polish Notation
A stack organisation is very effective for evaluating arithmetic
expressions.
The common mathematical method of writing arithmetic expressions
imposes di ficulties when evaluated by a computer.
The common arithmetic expressions are written in infix notation, with
each operator written between the operands.Consider the simple
arithmetic expression: A*B + C*D
To evaluate this arithmetic expression it is necessary to compute the
product A*B, store this product while computing C*D, and then sum
the two products.
From this example we see that to evaluate arithmetic expressions in
infix notation it is necessary to scan back and forth along the
expression to determine the next operation to be performed.

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
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The Polish mathematician Lukasiewicz showed that arithmetic
expressions can be represented in prefix notation.
This representation, often referred to as Polish notation, places the
operator before the operands.
The postfix notation, referred to as reverse Polish notation (RPN),
places the operator after the operands.
The following examples demonstrate the three representations:
A+B Infix Notation
+AB Prefix or Polish Notation
AB+ Postfix or Reverse Polish Notation
The RPN is in a form suitable for stack manipulation. The expression
A*B + C*D
is written in RPN as
AB*CD*+
and is evaluated as follows:
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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
 Stack operation to evaluate A*B+C*D RPN: AB*CD*+

→ D

→ B → C C

→ A A → A*B A*B A*B

A B * C D

→ C*D

A*B → A*B+C*D

* +
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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
 Instruction Formats (Page-247)
The most common fields found in instruction formats are:
1. An operation code field that specifies the operation to
be performed.
2. An address field that designates a memory address or
a processor register.
3. A mode field that specifies the way the operand or the
effective address is determined.
Computers may have instructions of several different lengths
containing varying number of addresses.
The number of address fields in the instruction format of a computer
depends on the internal organisation of its registers.
Most computers fall into one of three types of CPU organisations:
1. Single accumulator organisation.
2. General register organisation.
3. Stack organisation. Next Slide
Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
Accumulator-type organisation is the basic computer has an
accumulator. All operations are performed with an implied
accumulator register.
The instruction format in this type of computer uses one address field.
For example, the instruction that specifies an arithmetic addition is
defined by an assembly language instruction as
ADD X
where X is the address of operand. It results AC ← AC + M[X].
General register type of organisation was discussed. The instruction
format in this type of computer needs three register address fields.
Thus the instruction for an arithmetic addition may be written in an
assembly language as
ADD R1, R2, R3 to denote R1 ← R2 + R3.
number of address field can be reduced.
ADD R1, R2 to denote R1 ← R1 + R2.

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
 MOV R1, R2 R1 ← R2
ADD R1, X R1 ← R1 + M[X]
The stack-organised CPU was presented. Computers with stack
organisation would have PUSH and POP instructions which require an
address field. Thus the instruction
PUSH X
will push the word at address X to the top of the stack. The stack
pointer is updated automatically. Operation-type instructions do not
need an address field in stack-organised computers. This is because the
operation is performed on the two items that are on top of the stack.
The instruction ADD
in a stack computer consists of an operation code only with no address
field. This operation has the effect of popping the two top numbers
from the stack, adding the numbers, and pushing the sum into the stack.
There is no need to specify operands with an address field since all
operands are implied to be in the stack.
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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
Example: Evaluate the following arithmetic statement using zero,
one, two and three address instructions. X = (A + B)*(C + D)
Three address Instructions:

ADD R1, A, B R1 ←M[A]+M[B]

ADD R2, C, D R2 ←M[C]+M[D]
MUL X, R1, R2 M[X] ←R1*R2

Two address Instructions:

MOV R1, A R1 ←M[A]
ADD R1, B R1 ←R1+M[B]
MOV R2, C R2 ←M[C]
ADD R2, D R2 ←R2+M[D]
MUL R1, R2 R1 ←R1*R2
MOV X, R1 M[X] ←R1

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
One address Instructions: X = (A + B)*(C + D)
One-address instructions use an implied accumulator (AC) register
for all data manipulation. For multiplication and division there is a
need for a second register. However, here we will neglect the second
register and assume that the AC contains the result of all operations.

LOAD A AC ←M[A]
ADD B AC ←AC+M[B]
STORE T M[T] ←AC
LOAD C AC ←M[C]
ADD D AC ←AC + M[D]
MUL T AC ←AC * M[T]
STORE X M[X] ←AC

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
Zero address Instructions: X = (A + B)*(C + D)
A stack-organised computer does not use an address field for the
instructions ADD and MUL.
The PUSH and POP instructions are used.

To evaluate arithmetic expressions in a stack computer, it is

necessary to convert the expression into RPN.
The name "zero-address" is given to this type of computational
instructions.
PUSH A TOS ←A
PUSH B TOS ←B
ADD TOS ←(A+B)
PUSH C TOS ←C
PUSH D TOS ←D
ADD TOS ←(C+D)
MUL TOS ←(C+D)*(A+B)
POP X M[X] ←TOS
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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
 RISC Instructions: X = (A + B)*(C + D)
The instruction set of a typical RISC processor is restricted to the
use of load and store instructions when communicating between
me ory and CPU.
All other instructions are executed within the registers of the CPU
without referring to memory.
A program for a RISC-type CPU consists of LOAD and STORE
instructions that have one memory and one register address, and
computational-type instructions that have three addresses with all
three specifying processor registers.
LOAD R1, A R1 ←M[A]
LOAD R2, B R2 ←M[B]
LOAD R3, C R3 ←M[C]
LOAD R4, D R4 ←M[D]
ADD R1, R1, R2 R1 ←R1 + R2
ADD R3, R3, R2 R3 ←R3 + R4
MUL R1, R1, R3 R1 ←R1 * R3
STORE X, R1 M[X] ←R1
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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
 Addressing Modes
The operation field of an instruction specifies the operation to be
performed.
This operation must be executed on some data stored in computer
registers or memory words.
The way the operands are chosen during program execution is
dependent on the addressing mode of the instruction.
The addressing mode specifies a rule for interpreting or modifying the
address field of the instruction before the operand is actually
referenced.
Computers use addressing mode techniques for the purpose of
accommodating one or both of the following provisions:
1. To give programming versatility to the user by providing such
facilities as pointers to memory, counters for loop control,
indexing of data, and program relocation.
2. To reduce the number of bits in the addressing field of the
instruction.
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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
Example of Instruction Format to Illustrate Addressing Modes
Instruction format with mode field
Opcode Mode Address
The operation code specifies the operation to be performed. The mode
field is used to locate the operands needed for the oper tion.
There may or may not be an address field in the instruction. If there is
an address field, it may designate a memory address or a processor
register.
The instruction may have more than one address field, and each
address field may be associated with its own particular addressing
mode.
Addressing modes modify the address field of the instru tion, but,
there are two modes that need no address field at all. These are the
implied and immediate modes.

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
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 List of Addressing Modes
1. Implied Mode
2. Immediate Mode
3. Register Mode
4. Register Indirect Mode
5. Auto-increment or Auto-decrement Mode
6. Direct Address Mode
7. Indirect Address Mode
8. Relative Address Mode
9. Index Addressing Mode
10. Base Register Addressing Mode

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
 1. Implied Mode
In this mode the operands are specified implicitly in the definition of
the instruction.
For example, the instruction "complement accumulator" is an
implied-mode instruction because the operand in the accum lator
register is implied in the definition of the instruction.
In fact, all register reference instructions that use an accumulator are
implied-mode instructions.
Zero-address instructions in a stack-organised computer are implied-
mode effective address instructions since the operands are implied to
be on top of the stack.

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad

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 2. Immediate Mode
In this mode the operand is specified in the instruction itself. In other
words, an immediate-mode instruction has an operand field rather
than an address field.
The operand field contains the actual operand to be used in
conjunction with the operation specified in the instruction.
Immediate-mode instructions are useful for initialising registers to a
constant value.
3. Register Mode
Address field of an instruction may specify either a memory word or a
processor register.
When the address field specifies a processor register, the instruction is
said to be in the register mode.
In this mode the operands are in registers that reside within the CPU.
The particular register is selected from a register field in the
instruction. A k-bit field can specify any one of 2k registers.
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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
 4. Register Indirect Mode
In this mode the instruction specifies a register in the CPU whose
contents give the address of the operand in memory. In other words,
the selected register contains the address of the operand rather than
the operand itself.
Before using a register indirect mode instruction, the pr grammer
must ensure that the memory address of the operand is placed in the
processor register with a previous instruction.
A reference to the register is then equivalent to specifying a memory
address.
The advantage of a register indirect mode instruction is that the
address field of the instruction uses fewer bits to select a register than
would have been required to specify a memory address directly.

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
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 5. Auto-increment or Auto-decrement Mode
This is similar to the register i direct mode except that the register is
incremented or decremented after (or before) its value is used to
access memory.
When the address stored in the register refers to a table of data in
memory, it is necessary to increment or decrement the register after
every access to the table.
This can be achieved by using the increment or decrement instruction.
However, because it is such a common requirement, some computers
incorporate a special mode that aut matically increments or
decrements the content of the register after data access.

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
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 Effective Address
The address field of an instruction is used by the control unit in the
CPU to obtain the operand from memory.
Sometimes the value given in the address field is the address of the
operand, but sometimes it is just an address from which the address of
the operand is calculated.
To differentiate among the various addressing modes it is necessary to
distinguish between the address part of the instruction and the
effective address used by the control when executing the instruction.
The effective address is defined to be the memory address obtained
from the computation dictated by the given addressing mode.
The effective address is the address of the operand in a computational
type instruction. It is the address where control branches in response
to a branch-type instruction.

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
 6. Direct Address Mode

In this mode the effective address is equal to the address part of the
instruction.
The operand resides in memory and its address is given directly by
the address field of the instruction.

In a branch-type instruction the address field specifies the actual

branch address.

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
 7. Indirect Address Mode
In this mode the address field of the instruction gives the address
where the effective address is stored in memory.
Control fetches the instruction from memory and uses its address part
to access me ory again to read the effective address.
A few addressing modes require that the address field of the
instruction be added to the content of a specific register in the CPU.
The effective address in these modes is obtained from the following
computation:
effective address = address part of instruction + content of CPU register

The CPU register used in the computation may be the program

counter, an index register, or a base register. In either case we have a
different addressing mode which is used for a different application.

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
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 8. Relative Address Mode

In this mode the content of the program counter is added to the

address part of the instruction in order to obtain the effective address.
The address part of the instruction is usually a signed number (in 2's
complement representation) which can be either positive or negative.
When this number is added to the content of the program counter, the
result pr duces an effective address whose position in memory is
relative to the address of the next instruction.
Example:
Assume that the program counter contains the number 825 and the
address part of the instruction contains the number 24.
The instruction at location 825 is read from memory during the fetch
phase and the program counter is then incremented by one to 826.
The effective address computation for the relative address mode is
826 + 24 = 850. This is 24 memory locations forward from the
address of the next instruction.
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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
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Relative addressing is often used with branch-type instru tions when
the branch address is in the area surrounding the instruction word
itself.
It results in a shorter address field in the instruction format since the
relative address can be specified with a smaller number of bits
compared to the number of bits required to designate the entire
memory address.

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
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 9. Index Addressing Mode
In this mode the content of an index register is added to the address
part of the instruction to obtain the effective address.
The index register is a special CPU register that contains an index
value. The address field of the instruction defines the beginning
address of a data array in memory.
Each operand in the array is stored in memory relative to the
beginning address. The distance between the beginning address and
the address of the operand is the index value stored in the index
register.
Any operand in the array can be accessed with the same instruction
provided that the index register contains the correct index value. The
index register can be incremented to facilitate access to consecutive
operands.

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
If an inde type instruction does not include an address field in its
format, the instruction converts to the register indirect mode of
operation.
Some computers dedicate one CPU register to function solely as an
index register.
This register is involved implicitly when the index-mode instruction
is used. In computers with many processor registers, any one of the
CPU registers can contain the index number. In such a case the
register must be specified explicitly in a register field within the
instruction format.

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
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 10. Base Register Addressing Mode
In this mode the content of a base register is added to the address part of the
instruction to obtain the effective address.
This is similar to the indexed addressing mode except that the register is now called
a base register instead of an index register.
The difference between the two modes is in the way they are used rather than in the
way that they are computed. An index register is assumed to hold an index number
that is relative to the address part of the instruction.
A base register is assumed to hold a base address and the address field of the
instruction gives a displacement relative to this base address. This addressing
mode is used in computers to facilitate the relocation of programs in memory.

When programs and data are moved from one segment of memory to another, as
required in multiprogramming systems, the address values of instructions must
reflect this change of position.

With a base register, the displacement values of instructions do not have to change.
Only the value of the base register requires updating to reflect the beginning of a
new memory segment.

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
 Numerical Example (Page:266)
Address Memory
The two-word instruction at address
200 Load to AC Mode
200 and 201 is a “Load to AC"
R1 = 400 201 Address = 500 instruction with an address field equal
202 Next instruction to 500.
The first word of the instruction
specifies the operation code and mode,
and the second word specifies the
XR = 100 399 450 address part.
400 700 PC has the value 200 for fetching this
instruction. The content of processor
AC 500 800 register R1 is 400, and the content of an
index register XR is 100.
600 900 AC receives the operand after the
instruction is executed.
702 325
The mode field of the instruction can
800 300 specify any one of a number of modes.
Numerical example for addressing modes For each possible mode we calculate the
effective address and the operand that
must be loaded into AC.
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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
 Tabular List of Numerical Example
S Effective Content
Addressing Mode
L Address of AC
1 Direct address 500 800
2 Immediate operand 201 500
3 Indirect address 800 300
4 Relative address 702 325

1. In the direct address mode the effective address is the address part of the instruction
500 and the operand to be loaded into AC is 800.
2. In the immediate mode the second word of the instruction is taken as the operand
rather than an address, so 500 is loaded into AC. (The effective address in this case is
201.)
3. In the indirect mode the effective address is stored in memory at address 500. The
effective address is 800 and the operand is 300.
4. In the relative mode the effective address is 500 + 202 = 702 and the operand is 325.
(Note that the value in PC after the fetch phase and during the execute phase is 202.)

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Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
 Tabular List of Numerical Example
S Addressing Mode Effective Content
L Address of AC
1 Direct address 500 800
2 Immediate operand 201 500
3 Indirect address 800 300
4 Relative address 702 325
5 Indexed address 600 900
6 Register — 400
7 Register indirect 400 700
8 Auto-increment 400 700
9 Auto-decrement 399 450
5. Index mode: Effective address is XR + 500 = 100 + 500 = 600 and the operand is 900.
6. Register mode: the operand is in R1 and 400 is loaded into AC. (There is no effective
address in this case.)
7. Register indirect mode: the effective address is 400, equal to the content of R1 and the
operand loaded into AC is 700.
8. Auto-increment mode: is the same as the register indirect mode except that R1 is
incremented to 401 after the execution of the instruction.
9. Auto-decrement mode: decr ments R1 to 399 prior to the execution of the instruction.
The operand loaded into AC is now 450. Next Slide
Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
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 Do numerical 8.11 to 8.18

End of Unit-1

THANK YOU
Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad
 Memory Elements
Reset-Set Flip Flop/Latch (RS-Flip Flop)
Truth Table of RS-Flip Flop
R Q S R Q Q' Comment
0 1 0 1 Reset
1 0 1 0 Set

S Q' 0 0 No Change
1 1 Not Allowed

Computer Organisation and Architecture, Dr. Rakesh Ranjan, Department of Information Technology, ABES EC, Gaziabad