Roll No: __________ Batch: _____

DOES
Name:_______________________

______________________

T.Y.B.Sc. (Electronic Science)

Laboratory Handbook
ELECTRONIC-SCIENCE Practical I and III

Contributors:
Faculty members of
Department of Electronic Science

Department of Electronic Science

FERGUSSON COLLEGE
(AUTONOMOUS), PUNE

1
 ELS3607: Electronic Science Practical–III
(Modern Communication, Industrial Automation and Optoelectronics
Laboratory)
CONTENTS
Expt. Title of the Experiment Page
No. No.
B1 BPSK Generator 3
B2 Pulse Code Modulation and Demodulation 6
B3 Time Division Multiplexing 15
B4 Light Emitting Diodes 20
B5 Photodetectors 29
B6 Numerical Aperture of an Optical Fiber 39
B7 Fiber Optic Transmitter 47
B8 Introduction to PLC 51
B9 Ladder Programming – Latch, Timer, Counter 59
B10 Temperature Measurement and Control using PLC 75

2
 B1 BPSK Generator

Aim: To design, build, and test BPSK generator using opamp and analog multiplexer
Objectives:
1. To study the fundamentals of keying methods for data communication
2. To study opamp LF356 and CMOS Triple 2-channel analog multiplexer/demultiplexer
CD4053
3. To design BPSK generator using LF356 and CD4053
4. To build, and test BPSK generator circuit

Binary Phase Shift Keying:

The digital communication is the transmission of information in digital form from source to
destination. Basic elements of digital communication system are modulator, demodulator and
transmission medium.

BPSK modulation is the process by which the phase of the carrier is varied in accordance with
the modulating signal. The bpsk modulation technique is simplest and most robust of all PSK
modulation techniques, but it is unsuitable for high data-rate applications. In BPSK modulation,
the phase of the carrier signal is varied according to the modulating signal. In BPSK modulation
the output of logic 0 is phase shifted to the output for logic 1 in 1800. Figure 1 shows a
simplified block diagram of a BPSK modulator.

Data Input Multiplexer BPSK Signal

VmSin(ωt) -VmSin(ωt)

Carrier Phase Shift

Signal (1800)

Figure 1 Block diagram of a BPSK modulator

The coded signal enters to a multiplexer that commutes the phase of the carrier signal.
Depending on the logical condition of the digital input, the carrier is transferred to the output,
either in phase or at 180° outside of phase, with the reference carrier oscillator.
As seen from the Figure 1, a sinusoidal waveform is multiplied by the input bit stream. Each
time the bit stream changes sign (by crossing zero level), the phase of the PSK signal also
changes. The time domain illustration of a BPSK signal waveform is given in Figure 2.

3
 1 0 0 1 0 1

Phase changes (1800) with binary state change

Figure 2 BPSK modulator data input and output signals.

Circuit diagram:

Designing:

• Frequency of carrier signal is 10 kHz. The opamp LF356 is used for the inversion of the
carrier signal. It has high bandwidth than IC741.
• Opamp is used in inverting configuration with gain ‘-1’.
• Resistors, R1 and R2 selected are 10kΩ.
• The analog multiplexer CD4053 (CMOS Triple 2-channel analog multiplexer/
demultiplexer) is selected for selecting the carrier signals.

List of Components:
Sr. No. Component Specification
1 IC LF356, CD4053
2 Resistors R1, R2 (10kΩ)
3 Capacitors C0,1,2 (0.01F) Decoupling capacitors-not shown in diagram

4
Test and Measuring Instruments:
Sr. Name Model & Make Specification
1. Dual Power supply
2. Signal generator
3. Function generator
4. CRO

Procedure:
1. Design BPSK modulator circuit.
2. Apply ± 5 V supply to the modulator circuit.
3. Apply sinusoidal carrier signal Vin from signal generator to modulator as shown in circuit
diagram.
4. Set frequency, say 10 kHz, with maximum peak to peak voltage 2V.
5. Note the frequency and amplitude of the signal.
6. Apply modulating signal using TTL output of function generator as shown in circuit
diagram.
7. Set a frequency of data input less than 4 kHz and record it.
8. Observe the input signal, inverted output signal and BPSK output.
9. Comment on the output.

Observations:

1. Carrier frequency, fC = ____________ kHz

2. Peak to peak amplitude of Carrier input signal, Vm(p-p) = _________V
3. Data rate of modulating input, fm = _________kHz
4. Peak to peak amplitude of BPSK output signal, V0(p-p) = _________V

Results and Comments:

Frequently Asked Questions:

1. What are the types of keying methods used in digital data communications?
2. What is the use of PSK and BPSK?
3. List the various PSK techniques.
4. How is BPSK modulator works?
5. State the functions of each component used in the circuit.
6. Explain the role of multiplexer in the circuit.
7. List various applications of PSK methods.

5
 B2 Pulse Code Modulation and Demodulation

Aim: To study Pulse code modulation and demodulation

Objectives:
1. To understand the principle of Pulse Code Modulation and Demodulation.
2. To test the circuit with various test points
3. To study the effect on the variation of the amplitude of the modulating signal.
4. To study the effect on the variation of the frequency of the modulating signal.

Block Diagram:
Pulse Code Modulation (Transmitter)
Sine wave generator S/H Latch PISO
(Modulating Signal) Circuit Section

Pulse generator
(Carrier/Sample
Signal)

Ramp generator SIPO DAC LPF

Pulse Code Demodulation
Clock generator (Receiver)

Connection Diagram

Test and Measuring Instruments:

Sr Name Model & Make Specifications
1. PCM Trainer Kit
2. CRO/DSO

6
Introduction

Pulse-code modulation (PCM) is a method used to digitally represent sampled analog

signals. It is the standard form of digital audio in computers, Compact Discs, digital
telephony and other digital audio applications. In a PCM stream, the amplitude of the analog
signal is sampled regularly at uniform intervals, and each sample is quantized to the nearest
value within a range of digital steps. A PCM stream has two basic properties that determine
the stream's fidelity to the original analog signal: the sampling rate, which is the number of
times per second that samples are taken; and the bit depth, which determines the number of
possible digital values that can be used to represent each sample.

The PCM signal being in digital from transmission through low quality channels (with low
SNR is possible without any loss of quality. However, the bandwidth required for PCM signals
increases largely on the basis of Sampling frequency and number of clock pulses per sample.
The Digital Telephony, Digital Video etc. are a result of PCM techniques being used
extensively for better quality in combating noise in transmission.

PCM Modulator PCM Demodulator

1. Regulated Power Supply 1. Serial - Parallel Shift generator
2. AF Signal generator 2. D / A Converter
3. Sample and Hold Circuit 3. Passive Low Pass Filter
4. A / D Converter
5. Parallel – Serial Shift generator

Quantized Signal
ADC

PISO

Input S/H
signal BPF
Circuit
PCM
Output
Sample
PCM Transmitter Conversion Line Speed
Pulse Clock
Clock

Repeater Repeater
Serial PCM Code Serial PCM Code
Transmission Medium

Output Signal
DAC
SIPO
Line

Hold
LPF
Circuit

Quantized Signal
Line Speed Conversion PCM Receiver
Clock Clock

7
Test Procedure
1. Refer to the connection diagram and carry out the following connections.
2. Measure the sampling frequency and its amplitude using DSO.
3. Observe the ramp signal (line speed clock) and measure its amplitude and frequency.
4. Set the appropriate amplitude and the frequency (say 2V/1kHz) of the modulating signal
using DSO and note it.
5. Modulating signal is given to input of sample and hold (S/H) and sampling of this signal is
done by applying pulse signal.
6. Observe the S/H output waveform with modulating signal on DSO.
7. Connect output to the transmission latch section and another input is ramp signal.
8. Observe the output waveform that is quantized encoded output according to quantization
levels.
9. Observe the PISO (Parallel Input Serial Output)..
10. At receiver side, exactly opposite circuit is constructed, so that we can reconstruct the
original waveform (Message signal).
11. Output of PISO given to SIPO (Serial in Parallel Out) and forwarded to DAC (Digital to
Analog) section.
12. Observe the DAC and Hold output waveform with respect to input Modulating signal.
13. Connect output of DAC to Low Pass Filter generate original message signal and observe.

Observations:

Signal Amplitude Frequency

Sampling (carrier) signal
Ramp signal
Modulating input signal

Attach the following images of waveforms observed on DSO

Sr. CH#1 CH#2

Transmitter Section
1. Modulating Signal Input
2. Carrier Input (Pulse Generator output)
3. Ramp Generator Output
4. Modulating Signal Input S/H Output (Quantized Output)
5. Modulating Signal Input Comparator Output
6. Modulating Signal Input PISO Output
Receiver Section
7. Modulating Signal Input DAC Output (Quantized Output)
8. Modulating Signal Input Low Pass Output
9. DAC Output (Quantized Output) Low Pass Output

Results and Conclusions:

• Comments on the observations
References:

8
Observed Waveforms:

Sine Wave (Message signal):

Ramp Signal (Quantization levels):

9
 Digital Clock:

Monostable output:

10
 Sample and Hold output:

Comparator output
(compare each analog value with fixed quantized level in binary 1 and 0):

11
PARALLEL IN SERIAL OUT output (at transmitter side):

Digital to Analog convertor (at receiver side) output:

12
DAC output with fixed voltage potentiometer

13
Reconstructed output Message signal:

• Channel one: input sine wave

• Channel two: output sine wave

Frequently Asked Questions:

1. What are digital modulation techniques? Explain anyone.
2. What are the basic building blocks of Pulse Code Modulation? Explain each block.
3. What are the basic building blocks of Pulse Code demodulation? Explain each block.
4. Compare PCM with Delta modulation.
5. What are the advantages and disadvantages of digital modulation over analog and pulse
modulation?

14
 B3 Time Division Multiplexing

Aim: To design build and test multichannel Time Division Multiplexing (TDM) System
Objectives:
1. To understand the principles of different types of multiplexing techniques
2. To design and study of TDM for analog signals using analog multiplexer
3. To test the TDM for analog using analog multiplexer

Introduction:
In communication, the space can be divided into different frequency channels at the same time
for frequency division multiplexing or in different time slots for the same frequency for time
division multiplexing. Combination of these two is also used. Notice that each type has a guard
space to separate channels. Generally, the guard space (band) is used to reduce crosstalk and
therefore reduce circuit cost and complexity. The figure illustrates the different multiplexing
techniques.

TDM FDM
f

Designing:
In TDM, the time is divided into small time slots and each of these slots is occupied by a piece
of one of the signals to be sent. The multiplexer scans the input signal sequentially. Only one
signal occupies channel at one instant. It samples the signal sequentially. A potential divider
arrangement is used to obtain four different DC voltages as analog inputs, which are applied to the
inputs of CD4051. These signals are sampled at the rate determined by channel select control
circuit. Channel control circuit consists of a CMOS IC CD4060BC. It is 14 stage ripple binary
counters/oscillator. A oscillator is used to generate square wave and outputs of the counter are
used to generate channel control signals.
The output of multiplexer is series of dc outputs corresponding to 4-channels. A CMOS IC
CD4051, an 8-channel analog multiplexer, is used for this purpose. Out of 8 channels, lower
4-channels are used as a channel input.

• Analog Input Signals: A potential divider arrangement with five 1kΩ resistor is used to
obtain four different DC voltages as analog inputs, which are applied to the inputs of
CD4051. Refer Figure 1 and 2.

• Channel Select Control: A square wave oscillator is built using CD4060. Design
frequency of channel selection is fosc = 16 kHz. Let us select C = 100pF, R1 = 180/220kΩ
and R2 = 510kΩ. Since supply is 5V, lower value of resistor R1 is selected than the designed

15
 value. The outputs Q5 and Q6 are used as a channel control signals, which produces
frequencies 500Hz and 250Hz, correspondingly. Refer Formulae and Figure 3.

Circuit Diagrams:

Figure 1 Analog Inputs (AC/DC) Figure 2 Analog Multiplexer used as TDM

Design Formulae
𝟏
𝒇𝒐𝒔𝒄 = 𝒇𝒐𝒓 𝑽𝑫𝑫 ≥ 𝟏𝟎𝑽
𝟐. 𝟑𝑹𝟏 𝑪𝑿
𝒇𝒐𝒔𝒄
𝒇𝑨 =
𝟑𝟐
𝒇𝒐𝒔𝒄
𝒇𝑩 =
𝟔𝟒

Figure 3 Channel Select Signal generation

16
The timing waveforms of control signals and TDM output as described below can explain the
working of the circuit.

1 2 3 4 5 6 7 8
CH0 CH1 CH2 CH3 CH0 CH1 CH2 CH3

Q4

A (Q5)

B (Q6)

BA 00 01 10 11 00 01 10 11
4V

TDM output 3V
(Analog inputs) 2V
1V
0V
t
TDM output f0 f1 f2 f3 f0 f1 f2 f3
(Digital inputs)

Fig.4 Timing diagram of TDM system for Analog and Digital input Signals.

Components:
Sr. Component Control Inputs Analog Inputs MUX
1. ICs CD4060B ⤬ CD4051
2. Resistors R1 (180 kΩ), R2 (510 kΩ) R (1 kΩ → 5) ⤬
3. Capacitors CX (100pF) ⤬ ⤬

Test and Measuring Instruments:

Sr. Name Model & Make Specifications
1. Power supply
2. Digital Multi Meter
3. DSO/CRO

17
Test Procedure:
1. Build the circuit as shown in Figures 1 and 2. Connect the outputs of the potential divider
circuit to the inputs of the TDM circuit shown in Figure 2.
2. Apply the supply of ±5V to the circuit.
3. Measure the channel voltages and note in Table 1.
4. Connect Analog inputs (Fig. 1) to the channels (CH0 - CH3) of analog multiplexer CD4051
(Fig. 2). Measure the TDM output of IC4051 using DMM by varying the control signals
A, B manually. Note the readings in Table 2.
5. Connect the supply to Channel Select Signal generation circuit (Fig. 3). Observe the
oscillator frequency, and channel select outputs on DSO and Note in Table 3.
6. Connect the supply to Channel Select Signal generation circuit (Fig. 3). Connect channel
select signals to the select inputs of CD4051 and analog signals to channel inputs of
CD4051. Observe the TDM output on DSO and trace the output.

Observations:
Table 1. Input Signal Measurements: (Fig. 1)
Analog inputs V0 V1 V3 V4
Channel No. CH0 CH1 CH2 CH3
Expected Voltage 4V 3V 2V 1V
Observed Voltage

Table 2. TDM output (Fig. 2)

Control Signals
TDM Output Channel Selected
C B A
VOUT at TDM output
(Pin 9) (Pin 10) (Pin 11)
0 0 0
0 0 1
0 1 0
0 1 1

Table 3. Channel Select Control Signal: (Fig. 3)

Control signal Control signal
Oscillator Frequency Frequency Frequency
fosc
fA = fosc /32 (Pin 11) fB = fosc /64 (Pin 10)
Expected 16 kHz 500 Hz 250 Hz
Observed

Results: Comment on the results

18
References:
1. James T. Humphries and Leslie P. sheets, “Industrial Electronics.”
2. George Kennedy and Bernard Davis, “Electronic Communication Systems, 4th Edition,
TMH, pp.563-568.

Frequently Asked Questions:

1. Draw a block diagram of TDM and explain each block.
2. What is meant by analog multiplexer? Explain with the help of block diagram.
3. Which IC is used in this experiment for multiplexing? Draw block diagram and explain.
4. What is meant by transmission gate? Draw circuit diagram and symbol of it. Explain its
operating principle.
5. What is FDM? Discuss with the help of appropriate diagram/s.

19
 B4 Light Emitting Diodes

Aim: To determine characteristics of LED.

Objectives:
1. To understand the operating principle of LEDs
2. To determine the LED characteristics for red, yellow, and green LEDs.
3. To measure the LED voltages at 20 mA current for various LEDs.

Circuit Diagram:

Components:
Sr. Component Specifications
Colours: RED, ORANGE, YELLOW, GREEN, BLUE, VIOLET and
1. LEDs (5mm)
WHITE
2. Resistor R (330Ω) ¼watt

Test and Measuring Instruments:

Sr. Name Model & Make Specifications
1. Single Power supply
2. Digital Multi Meter
3. Ammeter

Test Procedure:
1. Connect the circuit as shown in circuit diagram. Use Red LED.
2. Vary the supply voltage and measure the current flowing through LED as well as voltage
across LED. Record the readings in Observation Table 1.
3. Repeat this procedure for Yellow and green LEDs. Record the readings in Observation
Table 1.
4. Plot a graph of LED current I vs LED Voltage V for Red, Yellow, and green LEDs on same
graph paper.
5. Measure the voltage across all LEDs at LED current 20mA and comment on observations.
6. Comment on the results.

20
Observations:
Observation Table I
LED Colour: Red LED Colour: Yellow LED Colour: Green
Sr. Voltage V Current I Voltage V Current I Voltage V Current I
No. (Volts) (mA) (Volts) (mA) (Volts) (mA)
1
2
3
4
.
.
.
.

Observation Table II
LED Current = 20mA
LED IR Red Orange Yellow Green Blue Violet White
Colour
Wavelength
940 630 610 590 525 470 *400 ̶
(nm)
LED
Voltage
* – Don’t see directly Violet (UV-LED-BLUE) harmful radiations.

Results: Comment on the results

References:
1. Light-Emitting Diodes E. Fred Schubert
2. LED Datasheet, TLUR6400, TLUR6401, Vishay Semiconductors www.vishay.com
3. https://en.wikipedia.org/wiki/Light-emitting_diode

21
Introduction:
An LED or a Light Emitting Diode is semiconductor device that emits light due to
Electroluminescence effect. An LED is basically a PN Junction Diode, which emits light when
forward biased.

Light Emitting Diodes are almost everywhere. You can find LEDs in Cars, Bikes, Street Lights,
Home Lighting, Office Lighting, Mobile Phones, Televisions and many more.
The reason for such wide range of implementation of LEDs is its advantages over traditional
incandescent bulbs and the recent compact fluorescent lamps (CFL). Few advantages of LEDs
over incandescent and CFL light sources are mentioned below:

• Low Power Consumption

• Small Size
• Fast Switching
• Physically Robust
• Long Lasting

Because of these advantages, LEDs have become quite popular among a large set of people.
Electronics Engineers, Electronic Hobbyists and Electronics Enthusiasts often work with LEDs
for various projects.

Basics of LED (Light Emitting Diode)

As mentioned in the introduction, an LED is a semiconductor light source. It consists of a PN
Junction Diode and when voltage is applied to the LED, electrons and holes recombine in the
PN Junction and release energy in the form of light (Photons).

The light emitted by an LED is usually monochromatic i.e. of single color and the color is
dependent on the energy band gap of the semiconductor.

Light Emitting Diodes can be

manufactured to emit all the
wavelengths of visible spectrum i.e.
from Red (620nm to 750nm) to blue
– violet (380nm to 490nm).

The electrical symbol of an LED is

similar to that of a PN Junction
Diode. The following image shows
a Red LED along with symbols of
PN Junction Diode and LED.

Characteristics of LED (Light Emitting Diode)

Before connecting an LED is a circuit and start using it, there are few characteristics of LED
that are worth knowing (actually, they are very important). If you refer to any of the datasheets
provided by the manufacturer, you can find a lot specification corresponding to electrical
characteristics, absolute maximum ratings, physical dimensions etc.
I’ll not bore you will all the characteristics but only with three important ones. They are the
Polarity, Forward Voltage and Forward Current.

22
Polarity of LED
Polarity is an indication of
symmetricity of an electronic
component. A Light Emitting Diode,
similar to a PN Junction Diode, is not
symmetric i.e. it allows current to
flow only in one direction

.
In an LED, the positive terminal is called as Anode and the negative terminal is called as
Cathode. For the LED to work properly, the Anode of the LED should be at a higher potential
than the Cathode as the current in LED flows from Anode to Cathode.

What happens if we connect the LED in reverse direction? Well, nothing happens as the LED
would not conduct. You can easily identify the Anode terminal of an LED as they usually have
longer leads.

Forward Current of LED

LEDs are very sensitive devices and the amount of current flowing through an LED is very
important. Also, the brightness of an LED depends on the amount of current drawn by the LED.

Every LED is rated with a maximum forward current that is safe to pass through it without
burning off the LED. For example, most commonly used 5mm LEDs have a current rating of
20mA to 30mA and the 8mm LEDs have a current rating of 150mA (refer to the datasheet for
exact values). How to we regulate the current flowing through an LED? In order to control the
current flowing through an LED, we make use of current limiting series resistors.

Forward Voltage of LED

Light Emitting Diodes are also rated for forward voltage i.e. the amount of voltage required for
the LED to conduct electricity. For example, all 5mm LEDs have a current rating of 20mA but
the forward voltage varies one LED to another.
Red LEDs have a maximum voltage rating of 2.2V, Blue LEDs have a maximum voltage rating
of 3.4V and White LEDs have a maximum voltage rating of 3.6V.

23
Simple LED Circuit
The following image shows the
circuit of a simple LED Circuit
consisting of a 5mm White LED
with a 5V power supply.

In order to regulate the current

and voltage, we have used a 180
Ω Resister rated for ¼ Watts of
Power Dissipation.

Types of LED
Through-hole LEDs
These are available in different shapes and
sizes and the most common ones being
3mm, 5mm and 8mm LEDs. These LEDs
are available in different colors like Red,
Blue, Yellow, Green, White, etc.

SMD LEDs (Surface Mount Light Emitting Diodes)

Surface Mount or SMD LEDs are a
special packages that can be easily
surface mount on a PCB. SMD LEDs are
usually differentiated based on their
physical dimensions. For example, the
most common SMD LEDs are 3528 and
5050.

24
Bi-color LEDs
The next type of LEDs are Bi-color
LEDs, as the name suggests, can
emit two colors. Bi-color LEDs
have three leads, usually two
anodes and a common cathode.
Depending on the configuration of
the leads, the color will be
activated.

RGB LED (Red – Blue – Green LED)

RGB LEDs are the most
favorite and most popular
LEDs among hobbyists and
designers. Even computer
builds are very popular for
implementing RGB LEDs
in Computer Cases,
Motherboards, RAMs, etc.

RGB LED contains 3 LEDs on a single chip and by a technique called PWM (Pulse Width
Modulation), we can control the output of the RGB LED to produce a wide range of colors.

High – Power LEDs

An LED with power rating
greater than or equal to 1 Watt is
called a High Power LED. This
is because, normal LEDs have a
power dissipation of few
millwatts.

High – Power LEDs are very

bright and are often used in
Flashlights, Automobile
Headlamps, Spotlights, etc.

Since the power dissipation of High – power LEDs is high, proper cooling and usage of heat
sinks is required. Also, the input power requirement for these LEDs will be usually very
high.

Unlike incandescent lamps, LEDs are not inherently white light sources. Instead, LEDs emit
nearly monochromatic light, making them highly efficient for colored light applications such

25
as traffic lights and exit signs. However, to be used as a general light source, white light is
needed. White light can be achieved with LEDs in three ways:

• Phosphor conversion, in which a phosphor is used on or near the LED to convert the
colored light to white light
• Color-mixed systems, in which light from multiple monochromatic LEDs (e.g., red,
green, and blue) is mixed, resulting in white light
• A hybrid method, which uses both phosphor-converted (PC) and monochromatic LEDs.

The ability of LED technology to produce high-quality white light with unprecedented energy
efficiency is the primary motivation for the intense level of research and development.

The wavelength of light, and therefore the color, depends on the type of semiconductor material
used to make the diode. That's because the energy band structure of semiconductors differs
between materials, so photons are emitted with differing frequencies. Categorization of
common LED semiconductors by frequency is given in the table.

While the wavelength of the light depends on the band gap of the semiconductor, the intensity
depends on the amount of power being pushed through the diode.
The unit for measuring luminous intensity is called the candela, although when you're talking
about the intensity of a single LED you're usually in the millicandela range. The interesting
thing about this unit is that it isn't really a measure of the amount of light energy, but an actual
measure of "brightness". This is achieved by taking the power emitted in a particular direction
and weighting that number by the luminosity function of the light. The human eye is more
sensitive to some wavelengths of light than others, and the luminosity function is a standardized
model that accounts for that sensitivity.

The luminous intensity of LEDs can range from the tens to the tens-of-thousands of
millicandela. The power light on your TV is probably about 100 mcd, whereas a good flashlight
might be 20,000 mcd. Looking straight into anything brighter than a few thousand millicandela
can be painful.

26
27
28
 B5 Photodetectors

Aim: To determine characteristics of various photodetectors.

Objectives:
1. To measure the LDR resistance for lights of different wavelength.
2. To determine the I-V characteristics of photodiode in photoconductive mode.
3. To determine the I-V characteristics of photodiode in photovoltaic mode.

Circuit Diagrams:
Diagram 1: LDR resistance for different wavelengths (colors)

Diagram 2: Photodiode in photoconductive mode (Quadrant III of I-V Characteristics)

Diagram 3: Photodiode in photovoltaic mode (Quadrant IV of I-V Characteristics)

29
Components:
Sr. Component Specifications
1. LEDs (5mm) Colours: RED, ORANGE, YELLOW, GREEN, BLUE, VIOLET
2. LDR
3. Photodiode BPW34
4. Resistor 330Ω, 10kΩ, 25kΩ

Test and Measuring Instruments:

Sr. Name Model & Make Specifications
1. Single Power supply
2. Digital Multi Meter
3. Ammeter
4. Lux meter
5. Incandescent bulb 40/60Watt

Test Procedure:
LDR
1. Connect the circuit as shown in Circuit Diagram 1. Use Red LED.
2. Set current 20 mA for RED LED and expose LDR to LED light.
3. Measure the LDR resistance and note the reading in Observation Table I.
4. Repeat this procedure to all different color LEDs.
5. Plot a graph of LDR resistance, R vs wavelength, 

Photodiode (as a photodetector – photoconductive mode)

6. Connect the circuit as shown in Circuit Diagram 2. Use photodiode BPW34.
7. Set the intensity of light = _____ lux. Vary the voltage from 0V to 10V in step of 2V. Note
the current reading in Observation Table II.
8. Repeat this procedure for different light intensity.
9. Plot a graph of photocurrent, I vs photodiode voltage, V.
10. Comment on the results.

Photodiode (photovoltaic mode)

11. Connect the circuit as shown in Circuit Diagram 3. Use photodiode BPW34.
12. Set the intensity of light = _____ lux.
13. Vary the load resistor RL in the range between 0 to 1MΩ. Note the photocurrent I and
photodiode voltage V in Observation Table III. .
14. Repeat this procedure for different light intensity.
15. Plot a graph of photocurrent, I vs photodiode voltage, V.
16. Comment on the results.

30
Observations:
Observation Table I: LED Current = 20mA
LED Color IR Red Orange Yellow Green Blue Violet
Wavelength
940 630 610 590 525 470 *400
(nm)
LDR
Resistance, R
* – (UV-LED-BLUE) Don’t see directly.
Observation Table II: Photodiode (as photodetector – photoconductive mode) – Quadrant-III
Sr. Intensity of light = _____ lux. Intensity of light = _____ lux.
Voltage V (V) Current I (mA) Voltage V (V) Current I (mA)
1 0 0
2 -2 -2
3 -4 -4
4 -6 -6
5 -8 -8
6 -10 -10

Observation Table III: Photodiode (photovoltaic mode) – Quadrant-IV

Sr. Intensity of light = _____ lux. Intensity of light = _____ lux.
Voltage V (V) Current I (mA) Voltage V (V) Current I (mA)
1
2
3
4
.
.

Results: Comment on the observations.

References:
1. APPLICATION NOTE #1 Light - Some Physical Basics,
https://resources.perkinelmer.com/corporate/cmsresources/images/44-
3447app_photodiodes.pdf
2. BPW34 datasheet, https://www.mouser.in/datasheet/2/427/VISH_S_A0012000273_1-
2572197.pdf
3. https://www.univie.ac.at/photovoltaik/praktikum/ws2017/silicon_photodiodes.PDF

31
Introduction:
Light dependent resistor (LDR)

As the name suggests an LDR or Light Dependent Resistor is a kind of resistor, that exhibit a
wide range of resistance values depending on the intensity of light incident on its surface. The
variation in the resistance range can be anywhere from few hundred ohms to many megaohms.

They are also known as Photoresistors. The resistance value in an LDR is inversely
proportional to the intensity of the light falling on it. Meaning when the light is less, the
resistance is more and vice versa.

• LDRs are light dependent resistors.

• Resistance decreases with increasing light levels.
• Typically > 1 MΩ when dark and < 1 kΩ in high light levels.
• Response time of 2 – 50 ms. (Much slower than phototransistors)
• They have a “light history”. Characteristics change a little as they acclimatize after long
periods in darkness.
• LDRs are more sensitive to certain wavelengths (colours). The CdS types are most
sensitive to green.

MOST IMPORTANT PROPERTIES

• Dark resistance value (usually hundreds or more kΩ)

• Resistance value at illumination level of 10 lux, usually expressed as minimum, typical,
and maximum value (usually in the kΩ range).
• Resistance sensitivity (resistance change as function of illumination level change) in linear
approximation expressed as γ (values about 0.8 to 0.95).

𝑅𝑎
log
𝑅𝑏
γ=
𝑏
log 𝑎

Where Ra and Rb are the resistance values at illumination levels a and b respectively.

LDR resistance versus illumination

Notice:
The response time to large changes in illumination level can be several seconds.

32
LDR Internal Construction

The following figure shows the internal dissected view of an LDR device wherein we can see
the photoconductive substance applied within the zig zag or coiled pattern, embedded over a
ceramic insulating base, and with the end points terminated as leads of the device. The pattern
ensures maximum contact and interaction between the crystalline photoconductive material
and the electrodes separating them.

The photoconductive material generally consists of cadmium sulfide (CdS) or cadmium

selenide (CdSe). The type and thickness of the material and width of its deposited layer specify
the range of the LDR resistance value and the amount of watts it can handle. The two leads of
the device is embedded within an an opaque non-conductive base with an insulated transparent
coating over the photoconductive layer.

The diameter of photocells or LDRs may range from 1/8 inch (3 mm) to above one inch (25
mm). Commonly these are available with diameters of 3/8 inch (10 mm).

Figure 1. A Silonex NSL- Figure 2. Schematic

19M51 LDR top view. Symbols of Photocell/ LDR Figure 3. Typical LDR
packaging.

33
Comparing LDR Characteristics with Human Eye

Figure Comparison between characteristics curves of photosensitive devices and our eye.

The graph above provides the comparison between the characteristics of photosensitive devices
and our eye. The graph shows the plotting of Relative spectral response against wavelength
from 300 to 1200 nanometers (nm).

The human eye characteristic waveform indicated by the dotted bell-shaped curve reveals the
fact that our eye has enhanced sensitiveness to a relatively narrower band of the
electromagnetic spectrum, approximately between 400 and 750 nm.

The peak of the curve has a maximum value in the green light spectrum within the range of
550 nm. This stretches down into the violet spectrum having a range between 400 to 450 nm
on one side. On the other side, this extends into the dark red-light region having a range
between 700 to 780 nm.

The figure above also reveals exactly why cadmium sulfide (CdS) photocells tend to be the
favorites in light-controlled circuit application: the spectral response curve peaks for Cds is
near 600 nm, and this specification is quite identical to the range of human eye. In fact, the
cadmium selenide (CdSe) response curve peaks may even extend beyond 720 nm.

34
Figure 3. Graph of resistance versus light level.

Lighting condition From (lux) To (lux) Mean value (lux)

Pitch Black 0 10 5
Very Dark 11 50 30
Dark Indoors 51 200 125
Dim Indoors 201 400 300
Normal Indoors 401 1000 700
Bright Indoors 1001 5000 3000
Dim Outdoors 5001 10,000 7500
Cloudy Outdoors 10,001 30,000 20,000
Direct Sunlight 30,001 100,000 65,000

Spectral response LDR Sunram CdS spectral response with visible light spectrum
superimposed.

35
The common CdS (cadmium sulfide) LDRs have peak spectral response at about 550 nm,
which is the green region of the visible spectrum. Note that if illuminating the LDR with an
LED that a red LED might give only about 30% of the response of a green LED on the same
current.

Applications:

For the digital ON-OFF applications such as flame detectors, LDRs with steep slopes to their
resistance versus light intensity curves are appropriate. For analog or measurement types of
applications such as exposure controls for cameras, LDRs with shallow slopes may be better
suited.

The slow response times of LDRs makes them unsuitable for data transmission, for example,
but can be an advantage in other circuits such as flame detectors or audio effects where the
slow response smooths out the signal being monitored or controlled.

The lux is the SI unit for illuminance generated by a luminous flux of 1 lumen evenly spread
over a surface of 1 square meter. The modern photocells or LDRs are adequately rated for
power and voltage, at par with normal fixed type resistors.

The power dissipation capacity for a standard LDR could be around 50 and 500 milliwatts,
which may depend on the quality of the material used for the detector.

Perhaps the only thing not so good about LDRs or Photoresistors is their slow response
specification to light changes. Photocells built with Cadmium-selenide typically exhibit have
shorter time constants than cadmium-sulfide photocells (approximately 10 milliseconds in
contrast to 100 milliseconds). These devices having lower resistances, increased sensitivity,
and elevated temperature resistance coefficient.

The main applications in which Photocells normally implemented are in photographic exposure
meters, light and dark activated switches for controlling streetlights, and burglar alarms. In
some light activated alarms applications the system is triggered through a light beam
interruption.

36
Photodiode:
The photodiode is a type of photodetector capable of converting light to a small current, which
is proportional to the level of illumination. The sensitivity of photodiodes depends on the
wavelength of incident light.
Note that photodiode current is non-zero with incident light, even when the photodiode voltage
is zero.
Photo-Diode is a silicon or germanium PN junction diode, which is photosensitive in reverse
bias condition. i.e. The reverse current in a photodiode depends on the intensity of light falling
on it or exposure of light. The application of this diode is in its reverse biased condition. The
voltage-current equation for photodiode is given by following equation.

Here,
I0: reverse saturation current,
V: applied potential to diode,
VT: voltage equivalent to temperature = KT/e,
η:constant (=1 for Ge and 2 for Si),
IP: photocurrent.
When, V is negative then hence equation (1) becomes as,
IR = −I0 − IP (2)
Equation (2) indicates that in reverse biased photo-diode the total current is sum of reverse
saturation current and photocurrent. In absence of light, the photocurrent becomes zero and the
total current flowing through diode is equal to reverse saturation current. This current is known
as dark current.

Figure: Photodiode I-V curves.

37
when operated in photovoltaic mode Vp = 0, such that the photogenerated current is the only
current that flows.

Photodiode I-V curves showing different operating modes..

Relative Spectral Sensitivity vs. Wavelength of BPW34.

38
 B6 Numerical Aperture of an Optical Fiber

Aim: To determine the numerical aperture (NA) of the optical fiber.

Objectives:
1. To study the numerical aperture (NA) of the optical fiber.
2. To determine the numerical aperture (NA) of the optical fiber.

Experimental Setup:

Electrical Connections of LED

List of Components:
Sr. Components Specifications

Transmitter SFH756V: Plastic Fiber Optic Transmitter Diode Plastic

1
diode Connector Housing (λpeak 660nm)
2 Resistors R = 100 
3 Optical fiber Plastic type

39
List of Test and Measuring Instruments:
Sr. Instrument Model & Make Specifications
1 Single Power Supply
2 Current meter
3 DMM

Procedure:
1. Mount LED source and optical fiber.
2. Provide the electrical connections to LED source.
3. Insert optical fiber into light source coupler at one end and keep the screen at some fixed
distance at another end.
4. Set the LED current between 20 mA and 40 mA and measure the LED Voltage.
5. Set the distance between the optical fiber and screen say, Z = 0.5 cm.
6. Find the diameter of the spot of the light observed on the screen and record it as ‘d’.
7. Repeat the above procedure for 5 to 6 different distances.
8. Calculate the numerical aperture for each reading.

Observations:
1.
2. Length of optical fiber = -------- meter
3. Wavelength of emitted light = -------- nm
4. Current supplied to LED, I = --------- mA
5. LED Voltage, V = --------- V
6. Electrical power supplied to LED, P = VI = -------- mW

Sr. Distance Diameter 𝒅 𝒅 𝑵𝑨

No. between fiber of the 𝐭𝐚𝐧−𝟏 [ ] 𝒅
𝟐𝒁 𝟐𝒁
and screen, Z spot d = 𝐬𝐢𝐧 (𝐭𝐚𝐧−𝟏 [ ])
𝟐𝒁
(cm) (cm)
1 0.5
2 1
3 1.5
4 2
5 2.5
6 3

Result:
Average Numerical Aperture (NA) = …………

Conclusion:

40
 Optical fiber basics
Refraction of light

As a light ray passes from one transparent medium to another, it changes direction; this
phenomenon is called refraction of light. How much that light ray changes its direction
depends on the refractive index of the mediums.

Refractive Index

Refractive index is the speed of light in a vacuum (abbreviated c, c=299,792.458km/second)

divided by the speed of light in a material (abbreviated v). Refractive index measures how
much a material refracts light. Refractive index of a material, abbreviated as n, is defined as

n=c/v

Snell’s Law

In 1621, a Dutch physicist named Willebrord Snell derived the relationship between the
different angles of light as it passes from one transparent medium to another. When light
passes from one transparent material to another, it bends according to Snell's law which is
defined as:

n sin(θ ) = n sin(θ )
1 1 2 2

where:
n is the refractive index of the medium the light is leaving
1

θ is the incident angle between the light beam and the normal (normal is 90° to the interface
1

between two materials)

n is the refractive index of the material the light is entering
2

θ is the refractive angle between the light ray and the normal
2

41
Note:

For the case of θ = 0° (i.e., a ray perpendicular to the interface) the solution is θ = 0° regardless
1 2

of the values of n and n . That means a ray entering a medium perpendicular to the surface is
1 2

never bent.

The above is also valid for light going from a dense (higher n) to a less dense (lower n) material;
the symmetry of Snell's law shows that the same ray paths are applicable in opposite direction.

Total Internal Reflection

When a light ray crosses an interface into a medium with a higher refractive index, it bends
towards the normal. Conversely, light traveling cross an interface from a higher refractive index
medium to a lower refractive index medium will bend away from the normal.

This has an interesting implication: at some angle, known as the critical angle θ , light c

traveling from a higher refractive index medium to a lower refractive index medium will be
refracted at 90°; in other words, refracted along the interface.

If the light hits the interface at any angle larger than this critical angle, it will not pass through
to the second medium at all. Instead, all of it will be reflected back into the first medium, a
process known as total internal reflection.

The critical angle can be calculated from Snell's law, putting in an angle of 90° for the angle of
the refracted ray θ . This gives θ :
2 1

Since

θ = 90°
2

So

sin(θ ) = 1
2

Then
θ = θ = arcsin(n /n )
c 1 2 1

42
For example, with light trying to emerge from glass with n =1.5 into air (n =1), the critical
1 2

angle θ is arcsin(1/1.5), or 41.8°.

c

For any angle of incidence larger than the critical angle, Snell's law will not be able to be solved
for the angle of refraction, because it will show that the refracted angle has a sine larger than
1, which is not possible. In that case all the light is totally reflected off the interface, obeying
the law of reflection.

HOW OPTICAL FIBER WORKS

Optical fibers are based entirely on the principle of total internal reflection. This is explained
in the following picture.

Optical fiber is a long, thin strand of very pure glass about the diameter of a human hair. Optical
fibers are arranged in bundles called optical cables and used to transmit light signals over long
distances.

The Structure of an Optical Fiber

Typical optical fibers are composed of core, cladding and buffer coating.

The core is the inner part of the fiber, which guides light. The cladding surrounds the core
completely. The refractive index of the core is higher than that of the cladding, so light in the
core that strikes the boundary with the cladding at an angle shallower than critical angle will
be reflected back into the core by total internal reflection.

For the most common optical glass fiber types, which includes 1550nm single mode fibers and
850nm or 1300nm multimode fibers, the core diameter ranges from 8 ~ 62.5 µm. The most
common cladding diameter is 125 µm. The material of buffer coating usually is soft or hard
plastic such as acrylic, nylon and with diameter ranges from 250 µm to 900 µm. Buffer coating
provides mechanical protection and bending flexibility for the fiber.

43
 OPTICAL FIBER MODE
What is Fiber Mode?

An optical fiber guides light waves in distinct patterns called modes. Mode describes the
distribution of light energy across the fiber. The precise patterns depend on the wavelength of
light transmitted and on the variation in refractive index that shapes the core. In essence, the
variations in refractive index create boundary conditions that shape how light waves travel
through the fiber, like the walls of a tunnel affect how sounds echo inside.

We can take a look at large-core step-index fibers. Light rays enter the fiber at a range of angles,
and rays at different angles can all stably travel down the length of the fiber as long as they hit
the core-cladding interface at an angle larger than critical angle. These rays are different modes.

Fibers that carry more than one mode at a specific light wavelength are called multimode fibers.
Some fibers have very small diameter core that they can carry only one mode which travels as
a straight line at the center of the core. These fibers are single mode fibers. This is illustrated
in the following picture.

44
Optical Fiber Index Profile

Index profile is the refractive index distribution across the core and the cladding of a fiber.
Some optical fiber has a step index profile, in which the core has one uniformly distributed
index and the cladding has a lower uniformly distributed index. Other optical fiber has a graded
index profile, in which refractive index varies gradually as a function of radial distance from
the fiber center. Graded-index profiles include power-law index profiles and parabolic index
profiles. The following figure shows some common types of index profiles for single mode and
multimode fibers.

Optical Fiber’s Numerical Aperture (NA)

Multimode optical fiber will only propagate light that enters the fiber within a certain cone,
known as the acceptance cone of the fiber. The half-angle of this cone is called the acceptance
angle, θmax. For step-index multimode fiber, the acceptance angle is determined only by the
indices of refraction:

Where
n is the refractive index of the medium light is traveling before entering the fiber
n is the refractive index of the fiber core
f

n is the refractive index of the cladding

c

How to Calculate Number of Modes in a Fiber?

Modes are sometimes characterized by numbers. Single mode fibers carry only the lowest-
order mode, assigned the number 0. Multimode fibers also carry higher-order modes. The
number of modes that can propagate in a fiber depends on the fiber’s numerical aperture (or

45
acceptance angle) as well as on its core diameter and the wavelength of the light. For a step-
index multimode fiber, the number of such modes, N , is approximated by
m

Where
D is the core diameter
λ is the operating wavelength
NA is the numerical aperture (or acceptance angle)

Note: this formula is only an approximation and does not work for fibers carrying only a few
modes.

What is N1 and N2 in numerical aperture?

To calculate the Critical Angle, first determine the N.A. (Numerical Aperture). The N.A. of
any glass combination may be calculated as follows: (where N1= the index of refraction of
the core glass), and N2=(the index of refraction of the cladding glass

What is the NA of a fiber?

The Numerical Aperture (NA) of a fiber is defined as the sine of the largest angle an
incident ray can have for total internal reflectance in the core. Rays launched outside the
angle specified by a fiber's NA will excite radiation modes of the fiber. A higher core index,
with respect to the cladding, means larger NA.

Why is na important for optical fiber?

The numerical aperture is a measure of the acceptance angle of the fiber. It is very important
because it determines how strongly a fiber guides light, and so how resistant it is to bend-
induced losses.

What is N1 and N2 in numerical aperture?

To calculate the Critical Angle, first determine the N.A. (Numerical Aperture). The N.A. of
any glass combination may be calculated as follows: (where N1= the index of refraction of
the core glass), and N2=(the index of refraction of the cladding glass

46
 B7 Fiber Optic Transmitter

Aim: To design, build and test a fiber optic transmitter.

Objectives:
1. To design a FSK modulator for Mark and Space frequencies.
2. To interface the FSK output to LED source with Optic fiber coupler
3. To couple the transmitter output to receiver through optical fiber cable (OFC).

Circuit Diagram:

Introduction:
The simplest FSK is binary FSK (BFSK). BFSK uses a pair of discrete frequencies to transmit
binary (0s and 1 s) information. With this scheme, the 1 is called the mark frequency and the 0
is called the space frequency.
Frequency Shift Keying FSK is the digital modulation technique in which the frequency of the
carrier signal varies according to the digital signal changes. FSK is a scheme of frequency
modulation. The output of a FSK modulated wave is high in frequency for a binary High input
and is low in frequency for a binary Low input. The binary 1s and 0s are called Mark and Space
frequencies. Representation of FSK modulated waveform with its input shown in Figure 1.

The FSK modulator block diagram comprises of two oscillators with a clock and the input
binary sequence. Block diagram is shown in Figure 2. The two oscillators, producing a higher
and a lower frequency signals, are connected to a switch along with an internal clock. To avoid
the abrupt phase discontinuities of the output waveform during the transmission of the message,
a clock is applied to both the oscillators, internally. The binary input sequence is applied to the
transmitter so as to choose the frequencies according to the binary input.

47
Figure 1. Representation of FSK modulated waveform.

Figure 2. FSK modulator block diagram.

Designing:
The basic element of FSK modulator is an astable multivibrator constructed using IC555 timer.
The frequency of oscillation is given by
1.44
𝑓=
(𝑅𝐴 + 2𝑅𝐵 )𝐶
Design an astable multivibrator for f1 =1070 Hz and f2 =1270 Hz and obtain the values for
resistors assuming C = 0.01 F.

Choose BC557/558 as a switch to select appropriate resistor combination for obtaining proper
frequencies in FSK. Select the base resistors of transistor (T1) 10 k each.

48
Modulator output cannot provide high current to the transmitter LED for long duration. Hence,
transistor BC547/548 is used. Base resistor having value 1k and collector resistor having
value 100 selected to drive transmitter LED. LED SFH756V and IRED SFH450V are
selected for transmission because it comes with plastic connector housing.

Light output is coupled to receiver via optical fiber cable (OFC). Receiver is phototransistor.
Phototransistor is connected as shown in diagram the output is taken across resistor R 0.
Phototransistor selected is SFH350V because it comes with plastic connector housing.

Test Procedure:
1. Design a FSK modulator for mark and space frequencies f1 =1070 Hz and f2 =1270 Hz.
2. Prepare a list of components required for the circuit.
3. Build the FSK modulator and transmitter circuit. Use
4. Select the necessary test and measuring instruments and connect them.
5. Provide +5 V power supply to the circuit.
6. Give the digital input 'logic-1' i,e. +5V to FSK modulator circuit.
7. Observe the output waveform on CRO/DSO and measure the amplitude and frequency of
the wave.
8. Similarly, measure the amplitude and frequency of the wave for 'Logic-0' input.
9. Connect OFC to transmitter LED SFH756V and receiver SFH350V as shown in diagram.
10. Take photograph of a) IC55 output, b) collector of transistor T2 c) emitter of transistor T3
11. Repeat (8) and (8) for transmitter IRED SFH450V and receiver SFH350V as shown in
diagram.
12. Comment on the received waveform for both cases.
13. Connect the digital input of frequency less than 150 Hz. Observe the digital input and
output of IC555. Comment on the waveforms.

List of Components:
Sr. Components Specifications
1 IC555
SFH350V: Plastic Fiber Optic Phototransistor Detector Plastic
2 Detector Connector Housing (λSmax 850nm))
SFH450V: Plastic Fiber Optic Infrared Transmitter Diode
Plastic Connector Housing (λpeak 950 nm)
3 Transmitter diode
SFH756V: Plastic Fiber Optic Transmitter Diode Plastic
Connector Housing (λpeak 660nm)
Transistors:
4 BC547/548
BC547/558
RA = 51 k, RA1 = 39 k, RB = 47 k, R0, R1, R2 = 10 k ,
5 Resistors
R3 = 1 k, R4 = 100 
6 Capacitors C, C1 = 0.01 F

49
List of Test and Measuring Instruments:
Sr. Instrument Model & Make Specifications
1 Single Power Supply
2 Function Generator
3 CRO/DSO

Observations:
Digital input Frequency Frequency
Logic Voltage type Expected Measured
High / 1 5V Mark 1070 Hz
Low / 0 0V Space 1270 Hz

Attach waveforms of
Transmitter CH1 CH2 Transmitter CH1 CH2
SFH756V Pin-3 of 555 Collector of SFH450V Pin-3 of 555 Collector of
T2 T2
Pin-3 of 555 Emitter of Pin-3 of 555 Emitter of
T3 T3

Observe waveforms of
CH1 CH2
Digital Input (TTL < 150Hz) Pin-3 of IC555

Conclusions:

50
 B8 Introduction to PLC

Aim: To implement basic logic gates on PLC using ladder programming

Objectives:
1. To familiarize the student with Programmable Logic Controllers (PLC) as hardware and the
software used
2. To get acquainted with programming PLC using ladder logic diagrams.
3. To implement the basic logic gates using ladder diagram

Introduction:
The programmable logic controller (PLC) as a control equipment has been widely in use in
various industries. Since last many years, initially PLCs performed only relay equivalent
functions. In the past few years, PLC's have gone through a rather dramatic revolution in terms
of capabilities and areas of applications. Now PLC's have gone into areas where process
computers were the only solution.

Basic functions of PLC:

The PLC is used for control applications as in special purpose machines for milling, drilling,
packing machines etc. and for plant process control. In short, PLC can be used for any
automation application.

To implement the above-mentioned applications, PLC senses inputs from the field (using its
input cards), for example from a level sensor, a proximity switch, pushbutton etc. Then
depending on the logic written in the PLC's logic memory, certain decisions are taken by the
PLC. Depending on the decisions taken, certain outputs, like contactors (for driving motors),
solenoids (for linear movement), lamps (for indications), valves (for flow control) c are driven
by the PLC.

How to use a PLC for a simple application?

To make use of PLC's, the user must first define the number of parameters that he/she wishes
to detect from the machine, these constitute the inputs of the PLC. For a large process the
number of inputs may go into hundred's. These inputs are to be continuously scanned by the
PLC and depending on the status of these inputs the PLC is to perform certain tasks. To perform
these tasks the PLC must drive some outputs. So user must also define the number of outputs
to be driven. Again for a large process, the outputs may also go into hundred's.

Now once the inputs and outputs are defined the user must specify in very clear and logical
terms, the basic functioning of the machine in both auto mode and manual mode. For this, a
flowchart is to be derived by writing a set of if ... then statements. This constitutes PLC logic
equations popularly called as ladder equations / diagram.

PLC Scan Cycle

The PLC, when it is on, it is permanent in PLC scan cycle. As shown in figure the PLC scans
the inputs first (input scan), then solves the logic (logic scan) and then drives the outputs (output
scan). This process constitutes a single scan of a PLC. When switched on, continuously it is in
PLC scan cycle. The process control logic should be written by taking into account the PLC

51
scan cycle that is normal linear programming methodology will not be useful. The PLC is
online when all three scans (INPUT, LOGIC, OUTPUT) are ON. The PLC is in offline where
INPUT and logic scan are on but OUTPUT scan is off. The above description is illustrated
pictorially in the block diagram of PLC and also illustrated is the scan cycle of PLC.

Traditionally PLC's have been programmed in a language called as ladder language. The ladder
diagram programming has been derived from contactor/relay diagram used in traditional
electrical panels which till late have been used for control applications and now are replaced
by PLC's for their advantage. The close resemblance between ladder diagram and contactor
diagram helps even a shop floor person to familiar with the programming of a PLC.

For users in electronic/electrical/computer engineering, the ladder diagram is a pictorial

representation of Boolean logic, with PLC- inputs, outputs, flags, timers, counters, registers as
parameters of Boolean equations. There are window-based ladder programming tools
available, which help user to make large program with good documentation tools similar to
what is available for higher-level languages in any computer.

A ladder program consists of set of individual ladders. A ladder consists of a number of contacts
and a single coil.
The contacts can be either Normally Open (NO) or Normally Closed (NC).

• ‘NO’ contact pictorially represented as

For a 'NO' contact, the contact is true if the parameter for that contact is ON or SET.

• ‘NC’ contact pictorially represented as

For a 'NC' contact, the contact is true if the parameter for that contact is OFF or RESET.

The coil is the final output of a ladder. A coil is on only if the ladder contacts are true. For
example, in the ladder below the coil of ladder is on if either INPUT 1 is ON or INPUT 2 is
ON.

Examples of OR logic using ladder diagram

1. The coil is on only if INPUT 1 is on and INPUT 2 is off.

2. Example of AND logic using ladder diagram

52
• More complex ladder according to the logic are also possible.
• The parameter for any contact in a ladder are to be decided by the user.
• In addition, whether they are ‘NO' or 'NC' type is also to be decided by the user. This
constitutes the programming of ladder.

Definition of PLC by NEMA Standards:

A digitally operating electronic apparatus which uses a programmable memory for the internal
storage of instructions for implementing the specific functions, such as logic sequencing,
timing, counting and arithmetic to control digital or analog input/output modules, various types
of machines or processes. In general, PLC's are made of at least the following functional blocks.

1. Central Processing Unit and Memory: Central processing unit of the programmable
controller directs the controller to perform the functions as stored by user in its memory.
2. Inputs/Outputs: Input and output units permit the processor to be connected to process
equipment of machinery.
3. Power Supply: This unit supplies the required power lines (+5V, ±12V, +24V, 0V etc.) to
all the electronic components.
Advantages of PLC's over other type of control systems
1) Ease of Programming: The ability to relate at the plant level with non-computer person
in a language the plant operator is familiar with viz. ladder diagram.

2) Ease of Maintenance: The ability to monitor the changing process on a hand held terminal
is of immense value, in addition to build in diagnostic features, help to identify fault at
module level, such as fuse blown indication etc. In addition, replacement of modules is
very straightforward and easy.
3) Designed for Industrial Environment: This aspect makes PLC's rugged and no special
setup like air conditioning required
4) Quick Installation: This ability to minimize wire runs, portability of equipment etc.
5) Flexibility: The PLC is very flexible that is if the plant engineer, to accommodate these
changes, can reprogram decisions or conditions in the process change the PLC in the plant.
If additional inputs or outputs needed, they can be added to the system if PLC is rack based.

Software aspects of PLC's

In general, PLC's are programmed in ladder language. This language is much closed to an
electrical diagram, and this makes it familiar to a person even at the shop floor level.

53
PLC Block Diagram:

Central Processing Unit

Input Module

Input Module

Keyboard and
Display

PLC Scan Cycle:

Input Scan Logic Scan Output Scan

BENIX PLC TRAINER SYSTEM S-1200

Hardware Configuration
SIMATIC S7 - 1200 PLC SYSTEM

SIMATIC S7 -. 1200 PLC SYSTEM

CPU 1214C

DC/DC/DC
(6ES7 214-1AG40-0XBO)

Processor : Siemens make SIMATIC S7 - 1200 PLC

Power Supply : +24V DC @ 5Amp

54
System Specifications
Slot Module Description

SIMATIC S7 - 1200 PLC with PROFINET (Ethernet)

communication adapter (IP Address : 192.108.0.1)
• 14 Digital Inputs : Address 10.0 To lo.7 & t1.0 To t1.5
0
SIMATIC S7 -. 1200 • 10 Digital outputs : Address e0.0 To e0.7 & e1.0 To e1.1
CPU 1214C • 2- Channel Analog Input Module ( 0 - 10 V Input)
Address : IW64 and IW66
• 1- Channel Analog Output Module( 0 - 10 V Input)
Address : QW80

Panel Description:
Power Switch Power On Switch provided in mains circuit and mounted on the panel.
Power Indicator Power on indicator provided on panel
Digital Input Fourteen ST5 Input terminals DI0.0 to DI0.7and DI1.0TO DI1.5
Digital Output Ten ST5 Output terminals DQO to DQ0.7 and DQ1.0 TO DQ1.1
Analog Input 2 Channel Analog Input (CHO and CH1 -Voltage Input) terminal
provided on panel.)
Analog Output 1 Channel Analog Output (CHO - Voltage Output /Current Output)
terminal provided on panel
Input Devices Four NO type pushbutton charged with 24V DC provided on panel
Five SPST Toggle switches charged with 24V DC provided on panel
Output devices Eight 24V operated Pilot Lamps provided on panel
One 24V DC operated Hooter with Lamp provided on panel
Voltage Source One 0 - 10V source provided on panel as an analog voltage input
Digital Voltmeter Two 0 - 20V digital voltmeters are provided on panel

Analog Input and Output Connector Details: PLC S7 - 12OO

Sr. Analog Inputs and Outputs PLC Address 15 PIN
D Connector (M)
1. AI-CH0 (0 TO 10V) IW64 1
2. AI-CH1 (0 TO 10V) IW66 2
3. AI-COMMON Com 3
4. AQ-CH0 (0 TO 10V) QW80 4
5. AQ-COMMON Com 5

55
Digital Input and Output connectors Details: PLC S7 - 12OO
Digital Inputs and Power Digital Outputs and Power
Sr. Digital PLC 15 PIN Digital PLC 15 PIN
Input Address D Connector Input Address D Connector
(M) (F)
1. DI I0.0 1 DO Q0.0 1
2. DI I0. 2 DO Q0.1 2
3. DI I0.2 3 DO Q0.2 3
4. DI I0.3 4 DO Q0.3 4
5. DI I0.4 5 DO Q0.4 5
6. DI I0.5 6 DO Q0.5 6
7. DI I0.6 7 DO Q0.6 7
8. DI I0.7 8 DO Q0.7 8
9. DI I1.0 9 DO Q1.0 9
10. DI I1.1 10 DO Q1.1 10
11. DI I1.2 11 +24V L 14
12. DI I1.3 12 COM M 15
13. DI I1.4 13 − − −
14. DI I1.5 14 − − −
15. COM − 15 − − −

Test and Measuring Instruments and Software:

Sr. Name Model & Make Specification
1 Programmable Logic Controller
Trainer System S-12OO
2 Personal Computer
3 SEMATIC Step 7 TIA Portal TIA PORTAL V13

56
Procedure of Ladder Programming for PLC:
1. Open the software “TIA PORTAL V13”.
2. Select “Create new project “.
3. Open the project view.
4. In devices(left hand side )
> add new device
> SIMATIC S7-1200
> CPU (check the CPU name on PLC that is connected to the system and select the
same)
> CPU 1214C DC/DC/DC
> 6E S7 214-1AG40-0XB0
> OK.
5. CATELOG (on right hand side)
6. > Signal boards
> AQ
> AQ 1 X 12 BIT, Drag the module to the center square in 1st column
7. For second column
> DI/DQ
> DI 8 DQ 8 Relay
> 6E S7 223-1 PH32-0XB0, Drag this module in 2nd column.
8. For third column
> AI / AQ
> AI 4 13BIT AQ 2 14 BIT
> 6E S7 234-4HE32-0XB0, Drag this module in 3rd column. Minimize the window.
9. Open
> Program blocks (left hand side)
> Main [OB1] .
10. Create your program using the given input switches and output coils.
11. Select the switches and coils to give their name (e.g I0.0) and tag (if needed).
12. For program loading, Right click on
> PLC [CPU 1214C DC/DC/DC]
> Download to drive
> Hardware and software.
13. To see which devices are connected click on
> Start search
> Load
In reset
> No action
> Delete all (to erase previous program)
> Load.
14. > Go online
Verification of Logic Expressions: OR Logic
Logic: lf any one of the input IN0 OR IN1 is TRUE, output is TRUE.

Ladder Diagram:

57
1. Connect PB1 to IN0 and PB2 to IN1.
2. Connect output DQ0 to RED indicator.
3. Enter the program as above and RUN the program.
4. Press either PB1 or PB2, or any two or both and observe the status of output DQ0.

AND Logic

Logic: lf input IN0 AND IN1 is TRUE, output is TRUE.

Ladder Diagram:

1. Connect PB1 to IN0 and PB2 to IN1.

2. Connect output DQ2 to RED indicator.
3. Enter the program as above and RUN the program.
4. Press either PB1 or PB2, or any two or both and observe the status of output DO1.

Exercise:
Similarly write the ladder rungs, for the verification of the following logic gates and verify the
same on PLC.
▪ NOT logic
▪ NAND logic
▪ NOR logic
▪ X-OR logic

Results and Conclusions:

Comment on the observations

Frequently Asked Questions

1. What is PLC?
2. What are the advantages of PLC over other control systems?
3. What are the hardware blocks of PLC?
4. Explain PLC scan cycle.
5. What are the different methods of PLC programming?
6. What are the specifications of PLC used in the experiments?
7. List five leading PLC manufacturing companies in the world.

58
 B9 Ladder Programming – Latch, Timer, Counter

Aim: To implement latch, timer and counter on PLC using ladder programming
Objectives:
1. To familiarize the student with Programmable Logic Controllers (PLC) as hardware
and the software used
2. To study the ladder programming for latch, timer and counter functions
3. To implement latch, timer and counter on PLC using ladder programming

Test and Measuring Instruments and Software:

Sr. Name Model & Make Specification
1 Programmable Logic Controller
Trainer System S-12OO
2 Personal Computer
3 SEMATIC Step 7 TIA Portal TIA PORTAL V13

Introduction:
The simple functions like logic gates are implemented on PLC in previous experiment The
representation of contacts and output coil in the ladder programming are studied in previous
experiment. In this experiment, the timing and counting functions will be studied. The required
functions are described as below.

TP: Generate Pulse

User can use the Generate pulse instruction to set the output Q for a programmed duration. The
instruction is started when the result of logic operation (RLO) at input IN changes from "0" to
"1" (positive signal edge). The programmed time PT begins when the instruction starts. Output
Q is set for the duration PT, regardless of the subsequent course of the input signal. Even if a
new positive signal edge is detected, the signal state at the output Q is not affected as long as
the PT time duration is running. User can query the current time value at the ET output. The
timer value starts at T#0s and ends when the value of duration PT is reached. When the duration
PT is reached and the signal state at input IN is "0", the ET output is reset.
The following table shows the parameters of the "Generate pulse" instruction:

Parameter Declaration Data type Memorv area Description

IN Input BOOL I,Q, M, D, L Start input

I,Q, M, D, L Duration of the pulse. Value

PT Input TIME
Or constant of the PT must be positive

Q Output BOOL I,Q, M, D, L Pulse output

ET Output TIME I,Q, M, D, L Current time value

59
In the ladder shown below Generate pulse timer has been used for setting a pulse to a output
Lamp for particular or given time period. The block shown below is TP (Generate Pulse) Timer
which enables the input instruction used before timer gets ON. Here S1 is used as a input for
enabling timer and Lamp is used as a output which we have to keep on for a given time period.
Therefore, as Sl gets ON, timer begins functioning and Lamp stays ON for given time. The
logic used is simple series connection,

State of S1, TP and Lamp when S1 is OFF

Sate of S1, TP and Lamp when S1 is put ON and released

State of S1, TP and Lamp when TP stops after completing a given time

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TON: Generate on-delay
User can use the "Generate on-delay" instruction to delay setting of the Q output by the
programmed duration PT. The instruction is started when the result of logic operation (RLO)
at input lN changes from "0” to "1" (positive signal edge). The programmed time PT begins
when the instruction starts. When the duration PT expires, the output Q has the signal state "l".
Output Q remains set as long as the start input is still "1''. When the signal-state at the ‘start
input’ changes from "1" to "0", the output Q resets. The timer function is started again when a
new positive signal edge is detected at the start input.

User can query the current time value at the ET output. The timer value starts at T#0s and ends
when the value of duration PT is reached. The ET output is reset as soon as the signal state at
the IN input change to “0". Following table shows the parameters of the "Generate on-delay"
instruction.

Parameter Declaration Data type Memorv area Description

IN Input BOOL I,Q, M, D, L Start input

I,Q, M, D, L Duration of the on delay.

PT Input TIME Value of the PT must be
Or constant positive

Q Output BOOL I,Q, M, D, L Output is set when PT expires.

ET Output TIME I,Q, M, D, L Current time value

In the next ladder Delay timer is used for delaying the activation of Lamp. The block shown
below is TON (ON Delay timer) which enables when the input instruction used before timer
gets ON. Here, Sl is used as a input for enabling timer and Lamp is used as a output which we
have to make ON after delay of a given time period. Therefore, as S1 gets ON, timer begins
functioning-and Lamp gets ON after a delay of a given time.

1. State of S1, TON and Lamp, when S1 is OFF.

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2. State of S1, TON and Lamp, when S1 is put ON.

3. State of S1, TON and Lamp when S1 is kept ON and TON has reached to given time.

4. State of S1, TON and Lamp when S1 is put OFF.

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TOF: Generate off-delay
User can use the "Generate off-delay" instruction to delay resetting of the Q output by the
programmed duration PT. The Q output is set when the result of logic operation (RLO) at input
IN changes from "0" to "l" (positive signal edge), When the signal state at input IN changes
back to "0", the programmed time PT starts. Output e remains set as long as the duration PT is
running. When duration PT expires, the Q output is reset. If the signal state at input IN changes
to "1" before the PT time duration expires, the timer is reset. The signal state at the output Q
continues to be "1".

User can query the current time value at the ET output. The current timer value starts at T#0s
and ends when the value of the time duration PT is reached. When the time duration PT expires,
the ET output remains set to the current value until the IN input changes back to "1". If input
IN switches to "1" before the duration PT has expired, the ET output is reset to the value T#Os.
The following table shows the parameters of the "Generate off-delay”, instruction:

Parameter Declaration Data type Memorv area Description

IN Input BOOL I,Q, M, D, L Start input

I,Q, M, D, L Duration of the off delay.

PT Input TIME Value of the PT must be
Or constant positive

Q Output BOOL Output is reset when PT

I,Q, M, D, L
expires.

ET Output TIME I,Q, M, D, L Current time value

In the next ladder off timer is used for making a Lamp OFF after some time. The block shown
below is TOF (OFF Delay timer) which enables when the input instruction used before timer
gets ON. Here S1 is used as a input for enabling timer and Lamp is used as a output which we
have to make OFF after delay of a given time period. Therefore, as S1 gets ON, timer begins
functioning and Lamp gets OFF after a delay of a given time period.

1. State of S1, TOF and Lamp when S1 is OFF.

63
2. State of S1, TOF and Lamp when S1 is put ON.

3. State of S1, TOF and Lamp when S1 is put ON and released.

4. State of S1, TOF and Lamp when TOF has reached to the given time.

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CTU: Count up
User can use the "Count up" instruction to increment the value at output CV. When the signal
state at the.CU input changes from "0" to "1" (positive signal edge), the instruction executes
and the current counter value at the CV output is incremented by one. When the instruction
executes for the first time, the current counter value at the CV output is set to zero. The counter
value is incremented each time a positive signal edge is detected until it reaches the high limit
for the data type INT specified at the CV output. When the high limit is reached, the signal
state at the CU input no longer has an effect on the instruction.

User can scan the counter status at the Q output. The signal state at the Q output is determined
by the PV parameter. If the current counter value is greater than or equal to the value of the PV
parameter, the Q output is set to signal state "1". In all other cases, the Q output has signal state
"0". You can also specify a constant for the PV parameter.

The value at the CV output is reset to zero when the signal state at input R changes to "1". As
long as the R input has signal state "1", the signal state at the CU input has no effect on the
instruction.

• Each call of the "Count up" instruction must be assigned an IEC counter in which the
instruction data is stored.

You can declare an IEC counter as follows:

• Declaration of a data block of the type CTU (for example, " CTU_DB")

• Declaration as a local tag of the type CTU in the "static" section of a block,for example,
#MyCTU_COUNTER

The following table shows the parameters of the “Count up” instruction:

Parameter Declaration Data type Memory area Description

I,Q, M, D, L
CU Input BOOL Count input
OR constant

I,Q, M, D, L,P
R Input BOOL Reset input
OR constant

I,Q, M, D, L, P Value at which output

PV Input Integers
OR constant is set

Q Output BOOL I,Q, M, D, L Counter status

I,Q, M, D, L, P
CV Output Integers, Current counter value
CHAR, DATE

65
In the ladder shown below Up Counter is used for counting up the pulses generated by making
S1 ON and OFF. The block shown below is CTU (Count Up) which enables when the input
instruction used before Counter gets ON. Here, S1 is used as an input for enabling Counter,
and Lamp is used as an output which we have to make ON after a programmed value for setting
an output is reached. So, as S1 gets ON, counter begins counting up and Lamp gets ON after
reaching on a programmed or given value. Here you will find that up counter increments the
value at CV by 1 as its keeps getting the positive pulses from S1.

1. State of S1, CTU, CV and Lamp, when S1 is OFF

• Here the programmed value is 5 and MW 100 is the temporary memory variable where
the count value is stored.

2. State of S1, CTU, CV and Lamp when S1 is put ON and OFF for 2 time
• Counter has count up the pulse generated by making S1 ON and OFF for 2 time. Here
you can see the up counter has incremented the value at CV by l from 0 to 2 as it gets
the positive signal edges from S1.

66
3. State of S1, CTU and Lamp when S1 is put ON and OFF for 5 time
• Counter has count up the pulse generated by making S1 ON and OFF for 5 time. Here
you can see how Lamp gets on as the up counter reaches to the programmed or given
value i.e. 5.

Here you will find that the up counter keeps incrementing the value at CV by l as it keeps
getting the positive pulses from S1. In these situations, we need to bring it back on its initial
value for functioning again. Therefore, in the ladder shown below we have put one another
input device reset in counter block at R to reset the counter as well as lamp.

67
4. State of S1, CTU, Reset and Lamp when Reset is put ON Here you can see the counter is
reset and Lamp is OFF.

CTD: Count down

• User can use the “count down” instruction to decrement the value at output CV. When
signal state at the CD input changes from "0" to "1" (positive signal edge), the
instruction executes and the current counter value at the CV output is decremented by
one. When the instruction executes the first time, the counter value of the CV parameter
is set to the value of the PV parameter. Each time a positive signal edge is detected, the
counter value is decremented until it reaches the low limit value of the specified data
type (INT). When the low limit is reached, the signal state at the CD input no longer
has an effect on the instruction.

• User can scan the counter status at the Q output. If the current counter value is less than
or equal to zero, the Q output is set to signal state "1". In all other cases, the Q output
has signal state "0". You can scan also specify a constant for the parameter PV.

• The value at the CV output is set to the value of the PV parameter when the signal state
at the LD input changes to "1". As long as the LD input has signal state "1", the signal
state at the CD input has no effect on the instruction

• Each call of the "Count down" instruction must be assigned an IEC counter in which
the instruction data is stored.

You can declare an IEC counter as follows:

• Declaration of a data block of the type CTD (for example, "CTD-DB")

• Declaration as a local tag of the type CTD in the "Static" section of a block (for
example, #MyCTD-COUNTER)

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The following table shows the parameters of the "Count down" instruction:

Parameter Declaration Data type Memory area Description

I, Q, M, D, L
CD Input BOOL Count input
OR constant

I, Q, M, D, L,P
LD Input BOOL Load input
OR constant

I, Q, M, D, L, P
PV Input Integers Value at which Q is set
OR constant

Q Output BOOL I, Q, M, D, L Counter status

CV Output Integers, I, Q, M, D, L, P Current counter value

CHAR, DATE

In the ladder shown below Down Counter is used for counting down the pulses generated by
making the S1 ON and OFF. The Block shown below is CTD (Count Down) which enables
when the input instruction used before counter gets ON. Here S1 is used as a input for enabling
Counter, Lamp is used as a output which we have to make ON when programmed value for
setting a output is reached. So, as S1 gets ON, Counter begins counting down and Lamp gets
ON after reaching on a programmed or given value. Here you will find that down counter
decrements the value at CV by 1 as its keeps getting the positive pulses from S1.

1. State of S1, CTD and Lamp when S1 is OFF and Reset is OFF. Here Programmed value is
5.

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2. State of S1, CTD and Lamp when S1 is put ON and OFF for once (1 time), here you can
see the value has been decremented by 1 from 5 to 4 as S1 supplied the positive edge signal
to CTD.

3. State of S1, CTD and Lamp when S1 is put ON and OFF for 5 times, here you can see as
the value is decremented to the minimum value 0 the Lamp is started. This is how Down
Counter works.

Now as you can see just like in case of up Counter, down counter too is keep decrementing
the value at CV by 1 as it keeps getting the positive pulses from S1. In these situations, we
need to bring it back on its initial value for functioning again. Therefore, in the ladder
shown below we have put one another input device reset in counter block at LD which is
nothing but a Load Input to Load the Programmed Value once again and reset the counter
and Lamp both.

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4. State of S1, CTD, LD and Lamp when LD is put ON. Here you can see both CTD and
Lamp are reset and the PV is loaded once again in block.

Exercise:
Write the ladder rungs, for the verification of the following functions and verify the same on
PLC.
▪ Latch ▪ Generate on-delay ▪ UP Counter
▪ Generate Pulse ▪ Generate off delay ▪ Down Counter

Results and Conclusions

• Comment on the results

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Frequently Asked Questions

1. What is latch? How latch can be implemented on PLC?

2. What are the types of timers?
3. How various timers can be implemented on PLC?
4. What are the types of counters?
5. How various counters can be implemented on PLC?
6. Which parameters are used to generate a pulse in PLC programming?
7. Which parameters are used to generate on time delay in PLC programming?
8. Which parameters are used to generate off time delay in PLC programming?
9. Which parameters are used for up counting in PLC programming?
10. Which parameters are used for down counting in PLC programming?
11. List and explain the applications in which these functions studied in this experiment are
used.

72
73
74
 B10 Temperature Measurement and Control using PLC

Aim: To implement temperature measurement and ON-OFF control using PLC

Objectives:
1. To study various blocks of temperature measurement system using ON-OFF control
2. To design and implement the AC static switch using TRIAC
3. To design and implement the DC static switch using Power BJT

Test and Measuring Instruments:

Sr. Name Model & Make Specification
1 Programmable Logic Controller
Trainer, mod. PLC-8/EV
2 Personal computer
3 Heater + cooling fan arrangement
4 Temperature transmitter

Temperature Transmitter using RTD (Resistance Temperature Detector): Metallic

materials are basically structured molecules having free electrons. These free electrons in metal
give rise to conductivity to metals. When heated, these free electrons collide with each other
and lattice structure creating resistance to free motion of electrons thereby increasing resistance
of metal with increase in temperature. Within small range of temperature, temperature
coefficient is constant and resistance at temp t is given by
RT = R0[1+ α (T-To)] = R0(1+αT)
Where RT is resistance at temp T, R0 is resistance at temperature T0, α is temperature coefficient
of material and T is Temp difference (T- To).
The phenomenon of change in resistance due to increase in temperature of material is used in
temperature measurement. For pure, strain free annealed platinum characteristic is very good
and is generally used as temperature sensor. Temperature transmitter based on RTD type,
PT100 is used in this system to sense a temperature. PT100 has 100Ω resistance at 0 and its
temperature coefficient is 0.00385 within temperature range 0 - 100C. Temperature
transmitter gives 4 - 20 mA output for 0 - 100C change in temperature. However, as PLC is
having Analog Input as voltage, this signal is converted into 1 - 5V. This is achieved by
applying 4 to 20 mA output to 250Ω resistor.

• For 1 to 5 Volt input, PLC converts 2764 - 13824 integer value.

• Using NORMALISE and SCALE instructions 1 - 5 Volt DC input is converted to 0 -
100C.
• 1V = 2764 = 0 and 5V = 13824 = 100C
Temperature Transmitter Voltage across R250Ω), Equivalent Integer
Current, I V = I × 250Ω Value

0C 4 1 2764

100C 20 5 13824

75
Hence, integer value corresponding temperature is determined by

𝐼𝑁𝑇𝐸𝐺𝐸𝑅 = 2764 + (110.6 × 𝑇 0 𝐶)

The system consists of mainly, PLC S-1200, heater, Cooler, hooter, LED Lamps and PC with
PLC software. Two 40W electric bulbs are used for heating. For cooling exhaust fan is used.
The LED lamps are used for indication of the status of the temperature. Temperature transmitter
with PT-100 is used with 250Ω load to get voltage output corresponding to temperature in
given range. Temperature range is 0-100C. Since the outputs are dc type (24V), heater and
fan are driven by relay unit (2 Relays). The outputs Q0.0 and Q0.1 are connected to relay coils
and contacts of relays are connected to heater and fan. The following table gives information
of Tag assignments and PLC connections.

Sr. Tag Name Connection Connector Function

No. to PLC

Inputs 15 Pin D (M)

1 Start I0.0 1 Start Process

2 Stop I0.1 2 Stop Process

3 COM ⎯ 15

4 1-5V A0.0 ⎯ Temp. Transmitter Output

Connected to Analog Channel

Outputs 15 Pin D (F)

1 Lamp1−RED Q0.0 1 Indicates Low Temperature

2 Lamp2−YELLOW Q0.1 2 Indicates Normal Temperature

3 Hooter - Blue Q0.2 3 Lamp Indicates High

Temperature and Hooter On

4 Heater Q0.3 4 Lamp indicates Heater On

5 Cooling fan Q0.4 5 Lamp indicates Fan On

6 Common COM 15

Temperature Control System: Connection Details

76
 PLC PLC
Digital
Digital Outputs
Inputs Lamp
Red Q0
Lamp
IN0 START Yellow Q1

IN1 STOP Hooter Q2

Heater Q3

Cooler Q4
COM
COM (GND) COM COM

Block Diagram of Experimental Setup:

Exhaust Fan

PLC 230VAC
Cooling
S7-1200 Relay 3-Pin Electric
Heater cords
Bulbs (Heating)
Relay 230VAC

Temp. TX
I to V (250Ω)
(PT-100)
4-20mA

Heating and Cooling System

Procedure:
Setup Arrangement
1. Plug in RTD connector, in RTD socket of control unit.
2. Put the RTD sensor and mercury thermometer in process chamber.
3. Connect water heater power cord (AC mains power for heater) to the output socket of
control relay circuit (provided on right side of the trainer unit) and cooling fan cord to the
output socket of control relay circuit (provided on right side of the trainer unit).
4. Make power on to the unit.
5. Observe temperature of mercury thermometer and the output voltage, at the output of
temperature transmitter on DPM.
PLC Connections
6. Connect 1 - 5 V signal output from transmitter to Analog voltage input of PLC.
7. Connect Digital input and output from PLC to control unit.

77
8. Connect Heater (light Bulbs) and Cooling Fan to control unit at respective socket.
Program loading and Verification of System.
9. Develop a ladder program and load it in PLC.
10. Put PLC in RUN mode and verify the operation.

Operation of a System:
1. Start process by activating START button.
2. If Temperature is less than 30C, output Q0.3 activated, and Electric supply provided to
Heater coil.
3. When Temperature goes above 35C (High Temperature), output Q0.3 deactivated and
electric supply to heater coil cuts off and Q0.2 activated turning on hooter.
4. When Temperature goes below 35C, output Q0.2 deactivated, and hooter turns off.
5. If Temperature is above than 35C, output Q0.4 activated, and electric supply provided to
cooling Fan.
6. If Temperature is less than or equal to 30C, output Q0.4 deactivated and electric supply to
cooling Fan cuts off.
7. If Temperature is less than 25C (Low Temperature), output Q0.0 activated and RED Lamp
glows.
8. If Temperature is between 25 and 30C (Normal Temperature), output Q0.1 activated and
YELLOW Lamp glows.
9. Stop the process by activating STOP button.

Results:
• Draw a ladder program.
Conclusions:

Frequently Asked Questions

1. What is RTD? What are the specifications of PT-100?

2. What is current communication? Why it is preferred in industrial applications.
3. Explain 2 wire, 3 wire and 4 wire connection of RTD.
4. How will you assign integer value for the given temperature in this system?
5. Which parameters are associated with NORMALISE and SCALE instructions.
6. How are relays connected to the output of the PLC? Draw an electrical diagram.

78
Program:

79
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