K-MAP(Karnaugh Map)

synchronous counter 1
It is a graphical method used to simplify
It is a type of digital counter where all the flip-
logical expression. The K-map is a diagram
flops are triggered simultaneously by the same
which made-up of squares. Each square
clock pulse. Here are the key properties of
represent one minterm.Usually this method
synchronous counters:
1. Simultaneous Clocking: is employed for solving 2,3,4 variable
All flip-flops in the counter receive the same simplification.Once the Boolean expression is
clock pulse simultaneously, eliminating in SOP form, we can plot it in the K-map by
propagation delay between stages. placing 1 in each corresponding cell If the
2. Predictable Operation: map contains horizontally or vertically
Since all flip-flops are triggered together, the adjacent 1’s, then we represent t ,it as a pairIf
state transitions are predictable and occur the map contain group of 4 one’s, which are
without timing inconsistencies. horizontally or vertically adjacent, then we
3. High Speed: can represent it as a Quad. The 1’s may or
Synchronous counters are faster compared to may not be in end-to-end form If the map
asynchronous counters because there is no contain group of 8 one’s, which are
cumulative delay caused by ripple effects. horizontally or vertically
4. Complex Design: adjacent, then we can represent it as an
Synchronous counters require additional logic Octant. The 1’s may or may not be in end-to-
gates to control the inputs of each flip-flop, end form
making their design more complex compared to The map method is first proposed by veitch
asynchronous counters. and is modified by karnaugh. So that the map
is also called veitch diagram.Simplifying the
expression using K-map.In order to simplify
the expression, consider each group of 1’s to
create minterm. The variables that may
appear both complemented and
uncomplemented form are eliminated from
DeMorgan's Theorem is a powerful theorem in the SOP expressionIf the expression contains
Boolean algebra which has a set of two rules n terms, then the K-map contains 2n cells
or laws. These two laws were developed to
show the relationship between two variable
AND, OR, and NOT operations. These two rules DeMorgan's second law states that the
enable the variables to be negated, i.e. opposite complement of the product (ANDing) of
of their original form. Therefore, DeMorgan's variables is equivalent to the sum (ORing) of
theorem gives the dual of a logic function. their individual complements.
DeMorgan's First Law states that the In other words, the complement of two or more
complement of a sum (ORing) of variables is ANDed variables is equal to the sum of the
equal to the product (ANDing) of their individual complement of each of the individual variables,
complements. In other words, the complement i.e.,
of two or more ORed variables is equivalent to AB¯¯¯¯¯¯¯=A¯¯¯¯+B¯¯¯¯
the AND of the complements of each of the It may also be represented as,
individual variables, i.e. ⟮ AB⟯ ′=A′+B′
A+B¯¯¯¯¯¯¯¯¯¯¯¯¯=A¯⋅ B¯
Or, it may also be represented as,
⟮ A+B⟯ ′=A′⋅ B′
Sequential Circuits.
We discussed various combinational circuits. All 2 Types of Sequential Circuits
these circuits have a set of output(s), which Following are the two types of sequential
depends only on the combination of present circuits −
inputs. The following figure shows the block  Asynchronous sequential circuits
diagram of sequential circuit.  Synchronous sequential circuits

Asynchronous sequential circuits

If some or all the outputs of a
sequential circuit do not change
(affect) with respect to active transition
of clock signal, then that sequential
circuit is called as Asynchronous
sequential circuit. That means, all the
outputs of asynchronous sequential
circuits do not change (affect) at the
same time. Therefore, most of the
outputs of asynchronous sequential
circuits are not in synchronous with
This sequential circuit contains a set of inputs and either only positive edges or only
output(s). The output(s) of sequential circuit negative edges of clock signal.
depends not only on the combination of present
inputs but also on the previous output(s). Synchronous sequential circuits
Previous output is nothing but the present state. If all the outputs of a sequential circuit
change (affect) with respect to active
Therefore, sequential circuits contain transition of clock signal, then that
combinational circuits along with memory sequential circuit is called as
(storage) elements. Some sequential circuits may Synchronous sequential circuit. That
not contain combinational circuits, but only means, all the outputs of synchronous
memory elements. sequential circuits change (affect) at
the same time. Therefore, the outputs
Following table shows the differences between of synchronous sequential circuits are
combinational circuits and sequential circuits. in synchronous with either only
positive edges or only negative edges
Combinational Circuits Sequential Circuits of clock signal.
Outputs depend on both
Outputs depend only on
present inputs and present
present inputs. state.
Feedback path is not
Feedback path is present.
present.
Types of Triggering 3
Following are the two possible types of triggering that are used in sequential circuits.
 Level triggering
 Edge triggering

Level triggering
There are two levels, namely logic High and logic Low in clock signal. Following are the two
types of level triggering.
 Positive level triggering
 Negative level triggering
If the sequential circuit is operated with the clock signal when it is in Logic High, then that type
of triggering is known as Positive level triggering. It is highlighted in below figure.

If the sequential circuit is operated with the clock signal when it is in Logic Low, then that type
of triggering is known as Negative level triggering. It is highlighted in the following figure.

Edge triggering
There are two types of transitions that occur in clock signal. That means, the clock signal
transitions either from Logic Low to Logic High or Logic High to Logic Low.

Following are the two types of edge triggering based on the transitions of clock signal.
 Positive edge triggering
 Negative edge triggering

If the sequential circuit is operated with the clock signal that is transitioning from Logic Low
to Logic High, then that type of triggering is known as Positive edge triggering. It is also called
as rising edge triggering. It is shown in the following figure.

If the sequential circuit is operated with the clock signal that is transitioning from Logic High
to Logic Low, then that type of triggering is known as Negative edge triggering. It is also
called as falling edge triggering. It is shown in the following figure.
 4
Latches
There are two types of memory elements based on the type of triggering that is suitable to
operate it.
 Latches
 Flip-flops
Latches operate with enable signal, which is level sensitive. Whereas, flip-flops are edge
sensitive. We will discuss about flip-flops in next chapter. Now, let us discuss about SR
Latch & D Latch one by one.

SR Latch
SR Latch is also called as Set Reset Latch. This latch affects the outputs as long as the
enable, E is maintained at ‘1’. The circuit diagram of SR Latch is shown in the following
figure.

This circuit has two inputs S & R and two outputs Q(t) & Q(t)’. The upper NOR gate has two
inputs R & complement of present state, Q(t)’ and produces next state, Q(t+1) when enable,
E is ‘1’. Similarly, the lower NOR gate has two inputs S & present state, Q(t) and produces
complement of next state, Q(t+1)’ when enable, E is ‘1’.

We know that a 2-input NOR gate produces an output, which is the complement of another
input when one of the input is ‘0’. Similarly, it produces ‘0’ output, when one of the input is
‘1’.
 If S=1, then next state Q(t+1) will be equal to ‘1’ irrespective of present state, Q(t) values.
 If R=1, then next state Q(t+1) will be equal to ‘0’ irrespective of present state, Q(t) values.

At any time, only of those two inputs should be ‘1’. If both inputs are ‘1’, then the next state
Q(t+1) value is undefined.
The following table shows the state table of SR latch.
S R Q(t+1)
0 0 Q(t)
0 1 0
1 0 1
1 1 -
Therefore, SR Latch performs three types of functions such as Hold, Set & Reset based on the
input conditions. 5

D Latch
There is one drawback of SR Latch. That is the next state value can’t be predicted when both
the inputs S & R are one. So, we can overcome this difficulty by D Latch. It is also called as
Data Latch. The circuit diagram of D Latch is shown in the following figure.

This circuit has single input D and two outputs Q(t) & Q(t)’. D Latch is obtained from SR Latch
by placing an inverter between S amp;& R inputs and connect D input to S. That means we
eliminated the combinations of S & R are of same value.
 If D=0 → S=0 & R=1, then next state Q(t+1) will be equal to ‘0’ irrespective of present state,
Q(t) values. This is corresponding to the second row of SR Latch state table.
 If D=1 → S=1 & R=0, then next state Q(t+1) will be equal to ‘1’ irrespective of present state, Q(t)
values. This is corresponding to the third row of SR Latch state table.

The following table shows the state table of D latch.

D Q(t+1)
0 0
1 1
Therefore, D Latch Hold the information that is available on data input, D. That means the output
of D Latch is sensitive to the changes in the input, D as long as the enable is High.
We implemented various Latches by providing the cross coupling between NOR gates.
Similarly, you can implement these Latches using NAND gates.

Flip-flops
Latches are the basic building blocks of flip-flops. We can implement flip-flops in two
methods.
In first method, cascade two latches in such a way that the first latch is enabled for every
positive clock pulse and second latch is enabled for every negative clock pulse. So that the
combination of these two latches become a flip-flop.

In second method, we can directly implement the flip-flop, which is edge sensitive. In this
chapter, let us discuss the following flip-flops using second method.
 SR Flip-Flop
 D Flip-Flop
 JK Flip-Flop
 T Flip-Flop
SR Flip-Flop
6
SR flip-flop operates with only positive clock transitions or negative clock transitions.
Whereas, SR latch operates with enable signal. The circuit diagram of SR flip-flop is shown in
the following figure.

This circuit has two inputs S & R and two outputs Q(t) & Q(t)’. The operation of SR flip-flop is
similar to SR Latch. But, this flip- flop affects the outputs only when positive transition of the
clock signal is applied instead of active enable.

The following table shows the state table of SR flip-flop.

S R Q(t+1)
0 0 Q(t+1)
0 1 0
1 0 1
1 1 -

Here, Q(t) & Q(t+1) are present state & next state respectively. So, SR flip-flop can be used for
one of these three functions such as Hold, Reset & Set based on the input conditions, when
positive transition of clock signal is applied. The following table shows the characteristic table
of SR flip-flop.By using three variable K-Map, we can get the simplified expression for next
state, Q(t+1). The three variable K-Map for next state, Q(t+1). The maximum possible groupings
of adjacent ones are already shown in the figure. Therefore, the simplified expression for
next state Q(t+1) is
Q(t+1)=S+R′Q(t)

D Flip-Flop
D flip-flop operates with only positive clock transitions or negative clock transitions.
Whereas, D latch operates with enable signal. That means, the output of D flip-flop is
insensitive to the changes in the input, D except for active transition of the clock signal. The
circuit diagram of D flip-flop is shown in the following figure.
 7
This circuit has single input D and two outputs Q(t) & Q(t)’. The operation of D flip-flop is similar to
D Latch. But, this flip-flop affects the outputs only when positive transition of the clock signal is
applied instead of active enable.
The following table shows the state table of D flip-flop.
D Q(t+1)
0 0
0 1
Therefore, D flip-flop always Hold the information, which is available on data input, D of
earlier positive transition of clock signal. From the above state table, we can directly write the
next state equation as
Q(t+1)=D

Next state of D flip-flop is always equal to data input, D for every positive transition of the
clock signal. Hence, D flip-flops can be used in registers, shift registers and some of the
counters.

JK Flip-Flop
JK flip-flop is the modified version of SR flip-flop. It operates with only positive clock
transitions or negative clock transitions. The circuit diagram of JK flip-flop is shown in the
following figure.

This circuit has two inputs J & K and two outputs Q(t) & Q(t)’. The operation of JK flip-flop is
similar to SR flip-flop. Here, we considered the inputs of SR flip-flop as S=J Q(t)’ and R=KQ(t) in
order to utilize the modified SR flip-flop for 4 combinations of inputs.The following table shows
the state table of JK flip-flop.
J K Q(t+1)
0 0 Q(t)
0 1 0
1 0 1
1 1 Q(t)'
Here, Q(t) & Q(t+1) are present state & next state respectively. So, JK flip-flop can be used for
one of these four functions such as Hold, Reset, Set & Complement of present state based on
the input conditions, when positive transition of clock signal is applied. The following table
shows the characteristic table of JK flip-flop.
 Present Inputs Present State Next State
8
J K Q(t) Q(t+1)
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
The maximum possible groupings of adjacent ones are already shown in the figure. Therefore,
the simplified expression for next state Q(t+1) is
Q(t+1)=JQ(t)′+K′Q(t)

T Flip-Flop
T flip-flop is the simplified version of JK flip-flop. It is obtained by connecting the same input
‘T’ to both inputs of JK flip-flop. It operates with only positive clock transitions or negative
clock transitions. The circuit diagram of T flip-flop is shown in the following figure.

This circuit has single input T and two outputs Q(t) & Q(t)’. The operation of T flip-flop is same
as that of JK flip-flop. Here, we considered the inputs of JK flip-flop as J=T and K=T in order to
utilize the modified JK flip-flop for 2 combinations of inputs. So, we eliminated the other two
combinations of J & K, for which those two values are complement to each other in T flip-flop.
The following table shows the state table of T flip-flop.
D Q(t+1)
0 Q(t)
1 Q(t)’
Here, Q(t) & Q(t+1) are present state & next state respectively. So, T flip-flop can be used for
one of these two functions such as Hold, & Complement of present state based on the input
conditions, when positive transition of clock signal is applied.
Construction of an R-S Flip-Flop Using NOR Gates:
9

An R-S (Reset-Set) flip-flop is a basic type of bistable multivibrator that has two inputs: R (Reset)
and S (Set), and two outputs: Q and Q' (the inverse of Q). It can store one bit of data, and its state
can be changed based on the inputs.
Circuit Construction:
1. Two NOR gates are connected in a feedback configuration, where the output of each NOR gate
is connected to one of the inputs of the other NOR gate.

- The first NOR gate has inputs: R (Reset) and the output of the second NOR gate (which is Q').
- The second NOR gate has inputs: S (Set) and the output of the first NOR gate (which is Q).
2. The outputs of the two NOR gates are Q and Q', where:
- Q is the output of the first NOR gate.
- Q' is the output of the second NOR gate.
Explanation of Working
1. R = 0, S = 0 (Hold State):
- When both R and S are 0, the state of the flip-flop remains unchanged (it "holds" its state).
The outputs Q and Q' will remain in their previous states.

2. R = 0, S = 1 (Set Condition):
- When S is 1 and R is 0, the output Q is set to 1, and Q' is set to 0. This is the set condition.

3. R = 1, S = 0 (Reset Condition):
- When R is 1 and S is 0, the output Q is reset to 0, and Q' is set to 1. This is the reset condition.

4. R = 1, S = 1 (Invalid Condition):

When both R and S are 1, the outputs are not valid. This combination causes both outputs Q and Q'
to be 0, which violates the basic rule of the flip-flop (because Q and Q' should always be
complementary). Hence, this state is undefined or invalid.

Working with NOR Gates:

The NOR gate produces an output of 1 only when both inputs are 0. Otherwise, the output is 0.
- In the Set and Reset conditions, one of the inputs of each NOR gate will be 0, while the other will
control the output.
- The feedback loops ensure that once the flip-flop is set or reset, it retains its state until the next
input change
 10

S-R Flip-flop Switching Diagram

This unbalance can cause one of the outputs to switch faster than the other resulting in the
flip-flop switching to one state or the other which may not be the required state and data
corruption will exist. This unstable condition is generally known as its Meta-stable state.
This unbalance can cause one of the outputs to switch faster than the other resulting in the
flip-flop switching to one state or the other which may not be the required state and data
corruption will exist. This unstable condition is generally known as its Meta-stable state.
Then, a simple NAND gate SR flip-flop or NAND gate SR latch can be set by applying a logic “0”,
(LOW) condition to its Set input and reset again by then applying a logic “0” to its Reset input.
The SR flip-flop is said to be in an “invalid” condition (Meta- stable) if both the set and reset
inputs are activated simultaneously.As we have seen above, the basic NAND gate SR flip-flop
requires logic “0” inputs to flip or change state from Q to Q’ and vice versa. We can however,
change this basic flip-flop circuit to one that changes state by the application of positive going
input signals with the addition of two extra NAND gates connected as inverters to the S and R
inputs.

ASCII Code (American Standard Code for Information Interchange)

ASCII (American Standard Code for Information Interchange) is a character encoding standard
used to represent text and control characters in computers and other electronic devices. It was
developed in the early 1960s and has since become a fundamental part of computing and
communication systems.ASCII uses 7 bits to represent each character, which allows for 128
unique symbols (0–127). These symbols include:Control characters (0–31): Non-printable
characters used for control purposes (e.g., carriage return, line feed, tab).ASCII is widely used in
text files, programming languages, data communication protocols, and more. It serves as the
foundation for modern character encoding systems such as UTF-8 (which is backward-compatible
with ASCII).
Edge triggered flip flops
Another type of simple edge-triggered flip-flop which 11 is very similar to the RS flip-flop called
a JK Flip-flop named after its inventor, Jack Kilby. The JK flip-flop is the most widely used of
all the flip-flop designs as it is considered to be a universal device.
The S = 0 and R = 0 condition (S = R = 0) must always be avoided, and if S or R change state while
the enable input is high the correct latching action may not occur. Then to overcome these two
fundamental design problems with the SR flip-flop design, the JK flip Flop was developed.

This simple JK flip Flop is the most widely used of all the flip- flop designs and is considered
to be a universal flip-flop circuit. The sequential operation of the JK flip flop is exactly the same
as for the previous SR flip-flop with the same “Set” and “Reset” inputs. The difference this time
is that the “JK flip flop” has no invalid or forbidden input states of the SR Latch even when S
and R are both at logic “1”.

The JK flip flop is basically a gated SR flip-flop with the addition of a clock input circuitry that
prevents the illegal or invalid output condition that can occur when both inputs S and R are
equal to logic level “1”. Due to this additional clocked input, a JK flip-flop has four possible input
combinations, “logic 1”, “logic 0”, “no change” and “toggle”. The symbol for a JK flip flop is
similar to that of an SR Bistable Latch as seen in the previous tutorial except for the addition
of a clock input.
The Basic JK Flip-flop

Both the S and the R inputs of the previous SR bistable have now been replaced by two inputs
called the J and K inputs, respectively after its inventor Jack Kilby. Then this equates to: J = S
and K = R.The two 2-input AND gates of the gated SR bistable have now been replaced by two
3-input NAND gates with the third input of each gate connected to the outputs at Q and Q’. This
cross coupling of the SR flip-flop allows the previously invalid condition of S = “1” and R = “1”
state to be used to produce a “toggle action” as the two inputs are now interlocked.
If the circuit is now “SET” the J input is inhibited by the “0” status of Q’ through the lower NAND
gate. If the circuit is “RESET” the K input is inhibited by the “0” status of Q through the upper
NAND gate. As Q and Q’ are always different we can use them to control the input. When both
inputs J and K are equal to logic “1”, the JK flip flop toggle.Then the JK flip-flop is basically an
SR flip flop with feedback which enables only one of its two input terminals, either SET or
RESET to be active at any one time thereby eliminating the invalid condition seen previously in
the SR flip flop circuit.
 12
5-bit ring counter
A 5-bit ring counter is a type of counter in which a single "1" (or "high" state) is shifted around in
a circular manner between 5 flip-flops. In this counter, the output of the last flip-flop is fed back
to the input of the first flip-flop, creating a continuous loop. The ring counter is used in various
applications like sequencing, timing, and state machines.
Components:
5 D flip-flops (or JK flip-flops configured as T flip-flops).
Clock signal (for synchronization).
Feedback connection from the last flip-flop (Q output) to the input of the first flip-flop.
The ring counter is initialized such that only one flip-flop is set to "1," and all others are "0."
Typically, this can be done by a preset or external reset.
The ring counter is initialized such that only one flip-flop is set to "1," and all others are "0."
Typically, this can be done by a preset or external reset.
The Q output of the last flip-flop (flip-flop 5) is connected to the D input of the first flip-flop (flip-
flop 1).All flip-flops share a common clock signal to ensure synchronization.

Shift Register
We know that one flip-flop can store one-bit of information. In order to store multiple bits of
information, we require multiple flip-flops. The group of flip-flops, which are used to hold
(store) the binary data is known as register.If the register is capable of shifting bits either
towards right hand side or towards left hand side is known as shift register. An ‘N’ bit shift
register contains ‘N’ flip-flops. Following are the four types of shift registers based on
applying inputs and accessing of outputs.
 Serial In - Serial Out shift register
 Serial In - Parallel Out shift register
 Parallel In - Serial Out shift register
 Parallel In - Parallel Out shift register

Serial In - Serial Out (SISO) Shift Register

The shift register, which allows serial input and produces serial output is known as Serial In
– Serial Out (SISO) shift register.
The block diagram of 3-bit SISO shift register is shown in the following figure.

This block diagram consists of three D flip-flops, which are

cascaded. That means, output of one D flip-flop is connected as the input of next D flip-
flop. All these flip-flops are synchronous with each other since, the same clock signal is
applied to each one. In this shift register, we can send the bits serially from the input of left
most D flip-flop. Hence,this input is also called as serial
input. For every positive edge triggering of clock signal, the data shifts from one stage to the
next. So, we can receive the bits serially from the output of right most D flip-flop. Hence, this
output is also called as serial output.