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ICC2_SAED32nm_Flow

The document outlines the Synopsys ICC2 compilation flow using SAED 32nm technology, detailing the necessary environment setup, design reading, floorplanning, placement, clock tree synthesis, routing, signoff checks, and final GDSII generation. It provides specific commands and scripts for each step, culminating in executing the compilation flow through a saved script. This comprehensive guide serves as a reference for users working with ICC2 in a 32nm design environment.

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prathiba
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39 views

ICC2_SAED32nm_Flow

The document outlines the Synopsys ICC2 compilation flow using SAED 32nm technology, detailing the necessary environment setup, design reading, floorplanning, placement, clock tree synthesis, routing, signoff checks, and final GDSII generation. It provides specific commands and scripts for each step, culminating in executing the compilation flow through a saved script. This comprehensive guide serves as a reference for users working with ICC2 in a 32nm design environment.

Uploaded by

prathiba
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Synopsys ICC2 Compilation Flow using SAED 32nm

1. Setup Environment
--------------------
Before running ICC2, set up your environment variables, including library paths and tool settings.

```bash
source /path_to_synopsys_tools/synopsys_setup.sh
export ICC2_HOME=/path_to_icc2
export SAED32NM_LIB=/path_to_saed32nm
export DESIGN_NAME=my_design
export WORK_DIR=/path_to_working_directory
```

2. Read and Setup the Design


----------------------------
Create an ICC2 script (e.g., `icc2_script.tcl`) and follow these steps:

```tcl
icc2_shell

set project_name "my_project"


set_design_library -path ${WORK_DIR}/work_lib

read_verilog ./netlist/my_design.v
read_liberty ${SAED32NM_LIB}/saed32nm.lib
read_def ./floorplan/my_design.def
read_sdc ./constraints/my_design.sdc

set_top_module my_design
set_db library ${SAED32NM_LIB}/saed32nm.db
set_db search_path [list ${SAED32NM_LIB} ./lib]
```

3. Floorplanning
----------------
```tcl
create_floorplan -core_utilization 0.7 -aspect_ratio 1 -row_core_ratio 0.9 -left_io2core 5 -right_io2core 5
-top_io2core 5 -bottom_io2core 5

create_pg_grid -supply_net VDD -ground_net VSS


```
4. Placement
------------
```tcl
place_opt -effort high
check_placement
legalize_placement
```

5. Clock Tree Synthesis (CTS)


-----------------------------
```tcl
set_clock_tree_options -balance_skew -target_skew 0.1
clock_opt
```

6. Routing
----------
```tcl
route_auto -global
route_auto -detail
verify_drc
```

7. Signoff Checks
-----------------
```tcl
report_timing -path full -delay max -max_paths 10
report_power
verify_drc
verify_lvs
```

8. Generate Final GDSII for Tapeout


-----------------------------------
```tcl
write_gds -hierarchical -output ./final_output/my_design.gds
```

9. Save and Exit


----------------
```tcl
save_design -as final_icc2_design
exit
```
Running the Script
------------------
Save the script (e.g., `icc2_flow.tcl`) and execute it using:

```bash
icc2_shell -f icc2_flow.tcl | tee icc2_run.log
```

This script covers the major ICC2 steps using SAED 32nm libraries.

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