Scribd
Upload
64 views

Synopsys_ICC2_Flow

The document outlines the steps for using the Synopsys ICC2 Compiler with SAED 32nm technology. It includes instructions for setting up the environment, reading technology libraries and design netlists, performing floorplanning, placement, clock tree synthesis, routing, signoff checks, and writing the final GDSII file. Both script commands and GUI steps are provided for each stage of the process.

Uploaded by

prathiba
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
64 views

Synopsys_ICC2_Flow

The document outlines the steps for using the Synopsys ICC2 Compiler with SAED 32nm technology. It includes instructions for setting up the environment, reading technology libraries and design netlists, performing floorplanning, placement, clock tree synthesis, routing, signoff checks, and writing the final GDSII file. Both script commands and GUI steps are provided for each stage of the process.

Uploaded by

prathiba
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 2

Synopsys ICC2 Compiler Steps using SAED 32nm

1. Setup Environment
- Script:
- source /path/to/synopsys/setup.sh
- export ICC2_HOME=/path/to/icc2
- export PATH=$ICC2_HOME/bin:$PATH
- GUI Steps:
- 1. Open a terminal and source the setup script.
- 2. Run icc2_shell or icc2_gui to launch the tool.

2. Read Technology Libraries


- Script:
- set search_path "/path/to/saed32nm"
- set tech_lib "saed32nm_tech.lef"
- set std_cell_lib "saed32nm_std.db"
- set_tlu_plus_files -max_tluplus saed32nm_max.tluplus -min_tluplus saed32nm_min.tluplus
-tech2itf saed32nm.itf
- read_liberty $std_cell_lib
- read_lef $tech_lib
- GUI Steps:
- 1. Go to File > Load Library
- 2. Select Technology LEF and Standard Cell Library
- 3. Browse to the SAED 32nm technology files and load them.

3. Read Design Netlist


- Script:
- read_verilog my_design.v
- current_design my_top_module
- GUI Steps:
- 1. Navigate to File > Import Netlist
- 2. Select your Verilog file (my_design.v) and load it.

4. Floorplanning
- Script:
- initialize_floorplan -core_utilization 0.7 -aspect_ratio 1 -core_offset {2 2 2 2}
- GUI Steps:
- 1. Go to Floorplan > Initialize Floorplan
- 2. Set core utilization, aspect ratio, and core offset values.

5. Placement
- Script:
- place_design
- legalize_placement
- GUI Steps:
- 1. Navigate to Placement > Place Standard Cells
- 2. Click Run Placement
- 3. After placement, run Legalize Placement.

6. Clock Tree Synthesis (CTS)


- Script:
- create_clock -name clk -period 1.0 [get_ports clk]
- derive_clock_timing
- route_clock_tree
- GUI Steps:
- 1. Go to Clock > Create Clock
- 2. Define the clock period and run CTS.

7. Routing
- Script:
- route_design
- GUI Steps:
- 1. Navigate to Routing > Route Design
- 2. Click Start Routing.

8. Signoff (DRC, LVS, STA)


- Script:
- check_drc
- check_lvs
- report_timing
- GUI Steps:
- 1. Go to Analysis > Design Rule Check
- 2. Run LVS Check
- 3. Run Static Timing Analysis (STA).

9. Write Final GDSII


- Script:
- write_gds my_design.gds
- GUI Steps:
- 1. Go to File > Export GDSII
- 2. Set output file as my_design.gds and save.

You might also like