11 L8B0SEE 129

269100
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 2.2 Test Generation Techniques for Combinational Circuits 21

Chapter 2 |- Test Generation for a process known as fault-simulation is performed [2.1]. For example, if a circuit
Combinational Logic Circuits has x stuck-at faults, then fault simulation is the process of applying every test
pattern to the fault-free circuit, and to each of the x copies ofthe circuit containing
exactly one stuck-at fault. When all test patterns have been simulated against all
the faults x, the detected faults f are used to compute the fault coverage (f.) which
is defined as

Instead of simulating one fault at a time, the method of parallel simulation, which
uses the word size N of a host computer to process N faults at a time, can be
employed. Another approach is to utilize the deductive simulation method, which
allows simulation of all faults simultaneously but is much harder to implement
and requires enormous memory capacity for larger circuits.
2.1 Fault Diagnosis of Digital Circuits It has been shown that the time required to compute test patterns for a com-
binational circuit grows in proportion to the square of the number of gates in the
Digital circuits, even when designed with highly reliable components, do not circuit [2.2]. Hence, for circuits of VLSI complexity the computation time re-
operate forever without developing some faults. When a circuit ultimately does quired for test generation is often unacceptably high.
develop a fault, it has to be detected and located so that its effect can be removed.
Fault detection means the discovery of something wrong in a digital system or
circuit. Fault location means the identification of the faults with components, 2.2 Test Generation Techniques for Combinational Circuits
functional modules, or subsystems, depending on the requirements. Fault diag-
nosis includes both fault detection and fault location. There are several methods available for deriving tests for combinational circuits.
Fault detection in a logic circuit is carried out by applying a sequence of test All these methods are based on the assumption that the circuit under test is non-
inputs and observing the resulting outputs. Therefore, the cost of testing includes redundant and only a single stuck-at fault is present at any time. In this section,
the generation of test sequences and their application. One of the main objectives
we discuss each method in some detail.
in testing is to minimize the length of the test sequence. Any fault in a nonre-
dundent* n-input combinational circuit can be completely tested by applying all
2.2.1 ONE-DIMENSIONAL PATH SENSITIZATION
2" input combinations to it; however, 2" increases very rapidly as n increases. For
a sequential circuit with n inputs and m flip-flops, the total number of input The basic principle involved in path sensitizing is to choose some path from the
combinations necessary to test the circuit exhaustively is 2" X 2" = 2"*"_If, for origin of the failure to the circuit output. The path is said to be “‘sensitized”” if
example, n = 20, m = 40, there would be 2 tests. At a rate of 10,000 tests per the inputs to the gates along the path are assigned values so as to propagate the
second, the total test time for the circuit would be about 33 million years! For- fault along the chosen path to the output [2.3].
tunately, a complete truth-table exercise of a logic circuit is not necessary—only The method can be illustrated with an example. Let us consider the circuit
the number of input combinations that detect most of the faults in the circuit is shown in Fig. 2.1 and suppose that the fault is line X5 s-a-1. To test X ; for s-a-1,
required. To determine which faults have been detected by a set of test patterns, X5 and G, must be set at 1 and X set at 0, so that G5 = 1 if the fault is absent.
We now have a choice of propagating the fault from G5 to the circuit output Z
*A circuit is said to be nonredundant if the function realized by the circuit is not the same as the via a path through GG or through G Gs. To propagate through GG, requires
function realized by the circuit in the presence of a fault. the output of G, and Gy to be 1. If G, = 1, the output of G, depends on the

20
22 2. Test Generation for Combinational Logic Circuits 2.2 Test Generation Techniques for Combinational Circuits 23
v, X,
X, G G
X

Figure 2.1 Circuit with a s-a-1 fault

output of Gs, and similarly if Gg = 1, the circuit output depends on G, only. X5

This process of propagating the effect of the fault from its original lécation to the Figure 2.2 Example circuit
circuit output is known as the forward trace. The next phase of the method is the
backward trace, in which the necessary gate conditions to propagate the fault X4 = 0 sensitizes the two paths simultaneously and also makes G, = G, = 0.
along the sensitized path are established. For example, to set G4 at 1 both X, and
Thus, two inputs to G change from 0 to 1 as a result of the fault G, s-a-0, while
G, must be set at 1; G, = 1 implies X, = 0. For G, to be 1, X, must be set at
the remaining two inputs remain fixed at 0. The fault will cause the output of G
0. for G to be 1, G, must be 0, which requires either X, = 0 or G; = 0. Since
to change from 1 to 0 and Y,YZYJ)TA is a test for G s-a-0.
X, has already been specified as 0, the output of G will be 0. It is worth noting The foregoing example shows the necessity of sensitizing more than one path
that G cannot be set at 0 by making G ; = 0, because this would imply X5 = 1, in deriving tests for certain faults. This is the principal idea behind the D-algo-
which is inconsistent with the previous assignment of X;. Therefore, the test rithm (see Sec. 2.2.3).
X,X,X3X,X5 = 10001 detects the fault X5 s-a-1, because the output of Z will
be O for the fault-free circuit and 1 for the circuit having the fault.
In general, the input combination generated by the path-sensitization procedure 2.2.2 BOOLEAN DIFFERENCE
for propagating a fault to the output may not be unique. For example, the X5 s-a-
The basic principle of the Boolean difference is to derive two Boolean expres-
1 fault in the circuit of Fig. 2.1 can also be detected by the test X, X,X3X,Xs =
sions—one of which represents normal fault-free behavior of the circuit, and the
—1001; this is done by sensitizing the path GsG3Go. X, has an unspecified value
other, the logical behavior under an assumed single s-a-1 or s-a-0 fault condition.
in this test; that is, the test is independent of input X .
These two expressions are then exclusive-ORed; If the result is 1, a fault is in-
The flaw in the one-dimensional path sensitization technique is that only one
dicated [2.5].
path is sensitized at a time. The following example shows the inadequacy of this
Let F(X) = F(xy, ..., x,) be a logic function of n variables. If one of the
procedure [2.4].
inputs to the logic function, for example, input x;, is faulty, then the output would
Let us try to derive a test for the fault G, s-a-0 in Fig. 2.2 by sensitizing the
be F(xy, ..., X, ..., x,). The Boolean difference of F(X) with respect to x; is
path G,G 4Gy We set X, = X3 = 0 so as to propagate the effect of the fault
defined as
through gate G,. Setting X, = 0 propagates it through gate G¢. To propagate it
through gate G, we require G4 = G5 = G; = 0. Because X, and X, have already aF(xy, ... X 0 X)) _ dFX)
been set to 0, we have G5 = 1, which makes G, = 0. To make G5 = 0, X; must dx; dx;
be set to 1; consequently, G, = 0, which with X, = 0 would make G, = 1.
=F(y,
s X X)) @ FO, o, XX)),
Therefore, we are unable to propagate through Gy. Similarly, we can show that
it is impossible to sensitize the single path G,G sG 3. However, we note that X ; = The function dF(X)/dx; is called the Boolean difference of F(X) with respect to x,.
24 2. Test G\eneration for Combinational Logic Circuits 2.2 Test Generation Techniques for Combinational Circuits 25

It is easy to see that when F(x,, ...,AX5 0255 X)) FF, oo X X)), AFX) _ d(xixs + x3xy)
dF(X)/dx; = 1, and that when F(x, ..., x;, ..., Fz) = FQy e o w5y, ies By dxy dxs
dF(X)/dx; = 0. To detect a fault on x;, it is necessary to find input combinations
_ ——dxaxy) — d(x,x5) _ d(x,x5) d(xsxy)
(tests) so that whenever x; changes to X; (due to a fault), F(xy, ..., X;, ..., x,) X5 a6 @ x3x4 & @ & Fre (By property 5)
will be different from F(x,, ..., %, ..., x,). In other words, the aim is to find
input combinations for each fault occurring on x; such that dF(X)/dx; = 1.
(By property 6)
Some useful properties of the Boolean difference are

dFX) _ dF(X (By property 4)

1, 4K_ dF ) ; F(X) denotes the complement of F(X).
dx, dx,
= X|XpXg. (By properties 6 and 7)
5 dF(X) _ dF(X)
Tody dy; This means that a fault on x; will cause the output to be in error only if
d dFX) _ d dFX) = 1, that is, if x, or x, (or both) are equal to 0 and x, is equal to 1. This
can be verified by inspection of Fig. 2.3(a).
Tdx o dy; dx dx;
dIF(X)GX)] dG(X dF(X) _ dF(X) dGX) Example 2 Consider the logic circuit shown in Fig. 2.3(b). Find the Boolean
4. @, = FX) @ G(X) pm @ e difference with respect to x,. We have
5 d[F|
[F(X) + GX)] —FdG(X) eXees) dF(X ) ® dF(?() . dG(X)- dF(X) _ d(xxs + x )
dx; [x; dx; dx; dx, dx

A Boolean function F(X) is said to be independent of x, if and only if F(X) is _ ——d0 dxixy) d(x,xs) dx)
= XX, dr, @ X% a @ @, B o (By property 5)
logically invariant under complementation of x;, that is, if

Flxpy, ooy X oo,X)) — Bl ¥1z010 55 Kp5 ¢ res Xog)

=5 @NE - x @x (By properties 1, 7, and 8)
=000 @ X)) @ x,
This implies that a fault in x; will not affect the final output F(X) and dF (x)/dx; -2 T
206005 X ) @ x,
= 0. Some additional properties can now be added to the original set (1-5):
=0l@ + Bk + @+ )] @ x
6. @
i, =0 if F(X) is independent of ;.
=xlo® + 0] @ X
=0 ®x
dF (X
7. %% _ 1 it Fx) depends only on . =0.
dx;
5. % - FX) d& if F(X) is independent
dIFX
of x,. X X
460 X X
9 w ooy dG(X)
&2 if F(X) is independent of x;.
X F F

To illustrate how the Boolean difference is used, we look at two examples. X

X
Example 1 Consider the logic circuit shown in Fig. 2.3(a). Find the Boolean (@) (b)
difference with respect to x;. We have Figure 2.3 Circuit examples
26 2. Test Generation for Combinational Logic Circuits 2.2 Test Generation Techniques for Combinational Circuits 27

This means that a fault in x, will not cause the output to be in error, which In general, the conventional Boolean difference is not capable of deriving tests
indicates that the circuit is not really a function of x,; this can be verified by for all the internal nodes of a logic network. This is illustrated by the following
noting that the original output F(X) = x, - x, + x, - X3 = x,. example.
So far the Boolean difference method has been applied to derive tests for input
line faults; it can also be used for faults on lines internal to the circuit. Example 3 Given the logic network of Fig. 2.5, determine the tests for checking
Let a combinational circuit realize the function F(X), and let 4 be an internal all single-node faults.
wire in the circuit. Tests for / can be found by expressing F as a function of /, The network function is given by
F(xy.x5,...,x,,h), and h as a function of the inputs h(x,, x5, ..., X,). F = X000 + XyXoxs.
As an example, consider the circuit of Fig. 2.4 and find tests to detect s-a-0
and s-a-1 faults on h: The conventional Boolean differences of F with respect to x,, x,, and x5 are

F = xx; + x3x4 + 201y aF_

== g + Eoxs,
=k (o + o), dy, PR
e L),
G aF
et + XX,
dF __dh _ —dG _ dG dh
o S w®ua aF L
=R SR
el + B
dh - dxsx,
LN + xox) | dOoxs
+ Xoxa) 4
dh
D ® dh @ dh dh The test inputs resulting from these Boolean differences will check all input-line
1) @ 0@ 0 faults and are as follows:
= XaXa XXy = (Y XXXy = %X, Xy (s-a-0) 110 or 101
Tests for / s-a-0 are given by
X (s-a-1) 010 or 001
. 4F _ _
S=
Jp = sT
Xt == XX,
xnfi x; (s-a-0) 010 or 011
X3 (s-a-1) 000 or 001
and s-a-1 by
x5 (s-a-0) 011 or 001
— dF - - +. BoFaXy
el s = Foafars
-
B dh = XX XaTaXs = (f X3 (s-a-1) 010 or 000

One may select the test set (110, 010, 001) as the set of tests capable of
detecting the faults on primary input lines. However, this test set may or may not
Xy h
ot
Xy

X
Xy

X n

Figure 2.4 Circuit with an internal fault Figure 2.5 A network implementation for F = %,1,%; +
 —fi

28 2. Test Generation for Combinational Logic

Circuits
2.2 Test Generation Techniques for Combinational Circuits 29
be sufficient to detect all internal-node faults. To
develop a complete set of tests Proceeding in a similar manner, the partial Boolean difference associated with
that will detect both input line and internal-node
faults, it is necessary to find tests path x3—n—p—F is given by
that will exercise completely each and every path
connecting a primary input to
the primary output. This can be carried out by using
the partial Boolean difference dF _dF dp dn
technique [2.6]. dv; dp dndx
In general, a conventional Boolean difference expre
ssion may be formed by
tom.d
concatenating individual Boolean differences.
For example, if Z = f(y) and y =
f(), then T X0X) - (x + x)

dz _dz dy
da dy dx which yields the tests
where dZ # dx is termed the partial Boolean difference with respect to Tu% (010)
partial Boolean difference associated with the path x,~/-n—pF in Fig. v, The and
given by
2.5 is
Fooxs (01 1),
The Boolean difference method generates all tests for every fault in a circuit.
It is a complete algorithm and does not require any trial and error. However, the
Because
method is costly in computation time and memory requirements.

CL
s Xe-p) =7, 2.2.3 D-ALGORITHM

The D-algorithm is the first algorithmic method for generating tests for nonre-
p_d - -
an " an ™ T dundant combinational circuits [2.7]. If a test exists for detecting a fault, the
D-algorithm is guaranteed to find this test. Before the D-algorithm can be dis-
a_dg
a - dI( X3) =X
cussed in detail, certain new terms must be defined.

Singular Cover
dl
dx, The singular cover ofa logic gate is basically a compact version of the truth table.
it follows that Figure 2.6 shows the singular cover for a two-input NOR gate; Xs or blanks are
used to denote that the position may be either 0 or 1. Each row in the singular
cover is termed a singular cube. The singular cover of a network is just the

Therefore, the tests that will exercise the path

@« b ¢ ab e
x,—/—n—p—F are
B 001 0 0 1
X - xy+% or (0 10) ,,:DD—" 01 0 X 1 0
and 10 o0 1 x 0
(a) (b)
X; or (00 0).
=
&

Figure 2.6 (a) Truth table; (b) singular cover

30 2. Test Generation for Combinational Logic Circuits 2.2 Test Generation Techniques for Combinational Circuits 31
1 2 3 4 5 6 a b ¢
B a b c
1 ¢ 110 e
0 C X 01 ane 1 b b
0 G 0 X 1 anc b1 b
1 1 (a) (b)
0 0
Figure 2.8 () Singular covers of the NAND gate; (b) propagation D-cubes of the
X 0
NAND gate
0 0 0
X 1
0N0O=0NX=XNO0

=
X 1 1

I
Figure 2.7 (a) A circuit; (b) singular covers of cach gate in the circuit IN1=1NX=XnN1

XNX=X
set of singular covers of each of its gates on separate rows in the table. This is 1N0=D,
illustrated by the example in Fig. 2.7.
0on1=0D.
Propagation D-Cubes For example, the propagation D-cubes of the two-input NAND gate can be formed
D-cubes represent the input—output behavior of the good and the faulty circuit.
from its singular covers, as shown in Fig. 2.8,
The symbol D may assume only one value 0 or 1; D takes on the value opposite
to D: thatis, ifD = 1,D = 0,and ifD = 0, D = 1. The definitions of D and Primitive D-Cube of a Fault
D could be interchanged, but they should be consistent throughout the circuit. The primitive D-cube of a fault is used to specify the existence of a given fault.
Thus, all Ds in a circuit imply the same value (0 or 1), and all Ds will have the It consists of an input pattern that brings the influence of a fault to the utput of
opposite value. the gate. For example, if the output of the NOR gate shown in Fig. 2.6 is s-a-0,
The propagation D-cubes of a gate are those that cause the output of the gate the corresponding primitive D-cube of a fault is
to depend only on one or more of its specified inputs (and hence to propagate a
fault on these inputs to the output). The propagation D-cubes for a two-input
NOR gate are

a b ¢ Here, the D is interpreted as being a 1 if the circuit if fault-free and a 0 if the

fault is present. The primitive D-cubes for the NOR gate output s-a-1 are
0 D D
D 0 D a b c
D D D

[SIRT]
1 X
The propagation D-cubes 0DD and DOD indicate that if one of the inputs of the X 1
NOR gate is 0, the output is the complement of the other input; DDD propagates
multiple-input changes through the NOR gate. The primitive D-cube of any fault in a gate can be obtained from the singular
Propagation D-cubes can be derived from the singular cover, or by inspection.
covers of the normal and the faulty gates in the following manner:
To systematically construct propagation D-cubes, cubes with different output val- 1. Form the sinéular covers of the fault-free and the faulty gate. Let oy and
ues in a gate’s singular cover are intersected, using the following algebraic rules: «, be sets of cubes in the singular covers of the fault-free gate the output
°
 32 2. Test Generation for Combinational Logic Circuits 2.2 Test Generation Techniques for Combinational Circuits 33

coordinates of which are 0 and 1, respectively, and let B, and B, be the X 0

RC/Rv]
- — o =
corresponding sets in the singular covers of the faulty gate. 1 1
1 1
2. Intersect members of a; with members of B,, and members of e with
0 1

AR
members of B,. The intersection rules are similar to those used for propa-
10
gation D-cubes.

The primitive D-cubes of faults obtained from o, N Bo correspond to those inputs

D-Intersection
that produce a 1 output from the fault-free gate and a 0 output from the faulty
gate. The primitive D-cubes of faults obtained from oy N B, correspond to those Finally, we need to consider the concept of D-intersection, which provides the
inputs that produce a 0 output from the fault-free gate and a 1 output from the tool for building sensitized paths. This is first explained by a simple example.
faulty gate. Consider the simple circuit shown in Fig. 2.9. We attempt to generate a test for
the 2 s-a-0 fault, described by the D-cube of the fault:
Example 4 Consider a three-input NAND gate with input lines a, b, and ¢, and
output line d. The singular cover for the NAND gate is
a b c d

C, 0 X X 1 To transmit the D on line 4 through G, we must try and match, that is, intersect,
Ch X 0 X 1taq the D specification with one of the propagation D-cubes for G . Such a match is
C X X 0 1 possible if we use the propagation D-cube:
Co 1 1 1 0] a 3 4 5
Assuming the input line b is s-a-1, the singular cover for the faulty NAND gate
0o D D
is
This produces a full circuit D-cube:
1 2 3 4 5
Cy 0 X X 1
Cy X x o 1B o 1 0 D D
Cy 1 X 1 0} B
Thus, setting X, = 0, X, = 1, X5 = 0 will sensitize a path from line 2 through
Therefore, line 4 to line 5, and this will therefore test for inverse polarity faults on these
c,NcC X 1 D, Cyu,NCy=D connections.
1 1 D,
It is worth noting that intersection of the D-cube of the fault with the other
CoNCy=1 0 1 D, CyuyNCy=1 1 D D. single D-input propagation cube (DOD) would not be successful, because in the
first cube the status of line 4 is D, whereas in the second cube it is required to be
Cy,NCy=1 X D D,
The primitive D-cube of the b s-a-1 fault is 101D. The primitive D-cubes of all
stuck-at faults for the three-input NAND gate are

a b c d Fault

0O X X D ds-a-0
X 0 X » ds-a-0 Figure 2.9 Circuit to illustrate D-intersection
 R
R R RR R R R ——E——EEE EE=EC—

34 2. Test Generation for Combinational Logic Circuits 2.2 Test Generation Techniques for Combinational Circuits 35
set at 0. This is incompatible with the requirement. The full set of rules for the Table 2.1 Application of the D-Algorithm
D-cube intersection is as follows [2.8]:
G, G, G, G, Gs
LetA = (a,as ....a,)andB = (b, bo, .. -, b,) be D-cubes where a; and
1 2 5 3 4 6 3 5 7 2 6 8 7 8 9,
b;equal 0, 1, X, D, or D fori,j = 1,2, . .., n. The D-intersection, denoted by
AN B, is given by: X 1 0 10 D 0 X 1 0 D D 1 D D
1 Xx o 0 1 D X 0 1 D 0 D D 1 D
. XNa; =a,.
0 0 1 1 1. D 1 1 0 D D D D D D
2. If
a; # X and b; # X, then
Singular Primitive Singular Propagation Propagation
a; i
if b; = a;, cover D-cube of cover D-cube D-cube
{Qj’ otherwise. fault

Finally,A N B = @, the empty cube, if for any i, @, N b, = @ otherwise, 23456 8 9

ANB=aNb,...
. a, Nb,. D-drive operation
1. Select pdcffor 6 s-a-0 1o D B
For example,
2. Intersect with Gate4 propagation D-cube 01 0 D D
(1X1D0) N (XD1D0) = 1D1DO, 3. Intersect with Gate 5 propagation D-cube 01 0 D D D,
(N.B. G5 D-cube: polarity inverted)
(01DX1) N (00XD1) = 0BDD1 = @. End of D-drive
Now that singular cubes, primitive D-cubes of a fault, propagation D-cubes, and
Consistency operation _ |
D-intersections have been defined, we shall discuss the D-algorithm in detail.
1. Check line 7 is at 1 from G singular cover 01 00D D D
The first stage of the D-algorithm consists of choosing a primitive D-cube of
Set line5 at 0 7
the fault under consideration. The next step is to sensitize all possible paths from
2. Check line 5 is at 0 from G, singular cover; 01 00D D D
the faulty gate to a primary output of the circuit; this is done by successive set primary input 1 at 1
intersection of the primitive D-cube of the fault with the propagation D-cubes of
successor gates. The procedure is called the D-drive. The D-drive is continued
End of Consistency
until a primary output has a D or D. The final step is the consistency operation,
which is performed to develop a consistent set of primary input values that will
account for all lines set to 0 or 1 during the D-drive.
The application of the D-algorithm is demonstrated in Table 2.1 by deriving
a test for detecting the fault 6 s-a-0 in the circuit of Fig. 2.10. The test for line 6
s-a-0 is 1010.
Fortunately, no inconsistencies were encountered in the foregoing example.
When they are, one must seek a different path for propagating the fault to the
output. This is illustrated by deriving the test for 5 s-a-1 in the circuit diagram of
Fig. 2.11.
The singular covers and the propagation D-cube of the circuit are shown in
Tables 2.2 and 2.3, respectively. The blanks in the tables are treated as Xs while G
performing intersections. The D-drive along lines 5-8-9 and the consistency
Figure 2.10 Circuit under test
 36 2. Test Generation for Combinational Logic Circuits
| Table 2.3 Propagation D-Cubes
1 2 3 4 5 6 7 8 9

a 0 D D

c 0 D D
ate 2
e {m, D 0 =
D
Gate 3 tes D D
) Fa 1 D D
| Gate 4 {.e,/ D 1 b
Figure 211 Circuit under test : s " . N »
| ate i D 0 D
operations are shown in Table 2.4. Any D-cube that represents a partially formed ;a D 1 D
test during the D-drive is called a “‘test cube’” and is represented by 7c and a Gate 6 {h, 1 D D
superscript denoting the step at which it is obtained. The primitive D-cube of the
) fault is chosen as the initial test cube #c°.
¢ As can be seen from the table the consistency operation terminates unsuc- . . . .
y cessfully due to the null intersection ¢c*. If j is chosen instead of i, fc> becomes Table 2.4 D-Drive Along Lines 5-8-9 and Consistency Operations
undefined. We now attempt to D-drive along lines 5-7-9; this is shown in Table 1 2 3 4 5 6 7 8
N 7
Table 2.2 Singular Cover D-drive B
| 1 1 0 D
i 1 2 3 4 5 2 7 8 9 =i, | 0 b 0 5/ _
| i X 1 1 =1 Nk, 1 0 D 0 1 D | D
Gate 1 [f ! X . Consistency B
o o 0 I 0 o D 0 1 D D
d X 1 0 1 0 1 0 D 0 1 D D
Gate 2 e 1 X 0 [} 0 1 0 D 0 1 D D
f 0 0 1

| Gate 3 {; 0 (1) |
1 Table 2.5 D-Drive Along Lines 5-7-9 and Consistency
i 0 X 1 |
— {J P i | 1 2 3 4 5 6 7 8 9
£ 1 1 o D-drive
1 X 1 1 1 0 D
Gate 5 m 1 x 1 | 0 fy 1 0 1 D D
n 0 0 0 w0y 1 0 1 D D 1 D

ate ’q ; ! | =N 1 0 1 D 1 D 1 D
=1*Ng 1 0 0 1 D 1 D 1 D
38 2. Test Generation for Combinational Logic Circuits
START
2.5 with the consistency operations. It can be seen from Table 2.5 that the final
test cube is 7c*. Thus, 100 is a test for detecting the fault 5 s-a-1. 1
The D-algorithm generates a test for every fault in a circuit, if such a test Assign a binary
value to an unassigned
exists. It uses less computation time and less memory space, and hence it is more primary input
efficient than the Boolean difference method. It can also identify redundant faults
>
by “‘proving’’ that no corresponding test exist.

s
Determine applications
2.24 PODEM (Path-Oriented Decision-Making) of all primary inputs
PODEM is an enumeration algorithm in which all input patterns are examined as
tests for a given fault [2.8]. The search for a test continues till the search space
is exhausted or a test pattern is found. If no test pattern is found, the fault is
considered to be untestable. PODEM uses logic schematic diagrams in a manner
similar to the D-algorithm for deriving tests. The high-level description of Isatest
generated?
PODEM is shown in Fig. 2.12. The functions of each box in the diagram are as
explained below.

Box 1 Initially, all primary inputs (PIs) are at x; that is, they are unassigned.
One of the PIs is assigned a 0 or 1, and the P is recorded as an unflagged node
in a decision tree. Thus, the process is similar to branch in the context of branch Test
and bound algorithms. possible
with additional
Box 2 The value at the selected primary input is forward traced in conjunction assigned primary
inputs?
with x’s at the rest of the primary inputs, by using the five-valued logic 0, 1, x,
D, D.

Box 3 If the input pattern of Box 2 constitutes a test, then the test generation
process is completed. Is there
an untried
Box 4 The decision tree increases in depth; that is, one more primary input is EXIT-Untestable combination of values
assigned a 0 or 1 to check if it is possible to generate a test. Two possible situations fault on assigned primary
may arise while evaluating Box 4:
inputs?

1. The signal line (on which a stuck-at fault is assumed to be present) has
the same logic value as the stuck-at value.
Set untried
2. There is no signal path from an internal signal line to a primary output combination of values on
such that the line is at D or D and all-the lines are at x. assigned primary inputs
In the first case, the fault remains masked in the presence of the assigned input
values, whereas in the second case the input pattern cannot be a test, because Figure 212 PODEM algorithm (from P. Goel, **An implict enumeration algorithm to
D or D cannot be propagated to the output. Therefore, only when none of the generate fests for combinational circuits,”” IEEE Trans. Comput., March
foregoing situations occurs is a test possible with the current assignment of Pls. 1981. Copyright © 1981 IEEE. Reprinted with permission).

39
 T
T T Im——.

40 2. Test Generation for Combinational Logic Circuits

2.2 Test Generation Techniques for Combinational Circuits 41

Box 5 If all primary inputs have been assigned values and a test pattern is still
not found, it is checked whether an untried combination values at the inputs might
generate a test or not. Given —A fault
— An empty decision tree
It is clear from the preceding discussion that the decision tree is an ordered —AllPIsatX
list of nodes (Fig. 2.13) having the following features:

1. Each node identifies a current assignment of 0 or 1 to a primary input. P With assignments made |
2. The ordering reflects the sequence in which the current assignments have so far on the PIs |
been made. |
|
Make initial !
asignment |
(Lor0)toan
{AII primary inputs x, X, ..., —‘,.} unassigned |
are initially unknown | P, add
| unflagged |
[Initial assignment] node to |
I decision |
| tree =
X 1 =0 - . 5 Decision Yes | |
{Unussd alternative asslgnmenl} ree =
empty?,
9
By=1, Ho EXIT
7/
{ Node removed }@ Whether or not
alternative
Implications
ofall
assignment made assigned
=1/ X3 =0
Yes Last ) and
’7z
e N
N node For good and unassigned
flagged?, ° machines
failing A Pls
No test } No test }
backtrace backtrace ; " No
Make
alternative
. assignment
on
remove associated 10
last node PI; flag -
last node
. \
No test } No test }
backtrace backtrace
Figure 2.13 Decision tree in PODEM algorithm (from P. Goel, “‘An implict enumera-
tion algorithm to generate tests for combinational circuits,”” IEEE Trans.
Figure 2.14 Flowchart of PODEM algorithm (from P. Goel, **An implict enumeration
Comput., March 1981. Copyright © 1981 IEEE. Reprinted with permis- algorithm to generate tests for combinational circuits,”” IEEE Trans.
sion). Comput., March 1981. Copyright © 1981 IEEE. Reprinted with permis-
sion).
42 2. Test Generation for Combinational Logic Circuits
G (Fig. 2.14)
A node is flagged (indicated by a check mark inside the node) if its initial
assignment has been rejected and the alternative is being tried. When both as-
signment choices at a node are rejected, the associated node is removed and the
predecessor nodes assignment is also rejected. The assignment at the most re- No GUT Yes
cently selected Pl is rejected if no test can be formed with this assignment. The
rejection of a PI assignment results in a bounding of the decision tree, because it >— ¥
Output at

1
avoids the enumeration of subsequent assignments to as yet unassigned PIs. Find gate B
Figure 2.14 shows a more detailed description of the PODEM. The decision with D or D
tree of Box 5 can be implemented as a stack. An initial PI assignment pushes an on inputs, X on
output and
unflagged node onto the stack. The bounding of the decision tree is done by closest toa
popping the stack until an unflagged node is on the top of the stack (Box 2). The primary output
5 Input
assignment value to that node is complemented, and the node is flagged (Box 8). stuck fault
All nodes popped out of the stack are in effect removed from the decision tree, onG.UT?
and then associated Pls are set to x (Box 7). A new combination of values on the Initial
PIs is obtained by the bounding process, and it is evaluated (Boxes 3 and 4) as a objective
possible test pattern. The entire process is iteratively continued until a test pattern Found such
is found, or it is determined that a test is possible only with additional PI assign-
a gate?
Test
ments (Box 2), or the decision tree is empty (Box 9). The decision tree becomes not
empty only if the fault under consideration is untestable. Because it is desirable possble Set output of ~
to have least number of flagged nodes in a decision tree, the selection of a proper with present | yes G.U.T. opposite Faulted
assignments to stuck fault input at X?
initial assignment will reduce the test generation time. PODEM uses a two-step direction
process to choose a PI and its logic value assignment: X-path
‘from gate B to™\ Yes 3 /
1. Determine an initial output. [An objective is defined by a logic value (0
a primary Yes
or 1), referred to as objective logic level; the signal line on which the
Initial Initial Initial
objective level is desired is known as objective net.] objective objective objective
2. Given the initial objective, choose a PI and its logic value that has a good
likelihood of satisfying the initial objective.
) Disable selection Set output of Set G.U.T.g‘h";
output | | Setopl:‘me‘[’(‘)"“
faulted input
of gate B at Box 5 gae Bro 1(0) 01O
Initial Objective for determining
present initial 5115 s AND,
NOR (NAND, is an AND, NOR
Rt stuck
e fault
objective OR) gate SV
The flowchart of Fig. 2.15 shows the procedure to determine initial objectives.
7 8 9 10
As mentioned previously, all signal lines in a circuit are initially unspecified. A
stuck-at fault for which a test pattern is to be derived could be located either at
the output or at an input of a gate, so that the output of the gate assumes (D or
@ (Fig. 2.16)
D). As the algorithm continues, the gate under test (G.U.T.) may not have un-
specified value at its output due to the implications of assignments at primary Figure 215 Determination of initial objective (from P. Goel, *‘An implict enumera-
inputs (derived during the backtrace procedure). tion algorithm to generate tests for combinational circuits,” IEEE Trans.
As can be seen in Fig. 2.15, if the fault is assumed to be at the output of a Comput., March 1981. Copyright © 1981 IEEE, Reprinted with permis-
sion).
44 2. Test Generation for Combinational Logic Circuits
@(Fig 2.15)
gate that is still unspecified, then the output is set to a value opposite to the
assumed stuck-at value. On the other hand, if a fault is on input line of a gate,
and the faulty input line is already specified, the output line has to be assigned 1
Yes Is objective
if the gate is AND (or NOR), and 0 if the gate is NAND (or OR). If the output net fed by a primary
of the gate under test is specified, that is, D (D) not x, then the output is propagated input?
via other gates toward a primary output. This can be done via a gate closest to a 1
primary output. If such a gate is not found, the D or D cannot be propagated to
Found primary input. No {fed by gate 0}
the output, that is, a test pattern cannot be formed with the current assignment at Initial assignment is
the primary inputs. On the other hand, if a gate is available for propagating D or the current objective
Current (OR/NAND with current objective= 1]
D to the output, it will still be necessary to have a path consisting of all
xs (x-path) o objective level {AND/NOR with current objective = 0
through which the D or D from the gate under test can be propagated to a primary and type of gate driv ing_ >—————""""""7]
output. If an x-path cannot be found, the gate should not be considered for de-
objective net?
G (Fig. 2.14) :
termining the initial objective. However, if an x-path exists, the output of the gate
is set to 1 if it is AND (or NOR), and 0 if it is NAND (or OR).
{OR/NAND with current objective = 1}
{ AND/NOR with current objective = 0}
Next objective net is that Next objective net is that
Backtrace input of Q which (a) is at X, input of Q which (a) is at X, |
(b) is the hardest to control (b) is the easiest to rnn/\mV
The procedure for obtaining a primary input assignment given an initial objective (among inputs at X) primary (among inputs at X) from
4 inputs 5 primary inputs
is shown in Fig. 2.16; this is known as backtrace. The backtrace procedure traces
a signal path from an objective net with a given objective level (initial objective)
backward to a primary input. During the backtracking, each gate is assigned logic
values such that the desired initial objective at the objective net can be achieved.
If the objective net is driven by an OR or a NAND gate, and the current objective
level is 1 (0), the next objective net is the input line of the driving gate that is 15Q Yes
Mo aNAND/NOR
easiest (hardest) to control. Alternatively, if the objective net is driven by an AND gate?
ora NOR gate, and the current objective level is 0 (1), the input line ofthe driving 6
gate that is easiest (hardest) to control is selected as the next objective net.
Let us demonstrate the application of the PODEM algorithm by deriving a test
for detecting the fault « s-a-0 in the circuit of Fig. 2.17. The initial objective is Next objective level is the Next objective is the
same as the current complement of the current
to set the output of gate A to logic 1, that is, the objective logic level is 1 on net objective level objective level
5 (Box 3 in Fig. 2.15). By going through the backtrace procedure, it can be 7 3
determined that the next objective net is 1 (or 2) and the objective logic level is
0. Because net 1 is fed by the primary input x,, the current objective logic level, Repeat with current objective
namely, logic 0, is assigned to the primary input x, as shown here: (&) J teplaced by newy determined
next objective
123 456 78 9 10 11 12 Figure 2.16 Backtrace procedure (from P. Goel, *‘An implict enumeration algorithm
00X X X X X X X X X X X to generate tests for combinational circuits,”” IEEE Trans. Comput.,
March 1981. Copyright © 1981 IEEE. Reprinted with permission).

ar
e
e —— T ————

46 2. Test Generation for Combinational Logic

Circuits
2.2 Test Generation Techniques for Combinational Circuit
s 47

via the paths AGJ and AHJ; propagation along either path individ
ually will lead
to inconsistency. This feature of the D-algorithm can lead to
a waste of effort if
a given fault is untestable. The PODEM is more efficient than
the D-Algorithm
in terms of computer time required to generate tests for combina
tional circuits.

2.2.5 FAN (Fanout-Oriented Test Generation)

The FAN algorithm is in principle similar to PODEM, but

more efficient [2.9].
The efficiency is achieved by reducing the number of backtra
cks in the search
tree. Unlike PODEM, where the backtracking is done along
a single path, FAN
uses the concept of multiple backtrace. Before we show
how FAN deals with the
Figure 2.17 Circuit under test test generation problem for stuck-at faults, several terms
have to be defined. A
bound line is a gate output that is part of reconvergent
fan-out loop. A line that
Because x;x,x3x, = 0XXX is not a test for the fault, is not bound is considered to be free. A headline is a free line
a second pass through the that drives a gate
algorithm results in the assignment of primary input x,, which that is part of a reconvergent fan-out loop. In Fig. 2.18, for
sets up D as the example, nodes H, 1,
output of gate A: and J are bound lines, A through H are free lines, and G,
H, and F are headlines.
123 Because by definition headlines are free lines, they can be conside
45 11 12 6 7 8 9 10 red as primary
input lines and can always be assigned values arbitrarily. Thus,
00 XXDXXX during the back-
X XX X trace operation, if a headline is reached, the backtree stops;
it is not necessary to
Because the output of gate A, namely, net 3, is not X, reach a primary input to complete the backtrace.
it is necessary to find a
gate with D as its input, X as its output, and closer to FAN uses a technique called multiple backtrace to reduce
the primary output (Box 5, the number of back-
Fig. 2.15). Both gates G and H satisfy the requirements tracks that must be made during the search process. For exampl
. The selection of gate G e, in Fig. 2.19 if
and the subsequent initial objective (Box 8, Fig. 2.15) the objective is to set H at logic 1, PODEM would backtra
result in the assignment of ce along one of the
primary input x;: paths to the primary inputs. Suppose the backtrace is done
via the path H-E-C,
12345678910 which will set £ to 1. Because E is at 1, C will set to 0. Howeve
11 12 r, a 0 at C sets
Fto1,G t00,and H to 0. Because this assignment fails to
000XDT1X0XDX X achieve the desired
objective, the backtrace process is performed via another
X1X2X3x4 = 000X is not a test for the fault because the path, for example,
primary output is X. Gate H-G-F-C, and the desired goal can be achieved. Thus,
Jhas D on input net 10 and Xs on input nets 9 and 11. in PODEM, several
The initial objective is to backtracks may be necessary before the requirement of setting
set the objective net 12 to logic 1. The selection of net up a particular
9 as the next objective
results in the assignment of primary input x,:
12345678910

wx
11 12
0000D11000DTD
D
Thus, the test for the fault « s-a-0 is X134 = 0000.
Oa
The same test could be
found for the fault by applying the D-algorithm; howeve
r, the D-algorithm re-
quires substantial trial and error before the test is found.
This is because of the
variety of propagation paths and the attendant consistency F
operations that are J
required. For example, « s-a-0 has to be simultaneously propaga
ted to the output
Figure 2.18 Example circuit
 48 2. Test Generation for Combinationa
l Logic Circuits
2.2 Test Generation Techniques for Combinational Circuits 49

Delay fault
A rd

Figure 2.19 Multiple backtrace along H-E-C and H-G-

F-C
c
logic value on a line is satisfied. FAN
avoids this waste of computation time Figure 221 Circuit with a delay fault
backtracking along multiple paths to the by
fan-out point. For example, if multiple
backirace is done via both H—E—C and H-G fall signal at the input or output of a gate can affect an output of the circuit.
-F~C, the value at C can be set so The
that the value at # is justified. second pattern, known as a transition or propagation pattern, propagat
es the
We illustrate the application of the FAN effect of the activated transition to a primary output of the circuit. To
algorithm by deriving a test for the illustrate,
fault Z s-a-0 in Fig. 2.20. First, the value let us consider a delay (slow-to-rise) fault at the input A of the circuit
D is assigned to the line Z and the valu shown in
I 1o each of the inputs M and N. The e
initial objectives are to set M and N Fig. 2.21. The test for slow-to-rise fault consists of the initialization pattern
to 1. ABC
By the multiple backtrace, G and / are = 001, followed by the transition pattern ABC = 101. Similarly, the two pattern
assigned 1 (note that instead of G and
L could be assigned logic 1). Again, by the multiple 7,
backtrace, we have the final tests for a slow-to-fall delay fault at input A will be ABC = 101, 001.
Note that
objectivesA = 1,B = 1, and £ = 1, F = 1. The assignmentA = 1, the slow-to-rise fault (slow-to-fall fault) corresponds to a transient stuck-at-
J=1,M =1, and the assignment £ = B = 1 makes 0
1, F = | makes / = 1, N (stuck-at-1) fault.
assignments A =B =F = F = | const - Thus, the
itute a test for the fault
Z s-a-0. It is easy To identify the presence of a delay fault in a combinational circuit, the hard-
to see that if the first multiple backtrace ware model shown in Fig. 2.22 is frequently used in literature. The initializ
stopped at L, and the second multiple ation
backrace at H, the test for the fault will be pattern is first loaded into the input latches. After the circuit has stabilized, the
C=D=1.
transition pattern is clocked into the input latches by using C/. The output pattern
2.2.6 DELAY FAULT DETECTION of the circuit is next loaded into the output latches by setting the clock C2 at logic
1 for a period equal to or greater than the time required for the output pattern
A delay fault in a combinational logic to
circuit can be detected only by applying be loaded into the latch and stabilize. The possible presence of a delay fault
sequence of two test patterns. The first a is
pattern, known as an initialization patte confirmed if the output value is different from the expected value.
sets up the initial condition in a circuit rn,
so that the fault slow-to-rise or slow-to- Delay tests can be classified into two groups: nonrobust and robust [2.10].
A
delay fault is nonrobust if it can detect a fault in the path under consideration
provided there are no delay faults along other paths. For example, the input vector
pair (111, 101) can detect the slow-to-rise fault at ¢ in Fig. 2.23(a) as long as the

Input latches Combinational

circuit
=F Output latches [———">

[ c2
Figure 220 Circuit under test
Figure 222 Hardware model for delay fault testing
50 2. Test Generation for Combinational Logic Circuits 2.3 Detection of Multiple Faults in Combinational Logic Circuits
51
a— d a d having k lines there are 24 possible single faults, but a total of 3* — 1 multiple
b faults [2.18]. Hence, test generation for all possible multiple faults is impracti
cal
c f fe even for small networks. N
One approach that reduces the number of faults that need be tested in a network
is fault collapsing which uses the concept of equivalent faults [2.19,2.20]. For
b— e c example, an x-input logic gate can have 2x + 2 possible faults; however, for
(@) (b) certain input faults, a gate output would be forced into a state that is indistin-
Figure 2.23 The illustration of (a) Nonrobust test; (b) robust test guishable from one of the s-a-0/s-a-1 output faults. Thus, for an AND
gate any
input s-a-0 fault is indistinguishable from the output s-a-0 fault, and for an OR
gate any input s-a-1 fault is indistinguishable for the output s-a-1 fault. Such
path b—d~f does not have a delay fault. However, if there is a slow-to-fall fault faults are said to be equivalent. For a NAND (NOR) gate, the set of input s-a-0
atd, the output of the circuit will be correct for the input pair, thereby invalidating (s-a-1) faults and the set of output faults s-a-1 (s-a-0) are equivalent. Thus,
an
the test for the delay fault at e. Therefore, the test (111, 101) is nonrobust. x-input gate has to be tested for x + 2 logically distinct faults.
A delay test is considered to be robust if it detects the fault in a path indepen- A systematic approach that reduces the number of faults that have to be con-
dent of delay faults that may exist in other paths of the circuit. For example, let sidered in test generation is the process of fault folding [2.21]. The central
idea
us assume a slow-to-fall delay fault at d in the path a—c—d—f of the circuit shown behind the process is to form fault equivalence classes for a given circuit
by
in Fig. 2.23(b). The input vector pair (01, 11) constitutes a robust test for the folding faults toward the primary inputs. For nonreconvergent fan-out circuits,
delay fault because the output of any gate on the other paths does not change the folding operation produces a set of faults on primary inputs, and this set test
when the second vector of the input pair is applied to the circuit. Thus, any covers all faults in the circuit. For reconvergent fan-out circuits, the set of faults
possible delay fault in these paths will not affect the circuit output. Robust tests at the primary inputs, fan-out origins, and fan-out branches test cover all faults
do not exist for many paths in large circuits [2,11,2.12]. Significant research in in the circuit.
recent years has concentrated on the design of circuits that are fully testable for Another approach that results in a significant reduction in the number of faults
all path delay faults using robust tests [2.13-2.16]. to be tested uses the concept of prime faults [2.22]. The set of prime faults for
a
network can be generated by the following procedure:

2.3 Detection of Multiple Faults 1. Assign a fault to every gate input line if that is a primary input line or a
fan-out branch line. The fault is s-a-1 for AND/NAND gate inputs, and
in Combinational Logic Circuits
s-a-0 for OR/NOR gate inputs. Treat an inverter as a single input NAND/
NOR gate if its output is a primary output; otherwise, no fault value
One of the assumptions normally made in test generation schemes is that only a
should be assigned to an inverter input line.
single fault is present in the circuit under test. This assumption is valid only if
the circuit is frequently tested, when the probability of more than one fault oc- 2. Identify every gate that has faults assigned to all its input lines as a prime
curring is small. However, this is not true when a newly manufactured circuit gate. Assign a fault to the output line of every prime gate that does not
is tested for the first time. Multiple-fault assumption is also more realistic in the fan out. The fault is s-a-0 for AND/NOR gate outputs, and s-a-1 for
'VLSI environment, where faults occurring during manufacture frequently affect OR/NAND gate outputs.
several parts of a circuit. Some statistical studies have shown that multiple faults, The number of prime faults in a network is significantly fewer than the number
composed of at least six single faults, must be tested in a chip to establish its of single faults, because many single faults can be represented by equivalent
reliability [2.17]. multiple prime faults.
Designing multiple-fault detection tests for a logic network is difficult because In general, test sets derived under the single-fault assumption can detect a
of the extremely large number of faults that have to be considered. In a circuit large number of multiple faults. However, there is no guarantee that a multiple
 R
RREREREREREREEEES ESE=S—————Goeeee

52 2. Test Generation for Combinational Logic Circuits

References RXj

24 Schneider, R. R., “‘On the necessity to exam

ine D-chains in diagnostic test
generation,” IBM Jour. of Res. and Develop.,
114 (January 1967).
25 Sellers, F. F., M. Y. Hsiao, and C. L. Bearn
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the Boolean difference,”” IEEE Trans. Compu
t., 676-683 (July 1968).
2.6 Chiang, A. C., I S. Reed, and A. V. Banes
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Boolean difference and automated fault diagn
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189-195 (February 1972).
2.7 Roth, J. P., “‘Diagnosis of automata failur
Figure 2.24 Multilevel fan-out-free network es: A calculus and a method,”
IEEE Trans. Comput., 278-291 (July 1966)
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2.8 Goel, P., ““‘An implicit enumeration algor
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national logic circuits,”” IEEE Trans. Compu
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2.9 Fujiwara, H., and T. Shimono, **On the accel
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gorithms,” IEEE Trans. Comput., 1137-114
4 (December 1983).
askis ations between faults [2.23]. 2.10 Park, E., and M. Mercer, “‘Robust and nonro
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¢ r;:;l::zg erre lal [2.24] have shown that for a restricied fun-out-free network, in a combinational circuit,”” Proc. Intl. Test
Conf., pp. 1027-1034 (1987).
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atic test pattern generator for
network that does not contain the network of Fig. 2.24 (or its equivalent) as a the detection of path delay faults,”” Proc.
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network of Fig. 2.24 is the smallest fan-out-free network that can contain multiple Schulz, M. H., K. Fuchs and F. Fink, ‘‘Adv
anced automatic (est pattern
faults that are not detected by every single-fault detection test set [2.18]. generation techniques for path delay fault
s,” Proc. 19th IEEE In. Faulr-
Bossen and Hong [2.25] have shown that any multiple fflu]l in a network can Toler ant Computing Symp.. pp. 44-51 (June 1989).
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be represented by an equivalent fault, the components o.t whlch are fa{llls on n of robust testable CMOS
combinational logic circuits,”” Proc. 18th
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Symp., pp. 220-225 (June 1988).
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pm/r:g:?\i;a:.:; Fun: [226] have shown that the commonly used hypothesis S. Lusky, “‘Synthesis of delay fault
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2.16 Pramanick, A. K., and S. M. Reddy
, ““On the design of path delay fault
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Intl. Fault-Tolerant Comput-
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Automation Conf., 77-84 (1980). . logic networks,”” JEEE Trans. Comput., 1286
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ruary 1966). 1972).