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Switching Circuits and Logic Design_Lateral Entry-1

The document outlines the examination details for the 3rd semester B.Tech course on Switching Circuits and Logic Design, including instructions for answering questions from two parts. Part A consists of 15 short answer questions, while Part B includes two questions from a selection of three. Additionally, it provides a course outcome assessment scheme with corresponding cognitive levels and marks allocation.

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Subhankar Sahu
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6 views

Switching Circuits and Logic Design_Lateral Entry-1

The document outlines the examination details for the 3rd semester B.Tech course on Switching Circuits and Logic Design, including instructions for answering questions from two parts. Part A consists of 15 short answer questions, while Part B includes two questions from a selection of three. Additionally, it provides a course outcome assessment scheme with corresponding cognitive levels and marks allocation.

Uploaded by

Subhankar Sahu
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Registration No/ College Roll No:

B.Tech
Total Number of Pages: 04
ECE21201
3rd SEMESTER (REGULAR) EXAMINATION – 2021
Switching Circuits and Logic Design
BRANCH (S): CSIT/CSSE/CS/CC/DS/WT/CSFE/CSE/CE/AIML
Time: 3 Hours
Max Marks: 100
Answer all Questions from Part – A and Part – B
The figures in the right hand margin indicate marks.

PART – A

Q1. Answer the following questions: [2x15]


a) Convert the binary numbers (1110101.11)2 to decimal.
b) Convert binary 1010 into Gray code.
c) Find the 10's complement of the following 6-digit decimal number: 123900.
d) Deduce the following Boolean functions using three-variable maps:
F(x, y, z) =∑(0,1,5,7)
e) Simplify the following Boolean expressions using three-variable maps:
A'B + BC' + B'C'
f) Minimize the following Boolean expressions to a minimum number of literals:
ABC + A 'B + ABC
g) Express the complement of the following functions in sum of min terms: F(x, y, z) =
∏(0, 3, 6, 7)
h) Write down Demorgan’s Theorem.
i) Demonstrate the truth table of Half adder.
j) Write down the characteristic equation of JK Flip-Flop.
k) Demonstrate the characteristic table of T-flip flop
l) Differentiate between latch and Flip-Flop.
m) Write down the excitation table of JK Flip-Flop.
n) Discuss the algorithmic state machines with example
o) Express the meaning of condition box in Algorithmic state machine representation

PART-B
Q2. (Answer any Two) [7X2]
a) Given the two binary numbers X = 1010100 and Y = 1000011, perform the
subtraction
(a) X - Y
(b) Y - X using 2's complements method
b) Express the following functions in sum of min terms and product of max terms:
(a) F(A,B, C,D) = B'D + A'D + BD
(b) F(x, y, z) = (x y + z)(x z + y).
c) Design a multiplexer to implement the following Boolean function
F(A, B, C, D) = ∑(0,1,3,4,8,9,15)

Q3. (Answer any Two) [7X2]


a) Convert the following Boolean function in F(A, B, C, D) = ∑ (0, 1,2,5,8,9, 10)
(a) sum of products terms and
(b) Product of sum terms
b) Elucidate the race around condition in J-K flip-flop and How to overcome this
problem with labelled diagram
c) A sequential circuit has three flip-flops, A, B, C; one input, x; and one output, y. The
state diagram. The circuit is to be designed by treating the unused states
As don't-care conditions. The final circuit must be analyzed to ensure that it is self
correcting.
(a) Use D flip-flops in the design.
(b) Use JK flip-flops in the design.

Q4. (Answer any Two) [7X2]


a) Design a Full Subs tractor using two Half-substractors and
(a) OR gate and (b) Nand gate
b) Design a 3 bit-ripple down counter using JK Flip-Flop with labelled diagram
c) A sequential circuit with two D flip-flops, A and B; two inputs, x and y; and one
output. Z is specified by the following next-state and output equations:
A (t + 1) = x 'y + x A
B (t + 1) = x' B + x A
z=B
(a) Draw the logic diagram of the circuit.
(b) Derive the state table.
(c) Derive the state diagram.

Q5. (Answer the following) [7X2]


a) Convert a D flip-flop to a JK flip-flop by including input gates to the D flip-flop. The
gates needed for the input of the D flip-flop can be determined by means of
sequential-circuit design procedures. The sequential circuit to be considered will have
one D flip-flop and two inputs, J and K.
b) Design a counter with the following repeated binary sequence: 0,1,2,3,4,5,6. Use
JK flip-flops.

Q6. (Answer the following) [7X2]


a) Discuss the working of Serial in Serial out (SISO) Register.
b) Design a combinational circuit with three inputs and one output. The output is equal
to logic-l when the binary value of the input is less than 3. The output is logic-O
otherwise.

Course Outcome Assessment Scheme:

COS QUESTIONS TOTAL


MARKS

CO1 Identify Number systems, logic gates & different 1(a),(b),(c),(d),(e),(f), 32


coding techniques and apply the fundamental (g),(h),2
concepts of Boolean Algebra and K-Maps to (a),(b)
simplify Boolean Functions.

CO2 Demonstrate the operation of various combinational and sequential 1(i),(j),(l),(m),3(b),4(a),(b),5(a) 57


circuits ,(b),6(a),6(b)

CO3 Describe different state machines and understand the design of various 1(n),(o), 4(c),3(c) 18
systems using state machines

CO4 Read voluntarily to enhance the knowledge in switching circuits and logic 3(a),2(c) 14
BL Cognitive level Question Numbers Marks Allotted Percentage

1 Remember 1(h),1(j),1(m),1(o) 8 6.61

2 Understand 1(n) 2 1.6

3 Apply 1(i),1(k), 2(a),2(b), 18 14.87

4 Analyse 3(a),3(b), ,1(l),6(a) 23 19

5 Evaluate 1(a),1(b),1(c),1(d),1(e),1(f), 1(g) 14 11.57

6 Create 2(c),3(c),4(a),4(b),4(c),5(a),5(b),6(b) 56 46.20

Total

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