2021 PhotonIcs & Electromagnetics Research Symposium (PIERS), Hangzhou, China, 22 November

3.33 Tb/s All-optical AND Logic Gate Based on Two-dimensional

Photonic Crystals
Fariborz Parandin1 , Reza Kamarian2 , Mohamadreza Jomour2 ,
Ali Lalbakhsh3 , and Mohammad Alibakhshikenari4
1
2021 Photonics & Electromagnetics Research Symposium (PIERS) | 978-1-7281-7247-7/21/$31.00 ©2021 IEEE | DOI: 10.1109/PIERS53385.2021.9694950

Department of Electrical Engineering, Eslamabad-E-Gharb Branch

Islamic Azad University, Eslamabad-E-Gharb, Kermanshah, Iran
2
Department of Electrical Engineering, Kermanshah Branch
Islamic Azad University, Kermanshah, Iran
3
School of Engineering, Macquarie University, Sydney, NSW 2109, Australia
4
Electronic Engineering Department
University of Rome “Tor Vergata”, Via del Politecnico 1, Rome 00133, Italy

Abstract— This paper presents the design and simulation of an all-optical AND logic gate
based on a two-dimensional photonic crystal with a hexagonal lattice. The “0” logical state for
the input is the state where no light is emitted. The “0” logical state at the output is defined when
the light emitted is close to zero. The “1” logical state for input is when light is emitted and for
output is when the light emitted is close to the input source power. The PWE method was used
for frequency calculations and the band structure. The FDTD method was used to calculate the
field distribution within the structure. One of the important features of this structure is its very
small size, which makes it suitable for optical integrated circuits. Furthermore, the difference
between “0” and “1” logic states is large enough to decrease the probability of error in the output.
In addition, the proposed optical AND gate has a high bit rate, which is calculated as 3.33 Tb/s.
1. INTRODUCTION
Nowadays, several microwave circuits and components such as filters [1–11], diplexers [12–14],
power dividers [15–23], couplers [24, 25], and amplifiers [26–29] are designed based on microstrip
substrates. However, this technology has a limitation for the upper microwave frequency range
because of high losses at this frequency range. Therefore, other technologies such, photonic crystal
technology or optical structures should be used in this frequency range.
Photonic crystals are periodic structures used to fabricate optical devices. The main feature
of photonic crystals is their frequency band gap and their ability to control and conduct optic
waves. The frequency band-gap property has also found several applications in electromagnetics
engineering [30–35]. In photonic crystals, the refractive index varies periodically. These variations
can occur in one (1D), two (2D) or three dimensions (3D) [36–39]. Variations in the refractive index
prevent optic emissions in a range of wavelengths known as the photonic band gap (PBG) [40–43].
To control and conduct this group of optic waves, it is possible to make changes, called defects, in
the periodic structure along a specific route [44–46].
In recent years, attention has been focused on the design and application of integrated circuits,
where it is appropriate to use optical logic gates as basic tools. So far, many logical gates have been
designed and implemented using photonic crystals [47–55]. Optical gates are a suitable basis for
designing and constructing optical logic circuits and optical integrated circuits and play important
roles in optical communication networks because of their high speed and low loss of transmission [56–
64].
This study designs and simulates an all-optical AND logic gate based on a 2D photonic crystal
with a hexagonal lattice. The plane wave expansion (PWE) method was used to calculate the band
structure and determine the PBG of the structure. The finite difference time domain (FDTD)
method was employed to calculate field distributions in the input and output routes.
The field developed by the source is considered to be the basis when defining “0” and “1” logic.
If the optical power at a point is very small compared to the power of the light source, it can be
considered as “0” logical. But if it is close to the power of the input source, it can be considered a
logical “1”.
2. OPTICAL AND LOGIC GATE STRUCTURE
The proposed structure for AND logic gate includes a 2D photonic crystal with a hexagonal lattice.
The structure consists of dielectric rods with a square cross-section having a 3.4 refractive index,
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 2021 PhotonIcs & Electromagnetics Research Symposium (PIERS), Hangzhou, China, 22 November

where the background material is air with a refractive index of 1. The rods have a dimension of
0.2a, where a is the lattice constant equal to 0.58 µm. The sides of the rods, whose cross-sectional
area is square, are equal to 0.232 µm.
The unit cell is shown in Fig. 1(a) to calculate the band structure, and Fig. 1(b) shows the band
structure. The PWE method was used to calculate the band structure. In this simulation, the
perfect match layer (PML) boundary condition was used.

(a)

(b)

Figure 1: (a) Unit cell and (b) band structure.

Figure 2: Proposed structure for optical AND logic gate.

Three PBGs were developed and defined as normalized frequency (a/λ). The main PBG was
placed at a distance of 0.27 to 0.41 (equal to a wavelength of 1.3 to 2 µm). To conduct and control
the light using defects, the wavelength of the light source should be within the range of BG range;
thus, the wavelength chosen for simulation was 1.55 µm.
A combination of linear and point defects were used to conduct light in the structure. Two linear
defects in the input route conduct light, and three point defects in the output route couple the light
with the output. Logic “0” and “1” are defined as the magnitude of optical power distribution.
The optical power distribution as the input of the source is assumed to be logical “1” when they
are on and logical “0” when they are off. For the output, the “0” logical state occurs when the
optical power distribution emitted is much lower than the input and “1” logical state when it is
close to the input power.
Figure 2 illustrates the structure developed for realization of the AND gate. For better perfor-
mance of the logic gate, the size of the three rods has been changed. The sides of the two modified
rods on the upper and lower routes are considered to be a2 . Also, the sides of the rod, located at
the junction of the two paths, are selected to be a1 . The value of these parameters is selected as
a2 = 0.2a0 and a1 = 0.6a0 , where a0 is the side of the other rods.
When one input is “1” and the other is “0”, the light reflected from the output transfers to an
input route having an inactivated source. To reduce the intensity of light entering the input, two
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 2021 PhotonIcs & Electromagnetics Research Symposium (PIERS), Hangzhou, China, 22 November

additional routes were developed at the top of and below the structure so that the reflected light
is conducted to these routes.
3. SIMULATION AND RESULTS
The FDTD method, was used to simulate the optical power distribution for the proposed AND
gate. In this simulation, step index optic sources were used at the inputs. The light produced by
optic sources is emitted throughout the defect routes and conducted to the output route. When
both inputs are “0”, no optical power distribution exists, and the field at the output is logical “0”.
Fig. 3 represents optical power distribution when inputs are not equal (A = 0, B = 1 and A = 1,
B = 0).

(a) (b)

Figure 3: Distribution of optical power for: (a) A = 0, B = 1 and (b) A = 1, B = 0.

Figure 3 shows that when one input is “1” and the other is “0”, a very slight amount of light is
conducted to the output. In this case, the optical power distribution ratio of the output to input
is low, implying logical “0”. Some of the light power has leaked to the other input route, and some
is reflected in the same input path.
Figure 4 shows the simulation results of the optical power distribution in the structure when
the inputs equal “1” (A = B = 1).

Figure 4: Distribution of optical power for A = 1 and B = 1.

Figure 4 indicates that when both inputs are “1”, the greatest amount of light is transferred to
the output. Calculations indicate that the optical power distribution ratio of output to input here
is high, which is equivalent to logical “1”. These results are consistent with the performance of an
AND logic gate.
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 2021 PhotonIcs & Electromagnetics Research Symposium (PIERS), Hangzhou, China, 22 November

Figure 5 shows the optical power distribution at the output at different wavelengths for A =
B = 1 when the sides of square a1 and two squares a2 are changed.

(a) (b)

Figure 5: Optical power distribution at output for A = B = 1, in terms of wavelength for: (a) different a1
and (b) different a2 .

Figure 5 indicates for the wavelengths of 1.45 and 1.55 µm, the output is “1” for A = B =
1. The best power output will occur for a1 = (0.6 to 0.8)a0 and a2 = 0.2a0 for wavelengths of
approximately 1.55 µm, and a2 = (0.6 to 0.8)a0 for wavelengths of approximately 1.45 µm.
These results lead to the selection of a wavelength of 1.55 µm to simulate the structure. Fig. 6
shows the simulation results of this state for a1 = 0.6a0 and a2 = 0.2a0 at A = 0, B = 1 and A = 1,
B = 0 and A = B = 1.
Figure 6 shows that the best output for logic state “1” is approximately 1.54 µm. The optical
power distribution for the output is 1.05. In this case, the optical power distribution at output for
the state where one input is “0”, is 0.25. The probability of error in sensing logic in the output
decreases due to the significant interspace. At wavelength 1.55 µm, the optical power value of
logical “0” is about 0.18, and about 0.88 for logical “1”.
Table 1 lists the logical inputs, logical values and the output to input ratios of the optical power
and corresponding logical values.

Figure 6: Optical power distribution at output for Figure 7: Response time curve of the output for
different wavelengths and inputs for a1 = 0.6a0 and optical AND gate.
a2 = 0.2a0 .
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 2021 PhotonIcs & Electromagnetics Research Symposium (PIERS), Hangzhou, China, 22 November

Table 1: Truth table for the proposed AND gate.

Output Output
Input A Input B
(normalized power) (logical value)
0 0 0 0
0 1 0.18 0
1 0 0.18 0
1 1 0.88 1

The two left columns in Table 1 show the normalized optical power of the inputs. The remaining
columns are the relative values of the optical power distribution of the output to input and their
logical equivalents.
When the relative value is about 0.18, the output is logical “0” and when it is about 0.88 the
output is logical “1”. The simulation results show that the proposed structure can be used as an
optical AND gate for wavelengths in ranges of 1530 nm to 1555 nm. The normalized power for
several wavelengths is shown in Table 2.

Table 2: Normalized power for optical AND gate for several wavelengths.

Wavelength (nm) A=B=0 A = 0, B = 1 A = 1, B = 0 A=B=1

1530 0 0.18 0.18 0.87
1535 0 0.25 0.25 1
1540 0 0.26 0.26 1.05
1545 0 0.24 0.24 0.99
1550 0 0.18 0.18 0.88
1555 0 0.15 0.15 0.64
Logic output 0 0 0 1

Table 2 shows that the best performance of the proposed AND gate is close to the wavelength
of 1550 nm. At lower wavelengths, the amount of optical power increases, for the logic state “0”.
Also, at higher wavelengths, the amount of power decreases, for the “1” logic state. Fig. 7 shows
a graph of response time for the AND gate for A = B = 1. In this case the output is in “1” state
logic gate.
Figure 7 shows that the delay time in output is about 0.06 ps. To calculate the speed of the
proposed optical AND gate, a short optical pulse enters the input. The input is inactive after
steady-state its output. When the input was changed to zero, it takes some time for the output to
get to zero (response time). Results show that the response time for the proposed optical gate is
about 0.3 ps. Therefore, the bit rate for the optical AND gate is BR = T1 = 3.33 Tb/s.
4. CONCLUSION
The present study designs and simulates an all-optical AND logic gate based on 2D photonic crystals
with a hexagonal lattice composed of square rods in air. The PWE and FDTD methods were used
to simulate the band structure and calculate the optical power distribution, respectively. The logic
values “0” and “1” are determined based on the amount of optical power in each port. The sides of
the critical squares were changed and their effects were obtained for the output power. The results
correspond with AND logic gate performance. The proposed optical gate has a small size and high
speed and is suitable for use in high speed optical integrated circuits.
ACKNOWLEDGMENT
The authors would like to thank the Eslamabad-E-Gharb Branch, Islamic Azad University.
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