SN74HC74, SN54HC74

ZHCSOD3F – DECEMBER 1982 – REVISED JUNE 2021

具有清零和预设功能的 SNx4HC74 二路 D 类上升沿触发器

1 特性 3 说明
• 缓冲输入 SNx4HC74 器件包含两个具有异步预设和清零引脚的
• 宽工作电压范围：2V 至 6V 独立 D 类正边沿触发触发器。
• 宽工作温度范围：-40°C 至 +85°C
器件信息(1)
• 支持多达 10 个 LSTTL 负载的扇出
器件型号 封装 封装尺寸（标称值）
• 与 LSTTL 逻辑 IC 相比，可显著降低功耗
SN74HC74D SOIC (14) 8.70mm × 3.90mm
2 应用 SN74HC74DB SSOP (14) 6.50mm × 5.30mm
• 将瞬时开关转换为拨动开关 SN74HC74N PDIP (14) 19.30mm × 6.40mm
• 二等分或四等分时钟信号 SN74HC74NS SO (14) 10.20mm × 5.30mm
SN74HC74PW TSSOP (14) 5.00mm × 4.40mm
SN54HC74J CDIP (14) 21.30mm × 7.60mm
SN54HC74W CFP (14) 9.20mm × 6.29mm
SN54HC74FK LCCC (20) 8.90mm × 8.90mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。

xCLK C

xPRE
C

xQ

C
C
C
xD
C
C

C
xQ
C
xCLR

功能引脚分配

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCLS094
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Table of Contents
1 特性................................................................................... 1 8 Detailed Description......................................................10
2 应用................................................................................... 1 8.1 Overview................................................................... 10
3 说明................................................................................... 1 8.2 Functional Block Diagram......................................... 10
4 Revision History.............................................................. 2 8.3 Feature Description...................................................10
5 Pin Configuration and Functions...................................3 8.4 Device Functional Modes..........................................11
Pin Functions.................................................................... 3 9 Application and Implementation.................................. 12
6 Specifications.................................................................. 4 9.1 Application Information............................................. 12
6.1 Absolute Maximum Ratings........................................ 4 9.2 Typical Application.................................................... 12
6.2 ESD Ratings............................................................... 4 10 Power Supply Recommendations..............................15
6.3 Recommended Operating Conditions.........................4 11 Layout........................................................................... 16
6.4 Thermal Information....................................................5 11.1 Layout Guidelines................................................... 16
6.5 Electrical Characteristics - 74..................................... 5 11.2 Layout Example...................................................... 16
6.6 Electrical Characteristics - 54..................................... 6 12 Device and Documentation Support..........................17
6.7 Timing Requirements - 74...........................................6 12.1 Documentation Support.......................................... 17
6.8 Timing Requirements - 54...........................................7 12.2 支持资源..................................................................17
6.9 Switching Characteristics - 74.....................................7 12.3 Trademarks............................................................. 17
6.10 Switching Characteristics - 54...................................8 12.4 静电放电警告.......................................................... 17
6.11 Operating Characteristics..........................................8 12.5 术语表..................................................................... 17
6.12 Typical Characteristics.............................................. 8 13 Mechanical, Packaging, and Orderable
7 Parameter Measurement Information............................ 9 Information.................................................................... 17

4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision E (December 2015) to Revision F (June 2021) Page
• 更新至全新的数据表标准.................................................................................................................................... 1
• RθJA increased for the D (86 to 133.6 ℃/W), DB (96 to 107.7 ℃/W), NS (76 to 122.6 ℃/W), and PW (113 to
151.7 ℃/W) and decreased for the N package (80 to 61.9 ℃/W) ..................................................................... 5

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5 Pin Configuration and Functions

1CLR

2CLR
1CLR 1 14 VCC
1D NC VCC
1D 2 13 2CLR
1CLK 3 12 2D 3 2 1 20 19
1PRE 1CLK 4 18 2D
4 11 2CLK
1Q NC 5 17 NC
5 10 2PRE
1Q 2Q 1PRE 6 16 2CLK
6 9
GND 7 8 2Q NC 7 15 NC
1Q 8 14 2PRE
D, DB, N, NS, PW, J, or W Package 9 10 11 12 13

14-Pin SOIC, SSOP, PDIP, SO, TSSOP, CDIP, or CFP 1Q GND NC 2Q 2Q

Top View FK Package
20-Pin LCCC
Top View

Pin Functions
PIN
D, DB, N, I/O DESCRIPTION
NAME NS, PW, J, FK
or W
1 CLR 1 2 Input Channel 1, Clear Input, Active Low
1D 2 3 Input Channel 1, Data Input
1CLK 3 4 Input Channel 1, Positive edge triggered clock input
1 PRE 4 6 Input Channel 1, Preset Input, Active Low
1Q 5 8 Output Channel 1, Output
1Q 6 9 Output Channel 1, Inverted Output
GND 7 10 — Ground
2Q 8 12 Output Channel 2, Inverted Output
2Q 9 13 Output Channel 2, Output
2 PRE 10 14 Input Channel 2, Preset Input, Active Low
2CLK 11 16 Input Channel 2, Positive edge triggered clock input
2D 12 18 Input Channel 2, Data Input
2 CLR 13 19 Input Channel 2, Clear Input, Active Low
VCC 14 20 — Positive Supply
1, 5, 7, 11, 15,
NC — Not internally connected
17

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage –0.5 7 V
IIK Input clamp current(2) VI < –0.5 V or VI > VCC ±20 mA
IOK Output clamp current(2) VI < –0.5 V or VI > VCC ±20 mA
IO Continuous output current VO = 0 to VCC ±25 mA
Continuous current through VCC or GND ±50 mA
TJ Junction temperature(3) 150 °C
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) Guaranteed by design.

6.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/
±2000
JEDEC JS-001(1)
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC
±1500
specification JESD22-C101(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC Supply voltage 2 5 6 V
VCC = 2 V 1.5
VIH High-level input voltage VCC = 4.5 V 3.15 V
VCC = 6 V 4.2
VCC = 2 V 0.5
VIL Low-level input voltage VCC = 4.5 V 1.35 V
VCC = 6 V 1.8
VI Input voltage 0 VCC V
VO Output voltage 0 VCC V
VCC = 2 V 1000
Δt/Δv Input transition rise and fall rate VCC = 4.5 V 500 ns
VCC = 6 V 400
SN54HC00 –55 125
TA Operating free-air temperature °C
SN74HC00 –40 85

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6.4 Thermal Information

SN74HC74 SN54HC74
DB PW FK
THERMAL METRIC(1) D (SOIC) N (PDIP) NS (SO) J (CDIP) W (CFP) UNIT
(SSOP) (TSSOP) (LCCC)
14 PINS 14 PINS 14 PINS 14 PINS 14 PINS 14 PINS 14 PINS 20 PINS
Rθ Junction-to-ambient
133.6 107.7 61.9 122.6 151.7 N/A N/A N/A °C/W
JA thermal resistance
Rθ
Junction-to-case (top)
JC(to 89.0 57.4 49.7 81.8 79.4 15.05 14.65 5.61 °C/W
thermal resistance
p)

Rθ Junction-to-board
89.5 57.9 41.7 83.8 94.7 N/A N/A N/A °C/W
JB thermal resistance
Junction-to-top
ΨJT characterization 45.5 17.6 29.3 45.4 25.2 N/A N/A N/A °C/W
parameter
Junction-to-board
ΨJB characterization 89.1 57.2 41.4 83.4 94.1 N/A N/A N/A °C/W
parameter
Rθ Junction-to-case
JC(bo (bottom) thermal N/A N/A N/A N/A N/A N/A N/A N/A °C/W
t) resistance

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

6.5 Electrical Characteristics - 74

over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
Operating free-air temperature (TA)
PARAMETER TEST CONDITIONS VCC 25°C -40°C to 85°C UNIT
MIN TYP MAX MIN TYP MAX
2V 1.9 1.998 1.9
IOH = –20 µA 4.5 V 4.4 4.499 4.4
High-level VI = VIH 6V 5.9 5.999 5.9
VOH V
output voltage or VIL
IOH = –4 mA 4.5 V 3.98 4.3 3.84
IOH = –5.2 mA 6V 5.48 5.8 5.34
2V 0.002 0.1 0.1
IOL = 20 µA 4.5 V 0.001 0.1 0.1
Low-level output VI = VIH
VOL 6V 0.001 0.1 0.1 V
voltage or VIL
IOL = 4 mA 4.5 V 0.17 0.26 0.33
IOL = 5.2 mA 6V 0.15 0.26 0.33
Input leakage
II VI = VCC or 0 6V ±0.1 ±1 µA
current
VI = VCC
ICC Supply current IO = 0 6V 4 40 µA
or 0
Input
Ci 2 V to 6 V 3 10 10 pF
capacitance

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6.6 Electrical Characteristics - 54

over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
Operating free-air temperature (TA)
PARAMETER TEST CONDITIONS VCC 25°C –40°C to 85°C –55°C to 125°C UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX
2V 1.9 1.998 1.9 1.9
IOH = -20
4.5 V 4.4 4.499 4.4 4.4
µA
6V 5.9 5.999 5.9 5.9
VOH High-level VI = VIH or
V
output voltage VIL IOH = -6
4.5 V 3.98 4.3 3.84 3.7
mA
IOH = -7.8
6V 5.48 5.8 5.34 5.2
mA
2V 0.002 0.1 0.1 0.1
IOL = 20
4.5 V 0.001 0.1 0.1 0.1
µA
Low-level output VI = VIH or 6V 0.001 0.1 0.1 0.1
VOL V
voltage VIL
IOL = 6 mA 4.5 V 0.17 0.26 0.33 0.4
IOL = 7.8
6V 0.15 0.26 0.33 0.4
mA
Input leakage
II VI = VCC or 0 6V ±0.1 ±1 ±1 µA
current
VI = VCC or
ICC Supply current IO = 0 6V 2 20 40 µA
0
Input 2 V to
Ci 3 10 10 10 pF
capacitance 6V

6.7 Timing Requirements - 74

over operating free-air temperature range (unless otherwise noted)
Operating free-air temperature (TA)
VCC 25°C –40°C to 85°C UNIT
MIN TYP MAX MIN TYP MAX
2V 6 5
fclock Clock frequency 4.5 V 31 25 MHz
6V 0 36 0 29
2V 100 125
PRE or CLR low 4.5 V 20 25
6V 14 21
tw Pulse duration ns
2V 80 100
CLK high or low 4.5 V 16 20
6V 14 17
2V 100 125
Data 4.5 V 20 25
6V 17 21
tsu Setup time before CLK↑ ns
2V 25 30
PRE or CLR
4.5 V 5 6
inactive
6V 4 5
2V 0 0
th Hold time, data after CLK↑ 4.5 V 0 0 ns
6V 0 0

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6.8 Timing Requirements - 54

over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
Operating free-air temperature (TA)
VCC 25°C –40°C to 85°C –55°C to 125°C UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX
2V 6 5 4.2
fclock Clock frequency 4.5 V 31 25 21 ns
6V 0 36 0 29 0 25
2V 100 125 150
PRE or CLR
4.5 V 20 25 30
low
6V 14 21 25
tw Pulse duration ns
2V 80 100 120
CLK high or
4.5 V 16 20 24
low
6V 14 17 20
2V 100 125 150
Data 4.5 V 20 25 30
6V 17 21 25
tsu Setup time before CLK↑ ns
2V 25 30 40
PRE or CLR
4.5 V 5 6 8
inactive
6V 4 5 7
2V 0 0 0
th Hold time, data after CLK↑ 4.5 V 0 0 0 MHz
6V 0 0 0

6.9 Switching Characteristics - 74

over operating free-air temperature range (unless otherwise noted)
Operating free-air temperature (TA)
PARAMETER FROM TO VCC 25°C –40°C to 85°C UNIT
MIN TYP MAX MIN TYP MAX
2V 6 10 6
fmax 4.5 V 31 50 25 MHz
6V 36 60 29
2V 70 230 290
PRE or
Q or Q 4.5 V 20 46 58
CLR
6V 15 39 49
tpd Propagation delay ns
2V 70 175 220
CLK Q or Q 4.5 V 20 35 44
6V 15 30 39
2V 28 75 95
tt Transition-time Q or Q 4.5 V 8 15 19 ns
6V 6 13 16

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6.10 Switching Characteristics - 54

over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
Operating free-air temperature (TA)
PARAMETER FROM TO VCC 25°C –40°C to 85°C –55°C to 125°C UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX
2V 6 10 6 4.2
fmax 4.5 V 31 50 25 21 MHz
6V 36 60 29 25
2V 70 230 290 345
PRE or
Q or Q 4.5 V 20 46 58 69
CLR
6V 15 39 49 59
tpd Propagation delay ns
2V 70 175 220 250
CLK Q or Q 4.5 V 20 35 44 50
6V 15 30 39 42
2V 28 75 95 110
tt Transition-time Q or Q 4.5 V 8 15 19 22 ns
6V 6 13 16 19

6.11 Operating Characteristics

over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Power dissipation capacitance
Cpd No load 2 V to 6 V 35 pF
per gate

6.12 Typical Characteristics

TA = 25°C

7 0.3
2-V
6 4.5-V
0.25 6-V
VOH Output High Voltage (V)

VOL Output Low Voltage (V)

5
0.2
4
0.15
3
0.1
2

2-V 0.05
1 4.5-V
6-V
0 0
0 1 2 3 4 5 6 0 1 2 3 4 5 6
IOH Output High Current (mA) IOL Output Low Current (mA)

图 6-1. Typical output voltage in the high state 图 6-2. Typical output voltage in the low state (VOL)
(VOH)

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7 Parameter Measurement Information

• Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.
• The outputs are measured one at a time, with one input transition per measurement.

Test VCC
90% 90%
Point
Input
10% 10%
0V
From Output tr(1) tf(1)
Under Test
VOH
CL(1) 90% 90%
Output
10% 10%
VOL
A. CL= 50 pF and includes probe and jig capacitance. tr(1) tf(1)

图 7-1. Load Circuit A. tt is the greater of tr and tf.

图 7-2. Voltage Waveforms Transition Times
VCC tw
Clock VCC
50%
Input
0V Input 50% 50%
0V
tsu th
VCC 图 7-4. Voltage Waveforms Pulse Width
Data
50% 50%
Input
0V

图 7-3. Voltage Waveforms Setup and Hold Times

VCC
Input 50% 50%
0V
tPLH(1) tPHL(1)
VOH
Output 50% 50%
VOL
(1) (1)
tPHL tPLH
VOH
Output 50% 50%
VOL
A. The maximum between tPLH and tPHL is used for tpd.
图 7-5. Voltage Waveforms Propagation Delays

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8 Detailed Description
8.1 Overview
The SNx4HC74 devices contain two independent D-type positive-edge-triggered flip-flops with asynchronous
preset and clear pins for each.
8.2 Functional Block Diagram

xCLK C

xPRE
C

xQ

C
C
C
xD
C
C

C
xQ
C
xCLR

8.3 Feature Description

8.3.1 Balanced CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The drive capability of this device may
create fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the output power of the device to be limited to avoid damage due to over-
current. The electrical and thermal limits defined in the 节 6.1 must be followed at all times.
The SN74HC74 can drive a load with a total capacitance less than or equal to the maximum load listed in the 节
6.9 connected to a high-impedance CMOS input while still meeting all of the datasheet specifications. Larger
capacitive loads can be applied, however it is not recommended to exceed the provided load value. If larger
capacitive loads are required, it is recommended to add a series resistor between the output and the capacitor to
limit output current to the values given in the 节 6.1.
8.3.2 Standard CMOS Inputs
Standard CMOS inputs are high impedance and are typically modeled as a resistor from the input to ground in
parallel with the input capacitance given in the 节 6.5. The worst case resistance is calculated with the maximum
input voltage, given in the 节 6.1, and the maximum input leakage current, given in the 节 6.5, using ohm's law
(R = V ÷ I).
Signals applied to the inputs need to have fast edge rates, as defined by the input transition time in the 节 6.3 to
avoid excessive current consumption and oscillations. If a slow or noisy input signal is required, a device with a
Schmitt-trigger input should be used to condition the input signal prior to the standard CMOS input.

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8.3.3 Clamp Diode Structure

The inputs and outputs to this device have both positive and negative clamping diodes as depicted in 图 8-1.

CAUTION
Voltages beyond the values specified in the 节 6.1 table can cause damage to the device. The
recommended input and output voltage ratings may be exceeded if the input and output clamp-
current ratings are observed.

VCC
Device

+IIK +IOK

Input Logic Output

-IIK -IOK

GND

图 8-1. Electrical Placement of Clamping Diodes for Each Input and Output

8.4 Device Functional Modes

表 8-1. Function Table
INPUTS OUTPUTS
PRE CLR CLK D Q Q
L H X X H L
H L X X L H
L L X X H(1) H(1)
H H ↑ H H L
H H ↑ L L H
H H L X Q0 Q0

(1) This configuration is nonstable; that is, it does not persist when
PRE or CLR returns to its inactive (high) level.

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9 Application and Implementation

备注
以下应用部分中的信息不属于 TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

9.1 Application Information

Toggle switches are typically large, mechanically complex and relatively expensive. It is desirable to use a
momentary switch instead because they are small, mechanically simple and low cost. Some systems require a
toggle switch's functionality but are space or cost constrained and must use a momentary switch instead.
If the data input (D) of the D-type flip-flop is tied to the inverted output ( Q), then each clock pulse will cause the
value at the output (Q) to toggle. The momentary switch can be debounced and connected through a Schmitt-
trigger buffer to the clock input (CLK) to toggle the output.
This application also utilizes a power-on reset circuit to ensure that the output always starts in the LOW state
when power is applied.
9.2 Typical Application
VCC

R1
R2

C1

VCC

VCC
PRE D

R3 CLK Q

CLR Q Output
C2

图 9-1. Typical application schematic

9.2.1 Design Requirements

9.2.1.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the 节 6.3. The supply voltage sets the
device's electrical characteristics as described in the 节 6.5.
The supply must be capable of sourcing current equal to the total current to be sourced by all outputs of the
SN74HC74 plus the maximum supply current, ICC, listed in the 节 6.5. The logic device can only source or sink
as much current as it is provided at the supply and ground pins, respectively. Be sure not to exceed the
maximum total current through GND or VCC listed in the 节 6.1.
Total power consumption can be calculated using the information provided in CMOS Power Consumption and
Cpd Calculation.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.

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CAUTION
The maximum junction temperature, TJ(max) listed in the 节 6.1, is an additional limitation to prevent
damage to the device. Do not violate any values listed in the 节 6.1. These limits are provided to
prevent damage to the device.

9.2.1.2 Input Considerations

Unused inputs must be terminated to either VCC or ground. These can be directly terminated if the input is
completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used
for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into the
SN74HC74, as specified in the 节 6.5, and the desired input transition rate. A 10-kΩ resistor value is often used
due to these factors.
The SN74HC74 has standard CMOS inputs, so input signal edge rates cannot be slow. Slow input edge rates
can cause oscillations and damaging shoot-through current. The recommended rates are defined in the 节 6.3.
Refer to the 节 8.3 for additional information regarding the inputs for this device.
9.2.1.3 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the 节 6.5. Similarly, the ground voltage is
used to produce the output LOW voltage. Sinking current into the output will increase the output voltage as
specified by the VOL specification in the 节 6.5.
Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.
Refer to 节 8.3 for additional information regarding the outputs for this device.
9.2.1.4 Timing Considerations
The SN74HC74 is a clocked device. As such, it requires special timing considerations to ensure normal
operation.
Primary timing factors to consider:
• Maximum clock frequency: the maximum operating clock frequency defined in 节 6.7 is the maximum
frequency at which the device is guaranteed to function. This value refers specifically to the triggering
waveform, measuring from one trigger level to the next.
• Pulse duration: ensure that the triggering event duration is larger than the minimum pulse duration, as
defined in the 节 6.7.
• Setup time: ensure that the data has changed at least one setup time prior to the triggering event, as defined
in the 节 6.7.
• Hold time: ensure that the data remains in the desired state at least one hold time after the triggering event,
as defined in the 节 6.7.
9.2.2 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in the 节 11.
2. Ensure the capacitive load at the output is ≤ 70 pF. This is not a hard limit, however it will ensure optimal
performance. This can be accomplished by providing short, appropriately sized traces from the SN74HC74
to the receiving device.
3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum
output current from the 节 6.1 is not violated. Most CMOS inputs have a resistive load measured in
megaohms; much larger than the minimum calculated above.

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 13

Product Folder Links: SN74HC74 SN54HC74
SN74HC74, SN54HC74
ZHCSOD3F – DECEMBER 1982 – REVISED JUNE 2021 www.ti.com.cn

4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation
9.2.3 Application Curves
Voltage (2 V/div)

Voltage (2 V/div)
Vout Vout
Vin Vin

Time (100 Ps/div) Time (200 ms/div)

D001 D002

图 9-2. Waveform for non-debounced switch. 图 9-3. Waveform for debounced switch.

14 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: SN74HC74 SN54HC74

 SN74HC74, SN54HC74
www.ti.com.cn ZHCSOD3F – DECEMBER 1982 – REVISED JUNE 2021

10 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
节 6.3. Each VCC terminal should have a bypass capacitor to prevent power disturbance. A 0.1-μF capacitor is
recommended for this device. It is acceptable to parallel multiple bypass caps to reject different frequencies of
noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be
installed as close to the power terminal as possible for best results, as shown in 图 11-1.

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 15

Product Folder Links: SN74HC74 SN54HC74
SN74HC74, SN54HC74
ZHCSOD3F – DECEMBER 1982 – REVISED JUNE 2021 www.ti.com.cn

11 Layout
11.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used. Such unused input pins must not be left unconnected because the undefined
voltages at the outside connections result in undefined operational states. All unused inputs of digital logic
devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to
prevent them from floating. The logic level that must be applied to any particular unused input depends on the
function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic
function or is more convenient.
11.2 Layout Example
GND VCC

Recommend GND flood fill for

improved signal isolation, noise Bypass capacitor
reduction, and thermal dissipation placed close to the
0.1 F device
Unused input
tied to GND
Unused inputs
1CLR 1 14 VCC tied to VCC
1D 2 13 2CLR
1CLK 3 12 2D
1PRE 4 11 2CLK
1Q 5 10 2PRE
1Q 6 9 2Q
Avoid 90° Unused output
corners for GND 7 8 2Q left floating
signal lines

图 11-1. Example layout for the SN74HC74

16 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: SN74HC74 SN54HC74

 SN74HC74, SN54HC74
www.ti.com.cn ZHCSOD3F – DECEMBER 1982 – REVISED JUNE 2021

12 Device and Documentation Support

12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• HCMOS Design Considerations
• CMOS Power Consumption and CPD Calculation
• Designing with Logic
12.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.4 静电放电警告
静电放电 (ESD) 会损坏这个集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。

12.5 术语表
TI 术语表 本术语表列出并解释了术语、首字母缩略词和定义。

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 17

Product Folder Links: SN74HC74 SN54HC74
 PACKAGE OPTION ADDENDUM

www.ti.com 11-May-2023

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

5962-8405601VCA ACTIVE CDIP J 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8405601VC Samples
& Green A
SNV54HC74J
5962-8405601VDA ACTIVE CFP W 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8405601VD Samples
& Green A
SNV54HC74W
84056012A ACTIVE LCCC FK 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 84056012A Samples
& Green SNJ54HC
74FK
8405601CA ACTIVE CDIP J 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 8405601CA Samples
& Green SNJ54HC74J
8405601DA ACTIVE CFP W 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 8405601DA Samples
& Green SNJ54HC74W
JM38510/65302B2A ACTIVE LCCC FK 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/ Samples
& Green 65302B2A
JM38510/65302BCA ACTIVE CDIP J 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/ Samples
& Green 65302BCA
JM38510/65302BDA ACTIVE CFP W 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/ Samples
& Green 65302BDA
M38510/65302B2A ACTIVE LCCC FK 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/ Samples
& Green 65302B2A
M38510/65302BCA ACTIVE CDIP J 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/ Samples
& Green 65302BCA
M38510/65302BDA ACTIVE CFP W 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/ Samples
& Green 65302BDA
SN54HC74J ACTIVE CDIP J 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 SN54HC74J Samples
& Green
SN74HC74DBR ACTIVE SSOP DB 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC74 Samples

SN74HC74DBRG4 ACTIVE SSOP DB 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC74 Samples

SN74HC74DR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC74 Samples

SN74HC74DRG4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC74 Samples

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 11-May-2023

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN74HC74DT ACTIVE SOIC D 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC74 Samples

SN74HC74N ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HC74N Samples

SN74HC74NE4 ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HC74N Samples

SN74HC74NSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC74 Samples

SN74HC74PWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC74 Samples

SNJ54HC74FK ACTIVE LCCC FK 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 84056012A Samples
& Green SNJ54HC
74FK
SNJ54HC74J ACTIVE CDIP J 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 8405601CA Samples
& Green SNJ54HC74J
SNJ54HC74W ACTIVE CFP W 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 8405601DA Samples
& Green SNJ54HC74W

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 11-May-2023

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN54HC74, SN54HC74-SP, SN74HC74 :

• Catalog : SN74HC74, SN54HC74

• Automotive : SN74HC74-Q1, SN74HC74-Q1
• Enhanced Product : SN74HC74-EP, SN74HC74-EP
• Military : SN54HC74
• Space : SN54HC74-SP

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
• Military - QML certified for Military and Defense Applications
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application

Addendum-Page 3
 PACKAGE MATERIALS INFORMATION

www.ti.com 22-Jul-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74HC74DBR SSOP DB 14 2000 330.0 16.4 8.35 6.6 2.4 12.0 16.0 Q1
SN74HC74DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC74DRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC74DT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC74NSR SO NS 14 2000 330.0 16.4 8.45 10.55 2.5 12.0 16.2 Q1
SN74HC74PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74HC74PWR TSSOP PW 14 2000 330.0 12.4 6.85 5.45 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 22-Jul-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74HC74DBR SSOP DB 14 2000 356.0 356.0 35.0
SN74HC74DR SOIC D 14 2500 356.0 356.0 35.0
SN74HC74DRG4 SOIC D 14 2500 356.0 356.0 35.0
SN74HC74DT SOIC D 14 250 210.0 185.0 35.0
SN74HC74NSR SO NS 14 2000 356.0 356.0 35.0
SN74HC74PWR TSSOP PW 14 2000 356.0 356.0 35.0
SN74HC74PWR TSSOP PW 14 2000 366.0 364.0 50.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 22-Jul-2023

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
5962-8405601VDA W CFP 14 1 506.98 26.16 6220 NA
84056012A FK LCCC 20 1 506.98 12.06 2030 NA
8405601DA W CFP 14 1 506.98 26.16 6220 NA
JM38510/65302B2A FK LCCC 20 1 506.98 12.06 2030 NA
JM38510/65302BDA W CFP 14 1 506.98 26.16 6220 NA
M38510/65302B2A FK LCCC 20 1 506.98 12.06 2030 NA
M38510/65302BDA W CFP 14 1 506.98 26.16 6220 NA
SN74HC74N N PDIP 14 25 506 13.97 11230 4.32
SN74HC74N N PDIP 14 25 506 13.97 11230 4.32
SN74HC74NE4 N PDIP 14 25 506 13.97 11230 4.32
SN74HC74NE4 N PDIP 14 25 506 13.97 11230 4.32
SNJ54HC74FK FK LCCC 20 1 506.98 12.06 2030 NA
SNJ54HC74W W CFP 14 1 506.98 26.16 6220 NA

Pack Materials-Page 3
 GENERIC PACKAGE VIEW
FK 20 LCCC - 2.03 mm max height
8.89 x 8.89, 1.27 mm pitch LEADLESS CERAMIC CHIP CARRIER

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4229370\/A\

www.ti.com
 PACKAGE OUTLINE
J0014A SCALE 0.900
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

PIN 1 ID A 4X .005 MIN

(OPTIONAL) [0.13] .015-.060 TYP
[0.38-1.52]

1
14
12X .100
[2.54] 14X .014-.026
14X .045-.065 [0.36-0.66]
[1.15-1.65]
.010 [0.25] C A B

.754-.785
[19.15-19.94]

7 8

B .245-.283 .2 MAX TYP .13 MIN TYP

[6.22-7.19] [5.08] [3.3]

C SEATING PLANE

.308-.314
[7.83-7.97]
AT GAGE PLANE

.015 GAGE PLANE

[0.38]

0 -15 14X .008-.014

TYP [0.2-0.36]

4214771/A 05/2017

NOTES:

1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.

www.ti.com
 EXAMPLE BOARD LAYOUT
J0014A CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

(.300 ) TYP
[7.62] SEE DETAIL B
SEE DETAIL A

1 14

12X (.100 )
[2.54]

SYMM

14X ( .039)
[1]

7 8

SYMM

LAND PATTERN EXAMPLE

NON-SOLDER MASK DEFINED
SCALE: 5X

.002 MAX (.063)

[0.05] [1.6]
ALL AROUND METAL
( .063)
SOLDER MASK [1.6]
OPENING

METAL

SOLDER MASK .002 MAX

(R.002 ) TYP [0.05]
OPENING
[0.05] ALL AROUND
DETAIL A DETAIL B
SCALE: 15X 13X, SCALE: 15X

4214771/A 05/2017

www.ti.com
 MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38
0,65 0,15 M
0,22
28 15

0,25
0,09
5,60 8,20
5,00 7,40

Gage Plane

1 14 0,25

A 0°–ā8° 0,95
0,55

Seating Plane

2,00 MAX 0,05 MIN 0,10

PINS **
14 16 20 24 28 30 38
DIM

A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90

A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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