SN54HCT377, SN74HCT377

OCTAL D-TYPE FLIP-FLOPS

WITH CLOCK ENABLE
SCLS067D – NOVEMBER 1988 – REVISED MARCH 2003

D Operating Voltage Range of 4.5 V to 5.5 V D Contain Eight Flip-Flops With Single-Rail
D Outputs Can Drive Up To 10 LSTTL Loads Outputs
D Low Power Consumption, 80-µA Max ICC D Clock Enable Latched to Avoid False
D Typical tpd = 12 ns
Clocking

D ±4-mA Output Drive at 5 V

D Applications Include:
– Buffer/Storage Registers
D Low Input Current of 1 µA Max – Shift Registers
D Inputs Are TTL-Voltage Compatible – Pattern Generators
SN54HCT377 . . . J OR W PACKAGE SN54HCT377 . . . FK PACKAGE
SN74HCT377 . . . DW OR N PACKAGE (TOP VIEW)
(TOP VIEW)

CLKEN
VCC
1Q

8Q
1D
CLKEN 1 20 VCC
1Q 2 19 8Q
3 2 1 20 19
1D 3 18 8D 2D 4 18 8D
2D 4 17 7D 2Q 5 17 7D
2Q 5 16 7Q 3Q 6 16 7Q
3Q 6 15 6Q 3D 7 15 6Q
3D 7 14 6D 4D 8 14 6D
4D 8 13 5D 9 10 11 12 13
4Q 9 12 5Q

4Q

CLK
5Q
5D
GND
GND 10 11 CLK

description/ordering information
These devices are positive-edge-triggered D-type flip-flops. The ’HCT377 devices are similar to the ’HCT273
devices, but feature a latched clock-enable (CLKEN) input instead of a common clear.
Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the
positive-going edge of the clock (CLK) pulse if CLKEN is low. Clock triggering occurs at a particular voltage level
and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or
low level, the D input has no effect at the output. These devices are designed to prevent false clocking by
transitions at CLKEN.

ORDERING INFORMATION
ORDERABLE TOP-SIDE
TA PACKAGE†
PART NUMBER MARKING
PDIP – N Tube SN74HCT377N SN74HCT377N
–40°C to 85°C Tube SN74HCT377DW
SOIC – DW HCT377
Tape and reel SN74HCT377DWR
CDIP – J Tube SNJ54HCT377J SNJ54HCT377J
–55°C to 125°C CFP – W Tube SNJ54HCT377W SNJ54HCT377W
LCCC – FK Tube SNJ54HCT377FK
SNJ54HCT377FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

UNLESS OTHERWISE NOTED this document contains PRODUCTION Copyright  2003, Texas Instruments Incorporated
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

SN54HCT377, SN74HCT377
OCTAL D-TYPE FLIP-FLOPS
WITH CLOCK ENABLE
SCLS067D – NOVEMBER 1988 – REVISED MARCH 2003

FUNCTION TABLE
(each flip-flop)
INPUTS OUTPUT
CLKEN CLK D Q
H X X Q0
L ↑ H H
L ↑ L L
X L X Q0

logic diagram (positive logic)

1
CLKEN

11
CLK

C1 2
3 1Q
1D 1D

C1 5
4 2Q
2D 1D

C1 6
7 3Q
3D 1D

C1 9
8 4Q
4D 1D

C1 12
13 5Q
5D 1D

C1 15
14 6Q
6D 1D

C1 16
17 7Q
7D 1D

C1 19
18 8Q
8D 1D

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 SN54HCT377, SN74HCT377
OCTAL D-TYPE FLIP-FLOPS
WITH CLOCK ENABLE
SCLS067D – NOVEMBER 1988 – REVISED MARCH 2003

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 3)

SN54HCT377 SN74HCT377
UNIT
MIN NOM MAX MIN NOM MAX
VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V
VIH High-level input voltage VCC = 4.5 V to 5.5 V 2 2 V
VIL Low-level input voltage VCC = 4.5 V to 5.5 V 0.8 0.8 V
VI Input voltage 0 VCC 0 VCC V
VO Output voltage 0 VCC 0 VCC V
tt Input transition (rise and fall) times 500 500 ns
TA Operating free-air temperature –55 125 –40 85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
TA = 25°C SN54HCT377 SN74HCT377
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP MAX MIN MAX MIN MAX
IOH = –20 µA 4.5 V 4.4 4.499 4.4 4.4
VOH VI = VIH or VIL V
IOH = –4 mA 4.5 V 3.98 4.30 3.7 3.84
IOL = 20 µA 4.5 V 0.001 0.1 0.1 0.1
VOL VI = VIH or VIL V
IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33
II VI = VCC or 0 5.5 V ±0.1 ±100 ±1000 ±1000 nA
ICC VI = VCC or 0, IO = 0 5.5 V 8 160 80 µA
One input at 0.5 V or 2.4 V,
∆ICC‡ 5.5 V 1.4 2.4 3 2.9 mA
Other inputs at GND or VCC
4.5 V to
Ci 3 10 10* 10 pF
5.5 V
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

SN54HCT377, SN74HCT377
OCTAL D-TYPE FLIP-FLOPS
WITH CLOCK ENABLE
SCLS067D – NOVEMBER 1988 – REVISED MARCH 2003

timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
TA = 25°C SN54HCT377 SN74HCT377
VCC UNIT
MIN MAX MIN MAX MIN MAX
4.5 V 25 17 20
fclock
l k Clock frequency MHz
5.5 V 30 19 22
4.5 V 20 30 25
tw Pulse duration CLK high or low ns
5.5 V 18 28 23
4.5 V 12 18 15
Data
5.5 V 10 17 14
tsu ↑
Setup time before CLK↑ ns
4.5 V 12 18 15
CLKEN high or low
5.5 V 10 17 14
4.5 V 3 3 3
Data
5.5 V 3 3 3
th ↑
Hold time data after CLK↑ ns
4.5 V 5 5 5
CLKEN inactive or active
5.5 V 5 5 5

switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless

otherwise noted) (see Figure 1)
SN54HCT377
FROM TO
PARAMETER VCC TA = 25°C UNIT
(INPUT) (OUTPUT) MIN MAX
MIN TYP MAX
4.5 V 25 31 17
fmax MHz
5.5 V 30 37 19
4.5 V 15 30 45
tpd
d CLK Any ns
5.5 V 12 28 40
4.5 V 8 15 22
tt Any ns
5.5 V 6 14 21

switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless

otherwise noted) (see Figure 1)
SN74HCT377
FROM TO
PARAMETER VCC TA = 25°C UNIT
(INPUT) (OUTPUT) MIN MAX
MIN TYP MAX
4.5 V 25 31 20
fmax MHz
5.5 V 30 37 22
4.5 V 15 30 38
tpd
d CLK Any ns
5.5 V 12 28 35
4.5 V 8 15 19
tt Any ns
5.5 V 6 14 17

operating characteristics, TA = 25°C

PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance No load 30 pF

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 SN54HCT377, SN74HCT377
OCTAL D-TYPE FLIP-FLOPS
WITH CLOCK ENABLE
SCLS067D – NOVEMBER 1988 – REVISED MARCH 2003

PARAMETER MEASUREMENT INFORMATION

From Output Test 3V

High-Level
Under Test Point 1.3 V 1.3 V
Pulse
CL = 50 pF 0V
(see Note A) tw

Low-Level 3V
Pulse 1.3 V 1.3 V
LOAD CIRCUIT
0V

3V VOLTAGE WAVEFORMS
Input 1.3 V 1.3 V PULSE DURATIONS
0V
tPLH tPHL
VOH Reference 3V
In-Phase 90% 90% 1.3 V
Output 1.3 V 1.3 V Input
10% 10% V 0V
OL
tr tf tsu th
tPHL tPLH
Out-of- VOH Data 3V
90% 90% 2.7 V 2.7 V
Phase 1.3 V 1.3 V Input 1.3 V 1.3 V
10% 10% 0.3 V 0.3 V 0 V
Output VOL
tf tr tr tf

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES SETUP AND HOLD AND INPUT RISE AND FALL TIMES

NOTES: A. CL includes probe and test-fixture capacitance.

B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. The outputs are measured one at a time with one input transition per measurement.
D. For clock inputs, fmax is measured when the input duty cycle is 50%.
E. tPLH and tPHL are the same as tpd.

Figure 1. Load Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

 PACKAGE OPTION ADDENDUM

www.ti.com 30-Jul-2024

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN74HCT377DW OBSOLETE SOIC DW 20 TBD Call TI Call TI -40 to 85 HCT377

SN74HCT377DWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HCT377 Samples

SN74HCT377N ACTIVE PDIP N 20 20 RoHS & NIPDAU N / A for Pkg Type -40 to 85 SN74HCT377N Samples
Non-Green

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 30-Jul-2024

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 16-Apr-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74HCT377DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 16-Apr-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74HCT377DWR SOIC DW 20 2000 367.0 367.0 45.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 16-Apr-2024

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
SN74HCT377N N PDIP 20 20 506 13.97 11230 4.32

Pack Materials-Page 3
 PACKAGE OUTLINE
DW0020A SCALE 1.200
SOIC - 2.65 mm max height
SOIC

10.63 SEATING PLANE

TYP
9.97
PIN 1 ID 0.1 C
A
AREA
18X 1.27
20
1

13.0 2X
12.6 11.43
NOTE 3

10
11
0.51
20X
7.6 0.31 2.65 MAX
B 0.25 C A B
7.4
NOTE 4

0.33
TYP
0.10

0.25
SEE DETAIL A GAGE PLANE

1.27 0.3
0 -8 0.40 0.1

DETAIL A
TYPICAL

4220724/A 05/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.

www.ti.com
 EXAMPLE BOARD LAYOUT
DW0020A SOIC - 2.65 mm max height
SOIC

20X (2) SYMM

1
20

20X (0.6)

18X (1.27)

SYMM

(R0.05)
TYP

10 11

(9.3)

LAND PATTERN EXAMPLE

SCALE:6X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220724/A 05/2016
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DW0020A SOIC - 2.65 mm max height
SOIC

20X (2)
SYMM
1
20

20X (0.6)

18X (1.27)

SYMM

10 11

(9.3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:6X

4220724/A 05/2016
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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