EXP.

NO : 1A DATE: 13/01/2024
REALIZATION OF COMBINATIONAL LOGIC CIRCUITS-I
AIM:
To write a Verilog code to implement the Half Adder, Half Subtractor, Full Adder, and
Full Subtractor using data flow modeling and verify the result in MODELSIM Software.

ALGORITHM:
1. Start the program.
2. Declare the module with input and output ports.
3. Use the Boolean expressions with continuous assign statements, design the Half
Adder, Half Subtractor, Full Adder, and Full Subtractor using data flow modeling.
4. End the module.
5. Compile and Simulate the design in MODELSIM Software and Verify the
functionality of the design.
PROGRAM:

i)HALF ADDER
module halfadder(a,b,sum,carry);
input a,b;
output sum,carry;
assign sum=a^b;
assign carry=a&b;
endmodule

ii)HALF SUBTRACTOR
module halfsubtractor(a,b,diff,brw);
input a,b;
output diff, brw;
assign diff=a^b;
assign brw=(~a)&(b);
endmodule

iii)FULL ADDER
module fulladder(a,b,cin,sum,carry);
input a,b,cin;
output sum,carry;
assign sum=a^b^cin;
assign carry=(a&b)|(b&cin)|(cin&a);
endmodule

iv)FULL SUBTRACTOR
module fullsubtractor(a,b,bin,diff,bout);
input a,b,bin;
output diff,bout;
assign diff=a^b^bin;
assign bout=((~a)&b)|((~a)|b)&bin);
endmodule
SIMULATION OUTPUT:
i)HALF ADDER

ii)HALF SUBTRACTOR
iii)FULL ADDER

iv)FULL SUBTRACTOR
 Prelab(10)

Demo (20)

Record(10)

Viva(10)

Total(50)

RESULT:
Thus, the VERILOG code for Half Adder, Half Subtractor, Full Adder, and Full
Subtractor were implemented in dataflow modeling and the functionality of the design was
verified in the MODELSIM software.
EXP. NO: 1B DATE : 18/01/2024

AIM:
To write a Verilog code to implement the Half Adder,Half Subtractor,Full Adder,and Full
Subtractor in behavioral modeling using if-else statements and case statements and verify the
result in MODELSIM software.

ALGORITHM:
1. Start the program.
2. Declare the module with input and output ports.
3. Using if-else statements and case statements design half adder, half Subtractor, full
adder, and full Subtractor in behavioral modeling.
4. End the module.
5. Compile and simulate the design in MODELSIM software and verify the
functionality of the design.
PROGRAM:

i)HALF ADDER USING IF-ELSE STATEMENT

module ha_ifelse(a,b,sum,carry);
input a,b;
output reg sum,carry;
always@(a or b)
begin
if(a==0 && b==0)
begin
sum=0;
carry=0;
end
else if(a==0 && b==1)
begin
sum=1;
carry=0;
end
else if(a==1 && b==0)
begin
sum=1;
carry=0;
end
else if(a==1 && b==1)
begin
sum=0;
carry=1;
end
end
endmodule.

ii)HALF SUBTRACTOR USING IF-ELSE STATEMENT

module hs_ifelse(a,b,diff,borr);
input a,b;
output reg diff,borr;
always@(a or b)
begin
if(a==0 && b==0)
begin
diff=0;
borr=0;
end
else if(a==0 && b==1)
begin
diff=1;
 borr=1;
end
else if(a==1 && b==0)
begin
diff=1;
borr=0;
end
else if(a==1 && b==1)
begin
diff=0;
borr=0;
end
end
endmodule

iii)FULL ADDER USING IF-ELSE STATEMENT

module fa_ifelse(a,b,cin,sum,carry);
input a,b,cin;
output reg sum,carry;
always@(a or b or cin)
begin
if(a==0 && b==0 && cin==0)
begin
sum=0;
carry=0;
end
else if(a==0 && b==0 && cin==1)
begin
sum=1;
carry=0;
end
else if(a==0 && b==1 && cin==0)
begin
sum=1;
carry=0;
end
else if(a==0 && b==1 && cin==1)
begin
sum=0;
carry=1;
end
else if(a==1 && b==0 && cin==0)
begin
sum=1;
carry=0;
 end
else if(a==1 && b==0 && cin==1)
begin
sum=0;
carry=1;
end
else if(a==1 && b==1 && cin==0)
begin
sum=0;
carry=1;
end
else if(a==1 && b==1 && cin==1)
begin
sum=1;
carry=1;
end
end
endmodule

iv)FULL SUBTRACTOR USING IF-ELSE STATEMENT

module fs_ifelse(a,b,bin,diff,bout);
input a,b,bin;
output reg diff,bout;
always@(a or b or bin)
begin
if(a==0 && b==0 && bin==0)
begin
diff=0;
bout=0;
end
else if(a==0 && b==0 && bin==1)
begin
diff=1;
bout=1;
end
else if(a==0 && b==1 && bin==0)
begin
diff=1;
bout=1;
end
else if(a==0 && b==1 && bin==1)
begin
diff=0;
bout=1;
end
 else if(a==1 && b==0 && bin==0)
begin
diff=1;
bout=0;
end
else if(a==1 && b==0 && bin==1)
begin
diff=0;
bout=0;
end
else if(a==1 && b==1 && bin==0)
begin
diff=0;
bout=0;
end
else if(a==1 && b==1 && bin==1)
begin
diff=1;
bout=1;
end
end
endmodule

v)HALF ADDER USING CASE STATEMENT

module ha_case(a,sum,carry);
input [1:0]a;
output reg sum,carry;
always@(a)
begin
case(a)
2'b00:begin sum=0;carry=0;end
2'b01:begin sum=1;carry=0;end
2'b10:begin sum=1;carry=0;end
2'b11:begin sum=0;carry=1;end
endcase
end
endmodule

vi)HALF SUBTRACTOR USING CASE STATEMENT

module hs_case(a,diff,bout);
input [1:0]a;
output reg diff,bout;
always@(a)
begin
 case(a)
2’b00:begin diff=0;bout=0;end
2’b01:begin diff=1;bout=1;end
2’b10:begin diff=1;bout=0;end
2’b11:begin diff=0;bout=0;end
endcase
end
endmodule

vii)FULL ADDER USING CASE STATEMENT

module fa_case(a,b,cin,sum,cout);
input a,b;
input cin;
output reg sum,cout;
always@(a or b or cin)
begin
case({a,b,cin})
3’b000:begin sum=0;cout=0;end
3’b001:begin sum=1;cout=0;end
3’b010:begin sum=1;cout=0;end
3’b011:begin sum=0;cout=1;end
3’b100:begin sum=1;cout=0;end
3’b101:begin sum=0;cout=1;end
3’b110:begin sum=0;cout=1;end
3’b111:begin sum=1;cout=1;end
endcase
end
endmodule

viii)FULL SUBTRACTOR USING CASE STATEMENT

module fs_case(a,b,bin,diff,bout);
input a,b;
input bin;
output reg diff,bout;
always@(a or b or bin)
begin
case({a,b,bin})
3’b000:begin diff=0;bout=0;end
3’b001:begin diff=1;bout=1;end
3’b010:begin diff=1;bout=1;end
3’b011:begin diff=0;bout=1;end
3’b100:begin diff=1;bout=0;end
3’b101:begin diff=0;bout=0;end
3’b110:begin diff=0;bout=0;end
3’b111:begin diff=1;bout=1;end
endcase
end
endmodule
SIMULATION OUTPUT:

i)HALF ADDER USING IF-ELSE STATEMENT

ii)HALF SUBTRACTOR USING IF-ELSE STATEMENT

iii)FULL ADDER USING IF-ELSE STATEMENT

iv)FULL SUBTRACTOR USING IF-ELSE STATEMENT

v)HALF ADDER USING CASE STATEMENT

vi)HALF SUBTRACTOR USING CASE STATEMENT

vii)FULL ADDER USING CASE STATEMENT

viii)FULL SUBTRACTOR USING CASE STATEMENT

 Prelab(10)

Demo (20)

Record(10)

Viva(10)

Total(50)

RESULT:
Thus, the Half Adder, Half Subtractor, Full Adder,and Full Subtractor were implemented
using the behavioural modeling with if-else statement and case statement and the functionality of
the design was verified using MODELSIM software.
EXP. NO: 1C DATE : 25/01/2024
AIM:
To write a Verilog code to implement the Half Adder using NAND Gate, Half
Subtractor using NOR Gate, Full Adder, and Full Subtractor using NAND Gate in structural
modeling and verify the result in MODELSIM Software.

ALGORITHM:
1. Start the Program.
2. Declare the module with input and output ports for NAND and NOR gates.
3. Use the Boolean expressions with continuous assign statements, design NAND
gate, NOR gate.
4. End the module for NAND and NOR gates.
5. Compile and simulate the design of NAND and NOR gates in MODELSIM
Software and verify the functionality of the design.
6. Start the module for half adder, half subtractor, full adder, and full subtractor.
7. Declare the module with input and output ports.
8. Declare the required wires and registers.
9. Design the half adder, half subtractor, full adder, and full subtractor using NAND
and NOR gates in Structural modeling.
10. End the module for half adder, half subtractor, full adder, and full subtractor.
11. Compile and simulate the design of half adder,half subtractor,full adder,and full
subtractor in MODELSIM Software and verify the functionality of the design.
PROGRAM:
NAND GATE:
module nand1 (y,a,b);
input (a,b);
output y;
assign y = ~(a&b);
endmodule

i)HALF ADDER USING NAND Gate

module halfadd1(a,b,s,c);
input a,b;
output s,c;
wire w1, w2, w3;
begin
nand1 n1 (a,b,w1);
nand1 n2 (a,w1,w2);
nand1 n3 (b,w1,w3);
nand1 n4 (w2,w3,s);
nand1 n5 (w1,w1,c);
end
endmodule

NOR GATE:
module nor1 (y,a,b);
input a,b;
output y;
assing y = ~(a|b);
endmodule

ii)HALF SUBTRACTOR USING NOR Gate

module halfsub1(a,b,diff,borr);
input a,b;
output diff,borr;
wire w1, w2, w3;
begin
nor1 n1 (a,b,w1);
nor1 n2 (a,w1,borr);
nor1 n3 (w1,b,w2);
nor1 n4 (borr,w2,w3);
nor1 n5 (w3,w3,diff);
end
endmodule

iii)FULL ADDER USING NAND Gate

module fulladd1 (a,b,c,s,c1);
input a, b, c;
output s, c1;
 wire w1, w2, w3, w4, w5, w6, w7;
begin
nand1 n1 (a,b,w1);
nand1 n2 (a,w1,w2);
nand1 n3 (b,w1,w3);
nand1 n4 (w2,w3,w4);
nand1 n5 (w4,c1,w5);
nand1 n6 (w4,w5,w6);
nand1 n7 (w5,c1,w7);
nand1 n8 (w6,w7,s);
nand1 n9 (w5,w1,c1);
end
endmodule

iv)FULL SUBTRACTOR USING NAND Gate

module fullsub1 (a,b,bin,diff,bout);
input a, b, bin;
output diff,bout;
wire w1, w2, w3, w4, w5, w6, w7;
begin
nand1 n1 (a,b,w1);
nand1 n2 (a,w1,w2);
nand1 n3 (w1,b,w3);
nand1 n4 (w2,w3,w4);
nand1 n5 (w4,bin,w5);
nand1 n6 (w4,w5,w6);
nand1 n7 (w5,bin,w7);
nand1 n8 (w6,w7,diff);
nand1 n9 (w7,w3,bout);
end
endmodule
SIMULATION OUTPUT:

NAND GATE

i)HALF ADDER USING NAND GATE

NOR GATE

ii)HALF SUBTRACTOR USING NOR GATE

iii)FULL ADDER USING NAND GATE

iv)FULL SUBTRACTOR USING NAND GATE

 Prelab(10)

Demo (20)

Record(10)

Viva(10)

Total(50)

RESULT:
Thus the verilog code for Half Adder, Full Adder, Full Subtractor using NAND Gate
and Half Subtractor using NOR Gate were implemented in structural modeling and their
functionality was verified in MODELSIM Software.
EXP. NO : 1D DATE : 01/02/2024
REALIZATION OF COMBINATIONAL LOGIC CIRCUITS - II
AIM:
To write the Verilog code to implement the multiplexer using,
i) 2X1 MUX using behavioral modeling.
ii) 4X1 MUX using behavioral modeling.
iii) 8X1 MUX using 2X1 MUX and 4X1 MUX in structural modeling and verify the
result in ModelSim software.

ALGORITHM:
1.Start the program.
2.Declare the module of 2x1 multiplexer with input and output ports.
3.Use case statements, and design the 2×1 mux using behavioral modelling
4.End the module.
5.Compile and simulate the design in MODELSIM software and verify the
functionality of the design.
6.Declare the module of 4x1 multiplexer with input and output ports.
7.Use case statements, and design the 4×1 mux using behavioral modeling.
8.End the module.
9.Compile and simulate the design in MODELSIM software and verify the
functionality of the design.
10.Declare the module of 8x1 multiplexer with input and output ports.
11.Declare the required wires.
12.Design the 8×1 mux using 2x1 mux and 4x1 mux in structural modeling.
13.End the module.
14.Compile and simulate the design in MODELSIM software and verify the
functionality of the design.
PROGRAM:
i)2X1 MUX
module mux2x1 (i, s, y);
input [1:0]i;
input s;
output reg y;
always @ (i or s);
begin
case(s)
1’b0: begin y = i[0]; end
1’b1: begin y = i[1]; end
endcase
end
endmodule

ii)4X1 MUX
module mux4x1 (i, s, y);
input [3:0]i;
inupt [1:0]s;
output reg y;
always @ (i or s);
begin
case(s)
1’b00: begin y = i[0]; end
1’b01: begin y = i[1]; end
1’b10: begin y = i[2]; end
1’b11: begin y = i[3]; end
endcase
end
endmodule

iii)8X1 MUX USING 2X1 MUX AND 4X1 MUX

module mux2x1 (i, s, y);
input [1:0]i;
input s;
output reg y;
always @ (i or s);
begin
case(s)
1’b0: begin y = i[1]; end
1’b1: begin y = i[0]; end
endcase
end
endmodule
module mux4x1 (i, s, y);
input [3:0]i;
inupt [1:0]s;
output reg y;
always @ (a or s);
begin
case(s)
1’b00: begin y = i[0]; end
1’b01: begin y = i[1]; end
1’b10: begin y = i[2]; end
1’b11: begin y = i[3]; end
endcase
end
endmodule
module mux8x1(i0,i1,i2,i3,i4,i5,i6,i7,s2,s1,s0,y);
input i0,i1,i2,i3,i4,i5,i6,i7;
input s2,s1,s0;
output y;
wire w1,w2,w3;
mux4x1 m1(i7,i6,i5,i4,s1,s0,w1);
mux4x1 m2(i3,i2,i1,i0,s1,s0,w2);
mux2x1 m3(w1,w2,s2,w3);
assign y=w3;
endmodule
SIMULATION OUTPUT:

i)2X1 MUX

ii)4X1 MUX

iii)8X1 MUX
 Prelab(10)

Demo (20)

Record(10)

Viva(10)

Total(50)

RESULT:
Thus, the verilog code for
1. 2×1 MUX using behavioral modeling was implemented and the functionality of
the design was verified using MODELSIM software.
2. 4×1 MUX using behavioral modeling was implemented and the functionality of
the design was verified using MODELSIM software.
3. 8×1 MUX using 4x1 MUX and 2x1 MUX was implemented in structural
modeling and the functionality of the design was verified using MODELSIM
software.
EXP. NO : 1E DATE : 15/02/2024

REALIZATION OF COMBINATIONAL LOGIC CIRCUITS-III

AIM :
To write a Verilog code to implement the following,
i)8:3 encoder in behavioral modeling,
ii)3:8 decoder in behavioral modeling,
iii)4:16 decoder using two 3:8 decoders in structural modeling.

ALGORITHM:
1. Start the program for 8:3 encoder.
2. Declare the module of 8:3 encoder with input and output ports.
3. Use case statements, and design the 8:3 encoder using behavioral
modeling.
4. End the module for 8:3 encoder.
5. Compile and simulate the design in MODELSIM software and
verify the functionality of the design.
6. Start the program for 3:8 decoder.
7. Declare the module of 3:8 decoder with input and output ports.
8. Use if-else statements, and design the 3:8 decoder using
behavioral modeling.
9. End the module for 3:8 decoder.
10. Compile and simulate the design in MODELSIM software and
verify the functionality of the design.
11. Start the program for 4:16 decoder.
12. Declare the module of 4:16 with input and output ports.
13. Declare the required wires.
14. Design the 4:16 decoder using 3:8 decoder in structural
modeling.
15. End the module for 4:16 decoder.
16. Compile and simulate the design in MODELSIM software and
verify the functionality of the design.
PROGRAM:

i)8:3 ENCODER
module encoder_8_3(a,y);
input [7:0]a;
output reg [2:0]y;
always @ a
begin
case(a)
8'b00000001:begin y=3'b000;end
8'b00000010:begin y=3'b001;end
8'b00000100:begin y=3'b010;end
8'b00001000:begin y=3'b011;end
8'b00010000:begin y=3'b100;end
8'b00100000:begin y=3'b101;end
8'b01000000:begin y=3'b110;end
8'b10000000:begin y=3'b111;end
endcase
end
endmodule

ii)3:8 DECODER
module decoder_3_8(a,en,y);
input [2:0]a;
input en;
output reg [7:0]y;
always @ (*)
begin
if (en==0)
y=8'b00000000;
else if(en==1)
begin
if(a==3'b000)
y=8'b00000001;
else if(a==3'b001)
y=8'b00000010;
else if(a==3'b010)
y=8'b00000100;
else if(a==3'b011)
y=8'b00001000;
else if(a==3'b100)
y=8'b00010000;
else if(a==3'b101)
y=8'b00100000;
else if(a==3'b110)
y=8'b01000000;
else if(a==3'b111)
 y=8'b10000000;
end
end
endmodule

iii)4:16 DECODER
module decoder_4_16(a,y);
input [3:0]a;
output[15:0]y;
wire enbar;
wire [7:0]y_d2,y_d3;
assign enbar=~|a;
not d1(a[3],enbar);
decoder_3_8 d2(a[2:0],enbar,y_d2);
decoder_3_8 d3(a[2:0],~enbar,y_d3);
endmodule
SIMULATION OUTPUT:

i)8:3 ENCODER

ii)3:8 DECODER

iii)4:16 DECODER
 Prelab(10)

Demo (20)

Record(10)

Viva(10)

Total(50)

RESULT:
Thus,
i)8:3 encoder was implemented using behavioral modeling and the
functionality of the design was verified using MODELSIM software.
ii)3:8 decoder was implemented using behavioral modeling and the
functionality of the design was verified using MODELSIM software.
iii)4:16 decoder was implemented using two 3:8 decoders in
structural modeling and the functionality of the design was verified using
MODELSIM software.
EXP.NO : 1F DATE : 22/02/2024
AIM:
To write the Verilog code to implement the 8:3 priority encoder using case statement
in behavioral modelling and verify the functionality of the design.
ALGORITHM:
1.Start the program.
2.Declare the module with input and output ports.
3.Use case statement, and design the 8:3 Priority encoder using behavioral modeling.
4.End the module.
5.Compile and simulate the design in MODELSIM software and verify the
functionality of the design.
PROGRAM:
module priority_encoder(a,y);
input [7:0]a;
output reg [2:0]y;
always @(a)
begin
case (a)
8’b1xxxxxxx : y=3b’111;
8’b01xxxxxx : y=3b’110;
8’b001xxxxx : y=3b’101;
8’b0001xxxx : y=3b’100;
8’b00001xxx : y=3b’011;
8’b000001xx : y=3b’010;
8’b0000001x : y=3b’001;
8’b00000001 : y=3b’000;
endcase
end
endmodule
SIMULATION OUTPUT:
 Prelab(10)

Demo (20)

Record(10)

Viva(10)

Total(50)

RESULT:
Thus the Verilog code for 8:3 priority encoder was implemented using case
statement in behavioral modeling and the functionality of the design was verified using
MODELSIM software.
EXP. NO : 1G DATE : 22/02/2024
REALIZATION OF COMBINATIONAL LOGIC CIRCUIT -IV
AIM:
To write the Verilog code to implement the 4-bit Ripple Carry Adder using 1-bit Full
Adder in Structural Modeling and verify the functionality of the design in MODELSIM software.

ALGORITHM:
1. Start the program.
2. Declare the module with input and output ports for 1-bit full adder.
3. Use the Boolean expressions with continuous assign statement, design 1-bit full adder
using data flow modeling.
4. End the module for 1-bit full adder.
5. Compile and simulate the design of 1-bit full adder in MODELSIM software and verify
the functionality of the design.
6. Start the module for 4-bit ripple carry adder.
7. Declare the module with input and output ports for 4-bit ripple carry adder.
8. Declare the required wires for the 4-bit ripple carry adder.
9. Design the 4-bit Ripple Carry Adder using 1-bit Full Adder in structural modeling.
10. End the module for 4-bit ripple carry adder.
11. Compile and simulate the design for 4-bit ripple carry adder in MODELSIM software
and verify the functionality of the design.
PROGRAM:
module full_adder(a, b, cin, sum, cout);
input a, b, cin;
output sum, cout;
assign sum = a ^ b ^ cin;
assign cout = ((a & b) | (b & cin) | (a & cin));
endmodule
module rca_4bit(a, b, cin, s, cout);
input[3:0] a;
input[3:0] b;
input cin;
output[3:0] s;
output cout;
wire c1, c2, c3;
full_adder a1(a[0], b[0], cin, s[0], c1);
full_adder a2(a[1], b[1], c1, s[1], c2);
full_adder a3 (a[2], b[2], c2, s[2], c3);
full_adder a4 (a[3], b[3], c3, s[3], cout);
endmodule
SIMULATION OUTPUT:
 Prelab(10)

Demo (20)

Record(10)

Viva(10)

Total(50)

RESULT:
Thus, the Verilog code for 4-bit Ripple Carry Adder using 1-bit Full Adder was
implemented in structural modeling and the functionality of the design was verified in
MODELSIM software.
EXP. NO: 2 DATE: 29/02/2024
DESIGN OF 4-BIT ALU
AIM :
To write a Verilog code to implement the 4-bit ALU using behavioral modeling
and verify the functionality of the design in MODELSIM software.

ALGORITHM :
1. Start the program.
2. Declare the module with input and output ports.
3. Use the if-else statement and design the 4-bit ALU in behavioral modeling.
4. End the module.
5. Compile and simulate the design in MODELSIM software and verify the
functionality of the design.
PROGRAM :
module alu_4bit (
input [3:0] a,
input [3:0] b,
input [3:0] s,
output reg [7:0] y);
always @(*)
begin
if (s == 4'b0000)
y = a + b;
else if (s == 4'b0001)
y = a - b;
else if (s == 4'b0010)
y = a * b;
else if (s == 4'b0011)
y = a / b;
else if (s == 4'b0100)
y = a % b;
else if (s == 4'b0101)
y = a & b;
else if (s == 4'b0110)
y = a | b;
else if (s == 4'b0111)
y = a ^ b;
else if (s == 4'b1000)
y = ~(a & b);
else if (s == 4'b1001)
y = ~(a | b);
else if (s == 4'b1010)
y = ~(a ^ b);
else if (s == 4'b1011)
y = a << b;
else if (s == 4'b1100)
y = a >> b;
else if (s == 4'b1101)
y = (a == b) ? 4'b0001 : 4'b0000;
else if (s == 4'b1110)
y = (a != b) ? 4'b0001 : 4'b0000;
else if (s == 4'b1111)
y = ~a;
else
y = 4'b0000;
end
endmodule
SIMULATION OUTPUT :
 Prelab (10)

Demo (20)

Record (10)

Viva (10)

Total (50)

RESULT :
Thus, the Verilog code for 4-bit ALU was implemented using if-else statement in
behavioral modeling and the functionality of the design was verified using MODELSIM
software.