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SiC437

The SiC437 and SiC438 are microBUCK® DC/DC converters designed for input voltages ranging from 3 V to 28 V, offering adjustable output voltages down to 0.6 V and continuous currents of 12 A and 8 A respectively. They feature high efficiency with a peak efficiency of 97% and include robust protection mechanisms such as overvoltage and overcurrent protection. These converters are suitable for various applications including computing, consumer electronics, and industrial automation.

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0% found this document useful (0 votes)
3 views27 pages

SiC437

The SiC437 and SiC438 are microBUCK® DC/DC converters designed for input voltages ranging from 3 V to 28 V, offering adjustable output voltages down to 0.6 V and continuous currents of 12 A and 8 A respectively. They feature high efficiency with a peak efficiency of 97% and include robust protection mechanisms such as overvoltage and overcurrent protection. These converters are suitable for various applications including computing, consumer electronics, and industrial automation.

Uploaded by

flux.miao
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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SiC437, SiC438

www.vishay.com
Vishay Siliconix
3 V to 28 V Input, 8 A, 12 A
microBUCK® DC/DC Converter
FEATURES
• Versatile
- Operation from 3 V to 28 V input voltage
- Adjustable output voltage down to 0.6 V
- Scalable solution 8 A (SiC438), 12 A (SiC437),
and 24 A (SiC431)
LINKS TO ADDITIONAL RESOURCES - Output voltage tracking and sequencing with pre-bias
start up
Simulation Evaluation Design Tools - ± 1 % output voltage accuracy at -40 °C to +125 °C
Tool Boards
• Highly efficient
DESCRIPTION - 97 % peak efficiency
The SiC43x are synchronous buck regulators with
integrated high side and low side power MOSFETs. Its - 1 μA supply current at shutdown
power stage is capable of supplying 12 A (SiC437) and 8 A - 50 μA operating current not switching
(SiC438) continuous current at up to 1 MHz switching • Highly configurable
frequency. This regulator produces an adjustable output
voltage down to 0.6 V from 3 V to 28 V input rail to - Four programmable switching frequencies available:
accommodate a variety of applications, including 300 kHz, 500 kHz, 750 kHz, and 1 MHz
computing, consumer electronics, telecom, and industrial.
- Adjustable soft start and adjustable current limit
SiC437’s and SiC438’s architecture delivers ultrafast
transient response with minimum output capacitance and - Three modes of operation: forced continuous
tight ripple regulation at very light load. The device is conduction, power save (SiC43xB, SiC43xD), or
internally compensated and is stable with any capacitor. No ultrasonic (SiC43xA, SiC43xC)
external ESR network is required for loop stability purposes.
The device also incorporates a power saving scheme that • Robust and reliable
significantly increases light load efficiency. - Cycle-by-cycle current limit
The regulator family integrates a full protection feature set, - Output overvoltage protection
including output overvoltage protection (OVP), cycle by
cycle overcurrent protection (OCP) short circuit protection - Output undervoltage / short circuit protection with auto
(SCP) and thermal shutdown (OTP). It also has UVLO and a retry
user programmable soft start. - Power good flag and over temperature protection
The SiC437 and SiC438 are available in lead (Pb)-free power
enhanced MLP-44L package in 4 mm x 4 mm dimension. • Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
APPLICATIONS

• 5 V, 12 V, and 24 V input rail POLs

• Desktop, notebooks, server, and industrial computing

• Industrial and automation

• consumer electronics

TYPICAL APPLICATION CIRCUIT AND PACKAGE OPTIONS


Axis Title
100 10000
98
EN

PGOOD

INPUT 96
BOOT
3.0 VDC to 24 VDC
CBOOT 94
eff - Efficiency (%)

VIN VOUT = 5 V, L = 1.5 µH 1000


Phase
VOUT 92
2nd line
1st line
2nd line

VDD SiC43x SW 90
CIN VDRV GL
88
MODE1 VOUT VOUT = 1.2 V, L = 0.56 µH 100
86
MODE2 VFB
RUP
PGND
AGND

84
RDOWN COUT 82
80 10
0 1 2 3 4 5 6 7 8 9 10 11 12
IOUT - Output Current (A)
Fig. 1 - Typical Application Circuit Fig. 2 - Efficiency vs. Output Current
(VIN = 12 V, fsw = 500 kHz, Power Saving Mode)

S20-0679-Rev. D, 27-Aug-2020 1 Document Number: 75921


For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC437, SiC438
www.vishay.com
Vishay Siliconix
PIN CONFIGURATION

21 MODE1
20 MODE2

20 MODE2
21 MODE1
24 PHASE

24 PHASE
23 BOOT

23 BOOT
18 VOUT

18 VOUT
19 EN

19 EN
22 VIN

22 VIN
Pin 1 indicator

17 FB FB 17
VIN 1 16 AGND AGND 16 25 26 1 VIN
AGND VIN
VIN 2 15 VDD VDD 15 2 VIN
14 PGOOD PGOOD 14
PGND 3 13 PGND PGND 13 27 3 PGND
PGND
PGND 4 12 VDRV VDRV 12 4 PGND
11 GL GL 11

28
SW 5
SW 6
SW 7

SW 8
SW 9
GL 10

GL 10
SW 9
SW 8

SW 7
SW 6
SW 5
GL

Fig. 3 - SiC43x Pin Configuration

PIN DESCRIPTION
PIN NUMBER SYMBOL DESCRIPTION
1, 2, 22, 26 VIN Input voltage
3, 4, 13, 27 PGND Power signal return ground
5 to 9 SW Switching node signal; output inductor connection point
10, 11, 28 GL Low side power MOSFET gate signal
12 VDRV Supply voltage for internal gate driver. Connect a 2.2 μF decoupling capacitor to PGND
14 PGOOD Power good signal output; open drain
15 VDD Supply voltage for internal logic. Connect a 1 μF decoupling capacitor to AGND
16, 25 AGND Analog signal return ground
17 FB Output voltage feedback pin; connect to VOUT through a resistor divider network.
18 VOUT Output voltage sense pin
19 EN Enable pin
20 MODE2 Soft start and current limit selection; connect a resistor to VDD or AGND per table 2
21 MODE1 Operating mode and switching frequency selection; connect a resistor to VDD or AGND per table 1
23 BOOT Bootstrap pin; connect a capacitor to PHASE pin for HS power MOSFET gate voltage supply
24 PHASE Switching node signal for bootstrap return path

ORDERING INFORMATION
OPERATING
PART MAXIMUM LIGHT LOAD
PART NUMBER VDD, VDRV JUNCTION PACKAGE
MARKING CURRENT MODE
TEMPERATURE
SiC437AED-T1-GE3 SiC437A Ultrasonic
Internal
SiC437BED-T1-GE3 SiC437B Power saving
12 A
SiC437CED-T1-GE3 SiC437C Ultrasonic
External
SiC437DED-T1-GE3 SiC437D Power saving
-40 °C to +125 °C PowerPAK® MLP44-24L
SiC438AED-T1-GE3 SiC438A Ultrasonic
Internal
SiC438BED-T1-GE3 SiC438B Power saving
8A
SiC438CED-T1-GE3 SiC438C Ultrasonic
External
SiC438DED-T1-GE3 SiC438D Power saving

S20-0679-Rev. D, 27-Aug-2020 2 Document Number: 75921


For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC437, SiC438
www.vishay.com
Vishay Siliconix

ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)


ELECTRICAL PARAMETER CONDITIONS LIMITS UNIT
VIN Reference to PGND -0.3 to +30
VOUT Reference to PGND -0.3 to +22
VDD / VDRV Reference to PGND -0.3 to +6
SW / PHASE Reference to PGND -0.3 to +30
100 ns;
SW / PHASE (AC) -8 to +35
reference to PGND V
BOOT Reference to PGND -0.3 to +6
BOOT to SW -0.3 to +6
AGND to PGND -0.3 to +0.3
EN Reference to AGND -0.3 to +30
All other pins Reference to AGND -0.3 to +6
Temperature
Junction temperature TJ -40 to +150
°C
Storage temperature TSTG -65 to +150
Power Dissipation
Junction to ambient thermal impedance (RJA) 16
°C/W
Junction to case thermal impedance (RJC) 2
Maximum power dissipation Ambient temperature = 25 °C 7.75 W
ESD Protection
Human body model 4000
Electrostatic discharge protection V
Charged device model 1000

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating/conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS (all voltages referenced to GND = 0 V)


PARAMETER MIN. TYP. MAX. UNIT
Input voltage (VIN) (SiC43xA, SiC43xB) 4.5 - 28
Input voltage (VIN) (SiC43xC, SiC43xD) 3 - 28
Logic supply voltage, gate driver supply voltage (VDD, VDRV)
4.5 - 28
(SiC43xC, SiC43xD)
V
Enable (EN) 0 - 28
Input voltage (VIN), external supply on VDD / VDRV 3 - 28
0.9 x VIN
Output voltage (VOUT) 0.6 -
and < 20 V
Temperature
Recommended ambient temperature -40 to +105
°C
Operating junction temperature -40 to +125

S20-0679-Rev. D, 27-Aug-2020 3 Document Number: 75921


For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC437, SiC438
www.vishay.com
Vishay Siliconix

ELECTRICAL SPECIFICATIONS (VIN = 12 V, VEN = 5 V, TJ = -40 °C to +125 °C, unless otherwise stated)
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Power Supplies
VIN = 6 V to 28 V
VDD supply VDD 4.75 5 5.25
(SiC43xA, SiC43xB) V
VDD UVLO threshold, rising VDD_UVLO 3.3 3.6 3.9
VDD UVLO hysteresis VDD_UVLO_HYST - 300 - mV
Maximum VDD current IDD VIN = 6 V to 28 V 3 - - mA
VIN = 6 V to 28 V
VDRV supply VDRV 4.75 5 5.25 V
(SiC43xA, SiC43xB)
Maximum VDRV current IDRV VIN = 6 V to 28 V 50 - - mA
Input current IVIN Non-switching, VFB > 0.6 V - 50 120
μA
Shutdown current IVIN_SHDN VEN = 0 V - 0.5 3
Controller and Timing
TJ = 25 °C 597 600 603
Feedback voltage VFB m/V
TJ = -40 °C to +125 °C (1) 594 600 606
VFB input bias current IFB - 2 - nA
Minimum on-time tON_MIN. - 50 65 ns
tON accuracy tON_ACCURACY -10 - 10 %
On-time range tON_RANGE 65 - 2250 ns
Ultrasonic version (SiC43xA, SiC43xC) 20 - 30
Minimum frequency, skip mode fSW_MIN. kHz
Power save version (SiC43xB, SiC43xD) 0 - -
Minimum off-time tOFF_MIN. 205 250 305 ns
Power MOSFETs (SiC437)
High side on resistance RON_HS - 10.1 -
VDRV = 5 V, TA = 25 °C m
Low side on resistance RON_LS - 3.9 -
Power MOSFETs (SiC438)
High side on resistance RON_HS - 10.1 -
VDRV = 5 V, TA = 25 °C m
Low side on resistance RON_LS - 5.5 -
Fault Protections
Over current protection
IOCL_P TJ = -10 °C to +125 °C -20 - 20
(inductor valley current)
%
Output OVP threshold VOVP - 20 -
VFB with respect to 0.6 V reference
Output UVP threshold VUVP - -80 -
TOTP_RISING Rising temperature - 150 -
Over temperature protection °C
TOTP_HYST Hysteresis - 25 -
Power Good
VFB_RISING_VTH_OV VFB rising above 0.6 V reference - 20 -
Power good output threshold %
VFB_FALLING_VTH_UV VFB falling below 0.6 V reference - -10 -
Power good hysteresis VFB_HYST - 40 - mV
Power good on resistance RON_PGOOD - 7.5 15 
Power good delay time tDLY_PGOOD 15 25 35 μs
EN / MODE / Ultrasonic Threshold
EN logic high level VEN_H 1.6 - -
V
EN logic low level VEN_L - - 0.4
EN pull down resistance REN - 5 - M
Switching Frequency
fsw = 300 kHz - 51 55
fsw = 500 kHz 90 100 110
MODE1 (switching frequency) RMODE1 k
fsw = 750 kHz 180 200 220
fsw = 1000 kHz 450 499 550

S20-0679-Rev. D, 27-Aug-2020 4 Document Number: 75921


For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC437, SiC438
www.vishay.com
Vishay Siliconix

ELECTRICAL SPECIFICATIONS (VIN = 12 V, VEN = 5 V, TJ = -40 °C to +125 °C, unless otherwise stated)
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Soft Start
Connect RMODE2 between
1.8 3 4.2
MODE2 and AGND
Soft start time tss ms
Connect RMODE2 between
3.6 6 8.4
MODE2 and VDD
Over Current Protection - SiC437
IOCP = 18 A 450 499 550
IOCP = 14 A 180 200 220
MODE 2 (over current protection) RMODE2 k
IOCP = 9.7 A 90 100 110
IOCP = 5.4 A - 51 55
Over Current Protection - SiC438
IOCP = 12 A 450 499 550
IOCP = 9.3 A 180 200 220
MODE 2 (over current protection) RMODE2 k
IOCP = 6.5 A 90 100 110
IOCP = 3.6 A - 51 55
Note
(1) Guaranteed by design

FUNCTIONAL BLOCK DIAGRAM

VIN VOUT

VDRV Sync
Regulator
rectifier
Rr
BOOT
VDD UVLO

EN Enable

MODE1
PH
Over voltage Control
under voltage logic SW

SW VDRV
VOUT Ramp On time
generator
FB
EA

Zero GL
Rc
Reference crossing

Cc PGOOD
Soft start

Over Over
MODE2 current temperature Power good

AGND PGND

Fig. 4 - SiC43x Functional Block Diagram

S20-0679-Rev. D, 27-Aug-2020 5 Document Number: 75921


For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC437, SiC438
www.vishay.com
Vishay Siliconix
OPERATIONAL DESCRIPTION
Device Overview • Slow path is the error amplifier loop which ensures the DC
The SiC43x is high efficiency synchronous buck regulators component of the output voltage follows the internal
capable of delivering up to 8 A (SiC438) and 12 A (SiC437) accurate reference voltage
continuous current. The device has user programmable
L VOUT
switching frequency of 300 kHz, 500 kHz, 750 kHz, and
VIN SW VOUT
1 MHz. The control scheme delivers fast transient response
and minimizes the number of external components. Thanks Ramp RUP
FB
to the internal ramp information, no high ESR output bulk or Cinj2 Rinj Cinj1 Load
INPUT COUT
virtual ESR network is required for the loop stability. This PWM
Comp Error Amp RDOWN
device also incorporates a power saving feature that Ripple based
controller Ref.
enables diode emulation mode and frequency fold back as RCOMP
the load decreases. CCOMP
SiC43x
SiC43x has a full set of protection and monitoring features: AGND
• Over current protection in pulse-by-pulse mode
• Output over voltage protection Fig. 5 - VM-COT Block Diagram
• Output under voltage protection with device latch All components for RAMP signal generation and error
amplifier compensation required for the control loop are
• Over temperature protection with hysteresis
internal to the IC, see Fig. 5. In order for the device to cover
• Dedicated enable pin for easy power sequencing a wide range of VOUT operation, the internal RAMP signal
• Power good open drain output components (RX, CX, CY) are automatically selected
This device is available in MLP44-24L package to deliver depending on the VOUT voltage and switching frequency.
high power density and minimize PCB area. This method allows the RAMP amplitude to remain constant
throughout the VOUT voltage range, achieving low jitter and
Power Stage fast transient Response. The error amplifier internal
SiC43x integrates a high performance power stage with a compensation consists of a resistor in series with a
low on resistance and gate charge, high side and low capacitor (RCOMP, CCOMP).
side MOSFETs. The MOSFETs are optimized to achieve up Fig. 6 demonstrates the basic operational waveforms:
to 97 % efficiency.
The input voltage (VIN) can go up to 28 V and down to as low VRAMP
as 3 V for power conversion. For input voltages (VIN) below
4.5 V an external VDD and VDRV supply is required (SiC43xC,
SiC43xD). For input voltages (VIN) above 4.5 V only a single VCOMP
input supply is required (SiC43xA, SiC43xB).
Control Mechanism
SiC43x employs an advanced voltage - mode COT control PWM
Fixed on-time
mechanism. During steady-state operation, feedback
voltage (VFB) is compared with internal reference (0.6 V typ.) Fig. 6 - VM-COT Operational Principle
and the amplified error signal (VCOMP) is generated at the Light Load Condition
internal comp node. An internally generated ramp signal and To improve efficiency at light-load condition, SiC437,
VCOMP feed into a comparator. Once VRAMP crosses VCOMP, SiC438 provide a set of innovative implementations to
an on-time pulse is generated for a fixed time. During the eliminate LS recirculating current and switching losses. The
on-time pulse, the high side MOSFET will be turned on. internal zero crossing detector monitors SW node voltage to
Once the on-time pulse expires, the low side MOSFET will determine when inductor current starts to flow negatively. In
be turned on after a dead time period. The low side MOSFET power saving mode, as soon as inductor valley current
will stay on for a minimum duration equal to the minimum crosses zero, the device deploys diode emulation mode by
off-time (tOFF_MIN.) and remains on until VRAMP crosses turning off low side MOSFET. If load further decreases,
VCOMP. The cycle is then repeated. switching frequency is reduced proportional to load
Fig. 5 illustrates the basic block diagram for VM-COT condition to save switching losses while keeping output
architecture. In this architecture the following is achieved: ripple within tolerance. The switching frequency is set by the
controller to maintain regulation. In the standard power save
• The reference of a basic ripple control regulator is
replaced with a high again error amplifier loop mode, there is no minimum switching frequency (SiC43xB,
SiC43xD). For SiC43xA, SiC43xC, the minimum switching
• This establishes two parallel voltage regulating feedback
frequency that the regulator will reduce to is > 20 kHz as the
paths, a fast and slow path
part avoids switching frequencies in the audible range. This
• Fast path is the ripple injection which ensures rapid light load mode implementation is called ultrasonic mode.
correction of the transient perturbation

S20-0679-Rev. D, 27-Aug-2020 6 Document Number: 75921


For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC437, SiC438
www.vishay.com
Vishay Siliconix

MODE SETTING, OVER CURRENT PROTECTION, SWITCHING FREQUENCY, AND SOFT START
SELECTION
The SiC437, SiC438 has a low pin count, minimal external MODE1 and MODE2, are user programmable by connecting
components, and offers the user flexibility to choose soft a resistor from MODEx to VDD or AGND, allowing the user to
start times, current limit settings, switching frequencies and choose various operating modes. This is best explained in
to enable or disable the light load mode. Two MODE pins, the tables below.

TABLE 1 - MODE1 CONFIGURATION SETTINGS


OPERATION CONNECTION fSWITCH (kHz) RMODE1 (k)
300 51
500 100
Skip to AGND
750 200
1000 499
300 51
500 100
Forced CCM to VDD
750 200
1000 499

TABLE 2 - MODE2 CONFIGURATION SETTINGS


SOFT-START TIME CONNECTION ILIMIT (%) RMODE2 (k)
30 51
54 100
3 ms to AGND 78 200
100 % (18 A on SiC437)
499
100 % (12 A on SiC438)
30 51
54 100
6 ms to VDD 78 200
100 % (18 A on SiC437)
499
100 % (12 A on SiC438)

OUTPUT MONITORING AND PROTECTION FEATURES


Output Overcurrent Protection (OCP)
SiC437, SiC438 has pulse-by-pulse over current limit
control. The inductor current is monitored during low side
MOSFET conduction time through RDS(on) sensing. After a OCPthreshold
pre-defined blanking time, the inductor current is compared
with an internal OCP threshold. If inductor current is higher Iload
than OCP threshold, high side MOSFET is kept off until the Iinductor
inductor current falls below OCP threshold.
OCP is enabled immediately after VDD passes UVLO rising
threshold. GH

Fig. 7 - Over-Current Protection Illustration

S20-0679-Rev. D, 27-Aug-2020 7 Document Number: 75921


For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC437, SiC438
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Vishay Siliconix
Output Undervoltage Protection (UVP)
UVP is implemented by monitoring the FB pin. If the voltage
level at FB drops below 0.12 V for more than 25 μs, a UVP
event is recognized and both high side and low side
MOSFETs are turned off. After a duration equivalent to
20 soft start periods, the IC attempts to re-start. If the fault
condition still exists, the above cycle will be repeated.
UVP is active after the completion of soft start sequence.

Output Overvoltage Protection (OVP)


OVP is implemented by monitoring the FB pin. If the voltage
level at FB rising above 0.72 V, a OVP event is recognized
and both high side and low side MOSFETs are turned off.
Normal operation is resumed once FB voltage drop below
0.68 V. Fig. 8 - Pre-Bias Start-Up
OOVP is active after VDD passes UVLO rising threshold.
Power Good
Over-Temperature Protection (OTP) SiC437, SiC438 power good is an open-drain output. Pull
PGOOD pin high through a > 10 k resistor to use this signal.
OTP is implemented by monitoring the junction
Power good window is shown in the below diagram. If
temperature. If the junction temperature rises above 150 °C,
voltage on FB pin is out of this window, PGOOD signal is
a OTP event is recognized and both high side and low
de-asserted by pulling down to AGND. To prevent false
MOSFETs are turned off. After the junction temperature falls
triggering during transient events, PGOOD has a 25 μs
below 125 °C (25 °C hysteresis), the device restarts by
blanking time.
initiating a soft start sequence.

Sequencing of Input / Output Supplies


VFB_Rising_Vth_OV
SiC437, SiC438 have no sequencing requirements on its (typ. = 0.72 V) VFB_Falling_Vth_OV
supplies or enables (VIN, VDD, VDRV, EN). (typ. = 0.68 V)
Vref (0.6 V)
VFB_Falling_Vth_UV
Enable VFB (typ. = 0.54 V) VFB_Rising_Vth_UV
(typ. = 0.58 V)
The SiC437, SiC438 have an enable pin to turn the part on
and off.
Pull-high
Driving the pin high enables the device, while driving the pin PG
low disables the device.
The EN pin is internally pulled to AGND by a 5 M resistor to
Pull-low
prevent unwanted turn on due to a floating GPIO.
Fig. 9 - PGOOD Window Diagram

Pre-Bias Start-Up
In case of pre-bias startup, output is monitored through FB
pin. If the sensed voltage on FB is higher than the internal
reference ramp value, control logic prevents high side and 
low side MOSFETs from switching to avoid negative output 
voltage spike and excessive current sinking through low 
side MOSFET. 

S20-0679-Rev. D, 27-Aug-2020 8 Document Number: 75921


For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC437, SiC438
www.vishay.com
Vishay Siliconix
ELECTRICAL CHARACTERISTICS 
(VIN = 12 V, VOUT = 1.2 V, fsw = 500 kHz, COUT = 47 μF x 7, CIN = 10 μF x 6, unless otherwise noted)

Axis Title Axis Title


100 10000 100 10000
VOUT = 5 V, L = 1.5 µH
98 97
96 94
94 91 VOUT = 5 V, L = 1.5 µH

eff - Efficiency (%)


eff - Efficiency (%)

1000 1000
92 88

2nd line
2nd line

1st line
1st line

2nd line
2nd line

90 85
VOUT = 1.2 V, L = 0.56 µH
88 82
100 VOUT = 1.2 V, L = 0.56 µH 100
86 79
84 76
82 73
80 10 70 10
0 1 2 3 4 5 6 7 8 9 10 11 12 0.01 0.1 1
IOUT - Output Current (A) IOUT - Output Current (A)

Fig. 10 - SiC437 Efficiency vs. Output Current Fig. 13 - SiC437 Efficiency vs. Output Current
(VIN = 12 V, fsw = 500 kHz, Full Load) (VIN = 12 V, fsw = 500 kHz, Light Load)

Axis Title Axis Title


100 10000 100 10000
98 95
90
96 VOUT = 5 V, L = 1.5 µH
85
94 VOUT = 5 V, L = 1.5 µH
eff - Efficiency (%)

eff - Efficiency (%)

1000 80 1000
92 VOUT = 1.2 V, L = 0.56 µH
75
2nd line

2nd line
1st line

1st line
2nd line

2nd line

90 70
VOUT = 1.2 V, L = 0.56 µH 65
88
100 60 100
86
55
84
50
82 45
80 10 40 10
0 1 2 3 4 5 6 7 8 9 10 11 12 0.01 0.1 1
IOUT - Output Current (A) IOUT - Output Current (A)

Fig. 11 - SiC437 Efficiency vs. Output Current Fig. 14 - SiC437 Efficiency vs. Output Current
(VIN = 12 V, fsw = 500 kHz, Ultrasonic Mode, Full Load) (VIN = 12 V, fsw = 500 kHz, Ultrasonic Mode, Light Load)

Axis Title Axis Title


100 10000 100 10000
98 97
96 94
94 91
eff - Efficiency (%)

eff - Efficiency (%)

1000 1000
92 88
2nd line

2nd line
1st line

1st line
2nd line

2nd line

VOUT = 1.2 V, L = 0.56 µH


90 VOUT = 1.2 V, L = 0.56 µH 85
88 82
100 100
86 79
84 76
82 73
80 10 70 10
0 1 2 3 4 5 6 7 8 9 10 11 12 0.01 0.1 1
IOUT - Output Current (A) IOUT - Output Current (A)

Fig. 12 - SiC437 Efficiency vs. Output Current Fig. 15 - SiC437 Efficiency vs. Output Current
(VIN = 5 V, fsw = 500 kHz, Full Load) (VIN = 5 V, fsw = 500 kHz, Light Load)

S20-0679-Rev. D, 27-Aug-2020 9 Document Number: 75921


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ELECTRICAL CHARACTERISTICS 
(VIN = 12 V, VOUT = 1.2 V, fsw = 500 kHz, COUT = 47 μF x 7, CIN = 10 μF x 6, unless otherwise noted)

Axis Title Axis Title


100 10000 100 10000
98 VOUT = 5 V, L = 0.82 µH 97 VOUT = 5 V, L = 0.82 µH
96 94
94 91

eff - Efficiency (%)


eff - Efficiency (%)

1000 1000
92 VOUT = 3.3 V, L = 0.56 µH 88

2nd line

2nd line
1st line

1st line
2nd line

2nd line
90 85 VOUT = 3.3 V, L = 0.56 µH

88 82
VOUT = 1.2 V, L = 0.36 µH 100 100
86 79
VOUT = 1.2 V, L = 0.36 µH
84 76
82 73
80 10 70 10
0 1 2 3 4 5 6 7 8 9 10 11 12 0.01 0.1 1
IOUT - Output Current (A) IOUT - Output Current (A)

Fig. 16 - SIC437 Efficiency vs. Output Current Fig. 19 - SiC437 Efficiency vs. Output Current
(VIN = 12 V, fsw = 1 MHz, Full Load) (VIN = 12 V, fsw = 1 MHz, Light Load)

Axis Title Axis Title


100 10000 100 10000
98 92
84
96
76 VOUT = 5 V, L = 1.5 µH
94 VOUT = 5 V, L = 1.5 µH
eff - Efficiency (%)

eff - Efficiency (%)

1000 68 1000
92 60
2nd line

2nd line
1st line

2nd line
2nd line

1st line
90 52
88 44
VOUT = 1.2 V, L = 0.56 µH
100 36 100
86
28
84
20
82 12 VOUT = 1.2 V, L = 0.56 µH
80 10 4 10
0 1 2 3 4 5 6 7 8 9 10 11 12 0.001 0.01 0.1 1
IOUT - Output Current (A) IOUT - Output Current (A)

Fig. 17 - SiC437 Efficiency vs. Output Current Fig. 20 - SiC437 Efficiency vs. Output Current
(VIN = 12 V, fsw = 500 kHz, FCCM, Full Load) (VIN = 12 V, fsw = 500 kHz, FCCM, Light Load)

Axis Title Axis Title


100 10000 100 10000
VOUT = 5 V, L = 2.2 µH
96 VOUT = 5 V, L = 2.2 µH
95
92
90
VOUT = 3.3 V, L = 1.5 µH 88
eff - Efficiency (%)

eff - Efficiency (%)

1000 1000
85 84 VOUT = 3.3 V, L = 1.5 µH
2nd line

2nd line
1st line

1st line
2nd line

2nd line

80 80
VOUT = 1.2 V, L = 0.56 µH
75 76
100 100
72
70
68
VOUT = 1.2 V, L = 0.56 µH
65 64
60 10 60 10
0 1 2 3 4 5 6 7 8 9 10 11 12 0.01 0.1 1
IOUT - Output Current (A) IOUT - Output Current (A)

Fig. 18 - SiC437 Efficiency vs. Output Current Fig. 21 - SiC437 Efficiency vs. Output Current
(VIN = 24 V, fsw = 500 kHz, Full Load) (VIN = 24 V, fsw = 500 kHz, Light Load)

S20-0679-Rev. D, 27-Aug-2020 10 Document Number: 75921


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ELECTRICAL CHARACTERISTICS 
(VIN = 12 V, VOUT = 1.2 V, fsw = 500 kHz, COUT = 47 μF x 7, CIN = 10 μF x 6, unless otherwise noted)

Axis Title Axis Title


100 10000 100 10000
VOUT = 5 V, L = 2.2 µH VOUT = 5 V, L = 2.2 µH
98 97
96 94
94 91
eff - Efficiency (%)

eff - Efficiency (%)


VOUT = 3.3 V, L = 2.2 µH 1000 VOUT = 3 .3V, L = 2.2 µH 1000
92 88

2nd line

2nd line
1st line
2nd line

1st line
2nd line
90 85
VOUT = 1.2 V, L = 0.82 µH
88 82
100 VOUT = 1.2 V, L = 0.82 µH 100
86 79
84 76
82 73
80 10 70 10
0 1 2 3 4 5 6 7 8 0.01 0.1 1
IOUT - Output Current (A) IOUT - Output Current (A)

Fig. 22 - SiC438 Efficiency vs. Output Current Fig. 25 - SiC438 Efficiency vs. Output Current
(VIN = 12 V, fsw = 500 kHz, Full Load) (VIN = 12 V, fsw = 500 kHz, Light Load)

Axis Title Axis Title


100 10000 100 10000
VOUT = 5 V, L = 2.2 µH
98 95
90 VOUT = 5 V, L = 2.2 µH
96
85
94
eff - Efficiency (%)

eff - Efficiency (%)

VOUT = 3.3 V, L = 2.2 µH 1000 80 VOUT = 3.3 V, L = 2.2 µH 1000


92 75
2nd line

2nd line
1st line

1st line
2nd line

2nd line

90 70
VOUT = 1.2 V, L = 0.82 µH 65
88
100 60 VOUT = 1.2 V, L = 0.82 µH 100
86
55
84
50
82 45
80 10 40 10
0 1 2 3 4 5 6 7 8 0.01 0.1 1
IOUT - Output Current (A) IOUT - Output Current (A)

Fig. 23 - SiC438 Efficiency vs. Output Current Fig. 26 - SiC438 Efficiency vs. Output Current
(VIN = 12 V, fsw = 500 kHz, Ultrasonic Mode, Full Load) (VIN = 12 V, fsw = 500 kHz, Ultrasonic Mode, Light Load)

Axis Title Axis Title


100 10000 100 10000
98 97
96 94
94 91
eff - Efficiency (%)

eff - Efficiency (%)

1000 1000
92 88
2nd line

2nd line

2nd line
1st line

1st line
2nd line

VOUT = 1.2 V, L = 0.82 µH


90 85 VOUT = 1.2 V, L = 0.82 µH

88 82
100 100
86 79
84 76
82 73
80 10 70 10
0 1 2 3 4 5 6 7 8 0.01 0.1 1
IOUT - Output Current (A) IOUT - Output Current (A)

Fig. 24 - SiC438 Efficiency vs. Output Current Fig. 27 - SiC438 Efficiency vs. Output Current
(VIN = 5 V, fsw = 500 kHz, Full Load) (VIN = 5 V, fsw = 500 kHz, Light Load)

S20-0679-Rev. D, 27-Aug-2020 11 Document Number: 75921


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ELECTRICAL CHARACTERISTICS 
(VIN = 12 V, VOUT = 1.2 V, fsw = 500 kHz, COUT = 47 μF x 7, CIN = 10 μF x 6, unless otherwise noted)

Axis Title Axis Title


100 10000 100 10000
97 97
94 94
91 VOUT = 3.3 V, L = 1 µH 91

eff - Efficiency (%)


eff - Efficiency (%)

1000 1000
88 88 VOUT = 3.3 V, L = 1 µH

2nd line
2nd line

1st line
1st line

2nd line
2nd line

85 85
VOUT= 1.2 V, L = 0.47 µH
82 82
100 100
79 79
76 76
VOUT = 1.2 V, L = 0.47 µH
73 73
70 10 70 10
0 1 2 3 4 5 6 7 8 0.01 0.1 1
IOUT - Output Current (A) IOUT - Output Current (A)

Fig. 28 - SiC438 Efficiency vs. Output Current Fig. 31 - SiC438 Efficiency vs. Output Current
(VIN = 12 V, fsw = 1 MHz, Full Load) (VIN = 12 V, fsw = 1 MHz, Light Load)

Axis Title Axis Title


100 10000 100 10000
VOUT = 5 V, L = 2.2 µH VOUT = 5 V, L = 2.2 µH
98 88
96
76
94
eff - Efficiency (%)
eff - Efficiency (%)

VOUT = 3.3 V, L = 2.2 µH 1000 1000


92 64 VOUT = 3.3 V, L = 2.2 µH

2nd line
2nd line

1st line
1st line

2nd line
2nd line

90 52
88 VOUT = 1.2 V, L = 0.82 µH 40
100 100
86
28
84
82 16
VOUT = 1.2 V, L = 0.82 µH
80 10 4 10
0 1 2 3 4 5 6 7 8 0.001 0.01 0.1 1
IOUT - Output Current (A) IOUT - Output Current (A)

Fig. 29 - SiC438 Efficiency vs. Output Current Fig. 32 - SiC438 Efficiency vs. Output Current
(VIN = 12 V, fsw = 500 kHz, FCCM, Full Load) (VIN = 12 V, fsw = 500 kHz, FCCM, Light Load)

Axis Title Axis Title


100 10000 100 10000
VOUT = 5 V, L = 3.3 µH
95 96
VOUT = 5 V, L = 2.2 µH
92
90
VOUT = 3.3 V, L = 2.2 µH 88
eff - Efficiency (%)

eff - Efficiency (%)

1000 1000
85 84
2nd line

2nd line

VOUT = 3.3 V, L = 2.2 µH


1st line
2nd line

1st line
2nd line

80 80
VOUT = 1.2 V, L = 1 µH
75 76
100 100
72
70
68
VOUT = 1.2 V, L = 0.82 µH
65 64
60 10 60 10
0 1 2 3 4 5 6 7 8 0.01 0.1 1
IOUT - Output Current (A) IOUT - Output Current (A)

Fig. 30 - SiC438 Efficiency vs. Output Current Fig. 33 - SiC438 Efficiency vs. Output Current
(VIN = 24 V, fsw = 500 kHz, Full Load) (VIN = 24 V, fsw = 500 kHz, Light Load)

S20-0679-Rev. D, 27-Aug-2020 12 Document Number: 75921


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ELECTRICAL CHARACTERISTICS 
(VIN = 12 V, VOUT = 1.2 V, fsw = 500 kHz, COUT = 47 μF x 7, CIN = 10 μF x 6, unless otherwise noted)

2.00 1.2
Normalized On-State Resistance, RDS(on)

1.75 1.1

EN Logic Threshold, VEN (V)


1.50 1.0

1.25 0.9
VIH_EN
1.00 0.8

0.75 0.7

0.50 0.6
VIL_EN
0.25 0.5

0.00 0.4
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C)
Temperature (°C)

Fig. 34 - On-Resistance vs. Junction Temperature Fig. 37 - EN Logic Threshold vs. Junction Temperature

608 100

606 90
Voltage Reference, VFB (mv)

604 80
Input Current, I VIN (uA)

602 70

600 60

598 50

596 40

594 30

592 20
-60 -40 -20 0 20 40 60 80 100 120 140 3 6 9 12 15 18 21 24 27 30 33
Temperature (°C) Input Voltage (V)

Fig. 35 - Voltage reference vs. Junction Temperature Fig. 38 - Input Current vs. Input Voltage

1.4 100
VEN = 5 V
1.3 90

1.2 80
EN Current, IEN (μA)

Input Current, IVIN (μA)

1.1 70

1.0 60

0.9 50

0.8 40

0.7 30

0.6 20
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C) Temperature (°C)

Fig. 36 - EN Current vs. Junction Temperature Fig. 39 - Input Current vs. Junction Temperature

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ELECTRICAL CHARACTERISTICS 
(VIN = 12 V, VOUT = 1.2 V, fsw = 500 kHz, COUT = 47 μF x 7, CIN = 10 μF x 6, unless otherwise noted)

3.0 1.00
2.8
0.75
2.5
Shutdown Current, IVIN_SHDN (uA)

2.3 0.50

Load Regulation (%)


2.0
0.25
1.8
1.5 0.00
1.3
-0.25
1.0
0.8 -0.50
0.5
-0.75
0.3
0.0 -1.00
0 3 6 9 12 15 18 21 24 27 30 0.0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25
Input Voltage (V) Output Current (A)

Fig. 40 - Shutdown Current vs. Input Voltage Fig. 42 - Load Regulation vs. Output Current

1.2 1.00

1.1 0.75
Shutdown Current, IVIN_SHDN (μA)

0.9 0.50

0.8 0.25
Line Regulation (%)

0.6 0.00

0.5 -0.25

0.3 -0.50

0.2 -0.75

0.0 -1.00
-60 -40 -20 0 20 40 60 80 100 120 140 3 6 9 12 15 18 21 24 27 30 33
Temperature (°C) Input Voltage (V)

Fig. 41 - Shutdown Current vs. Junction Temperature Fig. 43 - Line Regulation vs. Input Voltage

S20-0679-Rev. D, 27-Aug-2020 14 Document Number: 75921


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ELECTRICAL CHARACTERISTICS 
(VIN = 12 V, VOUT = 1.2 V, fsw = 500 kHz, COUT = 47 μF x 7, CIN = 10 μF x 6, unless otherwise noted)

Vin, 5V/div

Vin, 5V/div VDD, 5V/div

VDD, 5V/div
Vo, 500mV/div

Vo, 500mV/div VPgood, 5V/div

VPgood, 5V/div

Fig. 44 - Startup with VIN, t = 5 ms/div Fig. 47 - Shut down with VIN, t = 20 ms/div

VEN, 5V/div

VEN, 5V/div

VDD, 5V/div

VDD, 5V/div
Vo, 500mV/div

Vo, 500mV/div VPgood, 5V/div

VPgood, 5V/div

Fig. 45 - Startup with EN, t = 1 ms/div Fig. 48 - Shut down with EN, t = 100 ms/div

Vo, 50mV/div
Vo, 50mV/div

Io, 10A/div

Io, 10A/div

SW, 10V/div SW, 10V/div

Fig. 46 - Load Step, 6 A to 12 A, 1 A/μs, t = 10 μs/div Fig. 49 - Load Release, 12 A to 6 A, 1 A/μs, t = 10 μs/div

S20-0679-Rev. D, 27-Aug-2020 15 Document Number: 75921


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ELECTRICAL CHARACTERISTICS 
(VIN = 12 V, VOUT = 1.2 V, fsw = 500 kHz, COUT = 47 μF x 7, CIN = 10 μF x 6, unless otherwise noted)

Vo, 50mV/div Vo, 50mV/div

Io, 5A/div

Io, 5A/div

SW, 10V/div SW, 10V/div

Fig. 50 - Load Step, 0.1 A to 6 A, 1 A/μs, t = 10 μs/div Fig. 53 - Load Release, 6 A to 0.1 A, 1 A/μs, t = 20 μs/div
Skip Mode Enabled Skip Mode Enabled

Vo, 50mV/div
Vo, 50mV/div

Io, 5A/div

Io, 5A/div

SW, 10V/div
SW, 10V/div

Fig. 51 - Load Step, 0.1 A to 6 A, 1 A/μs, t = 10 μs/div Fig. 54 - Load Release, 6 A to 0.1 A, 1 A/μs, t = 10 μs/div
Forced Continuous Conduction Mode Forced Continuous Conduction Mode

Vo, 20mV/div Vo, 20mV/div

Vsw, 10V/div Vsw, 10V/div

Fig. 52 - Output Ripple, 0.1 A, t = 20 μs/divSkip Mode Enabled Fig. 55 - Output Ripple, 6 A, t = 1 μs/div
Forced Continuous Conduction Mode

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ELECTRICAL CHARACTERISTICS
(VIN = 12 V, VOUT = 1.2 V, fsw = 500 kHz, COUT = 47 μF x 7, CIN = 10 μF x 6, unless otherwise noted)

Vo, 500mV/div

Vo, 20mV/div

Vsw, 10V/div

Vsw, 10V/div

Fig. 56 - Output Ripple, 0.1 A, t = 2 μs/div Fig. 58 - Output Undervoltage Protection Behavior, t = 50 μs/div
Forced Continuous Conduction Mode

VPgood, 5V/div

Vo, 500mV/div

Iinductor, 10A/div

Vsw, 10V/div

Fig. 57 - Overcurrent Protection Behavior, t = 10 μs/div

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EXAMPLE SCHEMATIC

EN

RBOOT PGOOD
CBOOT
2.2 Ω 0.1 μF RPGOOD

10 kΩ

PGOOD
BOOT
PHASE
EN
VIN 1
MODE2
VIN-PAD
VIN = 4.5 V to 28 V RMODE2 CVDD
VIN 2 499 kΩ 1 μF
VDD
VIN 3 RMODE1
CIN_D
100 nF 100 kΩ
AGND-PAD MODE1

PGND-PAD SiC437
AGND
PGND 1
R_FB_L
PGND 2
VFB
CIN PGND 10 kΩ
22 μF
x2
SW 1

SW 2

SW 3

SW 4

SW 5
GL 1

VOUT
GL 2

VDRV

AGND
R_FB_H
45 kΩ

LO VOUT = 3.3 V at 12 A

CVDRV 1.5 μH
4.7 μF 3 mΩ COUT_D COUT_C COUT_B COUT_A
47 μF 47 μF 47 μF 47 μF

* * Analog ground (AGND), and power ground (PGND) are tied internally
PGND

Fig. 59 - SiC437 configured for 4.5 V to 28 V Input, 3.3 V Output at 12 A,


500 kHz Operating Frequency, Continuous Mode enabled,
all Ceramic Output Capacitance Design

S20-0679-Rev. D, 27-Aug-2020 18 Document Number: 75921


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EXTERNAL COMPONENT SELECTION FOR THE SiC43X
This section explains external component selection for Capacitor Selection
the SiC43x family of regulators. Component reference For instance, the design goal for output voltage ripple is 3 %
designators in any equation refer to the schematic shown in (45 mV for VOUT = 1.5 V) with ripple current of 4.43 A. The
Fig. 59. maximum ESR value allowed is shown by the following
See PowerCAD online design center to simplify external equation.
component calculations.
The output capacitors are chosen based upon required ESR
Output Voltage Adjustment and capacitance. The maximum ESR requirement is
controlled by the output ripple requirement and the DC
If a different output voltage is needed, simply change the tolerance. The output voltage has a DC value that is equal to
value of VOUT and solve for R_FB_H based on the following the valley of the output ripple plus 1/2 of the peak-to-peak
formula: ripple. A change in the output ripple voltage will lead to a
change in DC voltage at the output.
R _FB_L  V OUT - V FB 
R _FB_H = -----------------------------------------------------
V FB V RIPPLE 45 mV
ESR MAX. = --------------------- = -----------------
I RIPPLE 4.43 A
Where VFB is 0.6 V for the SiC43X. R_FB_L should be a
maximum of 10 k to prevent VOUT from drifting at no load.
ESR MAX. = 10.2 m
Inductor Selection
In order to determine the inductance, the ripple current must 
first be defined. Low inductor values allow for the use of The output capacitance is usually chosen to meet transient
smaller package sizes but create higher ripple current which requirements. A worst-case load release (from maximum
can reduce efficiency. Higher inductor values will reduce the load to no load) at the moment of peak inductor current,
ripple current and, for a given DC resistance, are more determines the required capacitance. If the load release is
efficient. However, larger inductance translates directly into instantaneous (maximum load to no load in less than 1 μs)
larger packages and higher cost. Cost, size, output ripple, the output capacitor must absorb all the inductor’s stored
and efficiency are all used in the selection process. energy. The output capacitor can be calculated according to
the following equation.
The ripple current will also set the boundary for power save 

operation. The SiC431 will typically enter power save mode L O  I OUT + 0.5 x I RIPPLE 
2
when the load current decreases to 1/2 of the ripple current. C OUT_MIN. = ------------------------------------------------------------------------------
MAX.
2 2
For example, if ripple current is 4 A, power save operation V PK - V OUT
will be active for loads less than 2 A. If ripple current is set 
at 40 % of maximum load current, power save will typically 
start at a load which is 20 % of maximum current. Where IOUT is the output current, IRIPPLE_MAX. is the
The inductor value is typically selected to provide ripple maximum ripple current, VPK is the peak VOUT during load
current of 25 % to 50 % of the maximum load current. This release, VOUT is the output voltage.
provides an optimal trade-off between cost, efficiency, and The duration of the load release is determined by VOUT and
transient performance. During the on-time, voltage across the inductor. During load release, the voltage across the
the inductor is (VIN - VOUT). The equation for determining inductor is approximately -VOUT, causing a down-slope or
inductance is shown below. falling di/dt in the inductor. If the di/dt of the load is not
much larger than di/dt of the inductor, then the inductor
 V IN - V OUT  x D current will tend to track the falling load current. This will
L O = ------------------------------------------------------ reduce the excess inductive energy that must be absorbed
K x I OUT_MAX. x f SW
by the output capacitor; therefore a smaller capacitance can
where, K is the maximum percentage of ripple current, D is be used.
the duty cycle, IOUT_MAX. is the maximum load current and Under this circumstance, the following equation can be
fSW is the switching frequency. used to calculate the needed capacitance for a given rate of
load release (diLOAD/dt).

L x I PK
2 
dT 
--------------------- -  I PK x I RELEASE  x -------------------
V OUT di LOAD 
C OUT = ----------------------------------------------------------------------------------------------------
2  V PK - V OUT  

I PK = I RELEASE +  --- x I RIPPLE 


1
2 MAX.

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Where IPK is the peak inductor current, IRIPPLE_MAX. is the Input Capacitance
maximum peak to peak inductor current, IRELEASE is the In order to determine the minimum capacitance the input
maximum load release current, VPK is the peak VOUT during voltage ripple needs to be specified; VCINPKPK  500 mV is a
load release, dILOAD /dt is the rate of load release. suitable starting point. This magnitude is determined by the
If the load step does not meet the requirement, increasing final application specification. The input current needs to be
the crossover frequency can help by adding feed forward determined for the lowest operating input voltage,
capacitor (CFF) in parallel to the upper feedback resistor to
generate another zero and pole. Placing the geometrical I CIN  RMS  =
mean of this pole and zero around the crossover frequency
will result in faster transient response. fZ and fP are the V OUT 2
D x  1 – D  + ------   -------------------------------------   1 – D   D
1 2
generated zero and pole, see equations below. IO x
12 L  ƒ sw  I OUT
 


1
fZ = --------------------------------------------
-
2 x R FB1 x C FF The minimum input capacitance can then be found,

D x 1 - D

1 

C IN_min. = I OUT x -----------------------------------------


f P = -----------------------------------------------------------------------

2 x  R FB1 // R FB2  x C FF V CINPKPK x f sw







Where RFB1 is the upper feedback resistor, RFB2 is the lower If high ESR capacitors are used, it is good practice to also
feedback resistor CFF is the feed forward capacitor, fZ is the add low ESR ceramic capacitance. A 4.7 μF ceramic input
zero from feed forward capacitor, fP is the pole frequency capacitance is a suitable starting point.
generated from the feed forward capacitor. Care must be taken to account for voltage derating of the
A calculator is available to assist user to obtain the value of capacitance when choosing an all ceramic input
the feed forward capacitance value. capacitance.
From the calculator, obtain the crossover frequency (fC). Use
the equation below for the calculation of the feed forward
capacitance value.
 


fC =  fZ x fP 

1 

C FF = -----------------------------------------------------------------------------------------------------


2 x  f C x  R FB1 x  R FB1 // R FB2    






As the internal RC compensation of the SiC431 works with


a wide range of output LC filters, the SiC431 offers stable
operation for a wide range of output capacitance, making
the product versatile and usable in a wide range of
applications.

S20-0679-Rev. D, 27-Aug-2020 20 Document Number: 75921


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SiC437, SiC438
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PCB LAYOUT RECOMMENDATIONS
Step 1: VIN/GND Planes and Decoupling Step 3: VDD/VDRV Input Filter

VIN plane

AGND
CVDD

PGND

CVDRV
PGND plane SW

1. Layout VIN and PGND planes as shown above


2. Ceramic capacitors should be placed between VIN and 1. CVDD cap should be placed between VDD and AGND to
PGND, and very close to the device for best decoupling achieve best noise filtering
effect
2. CVDRV cap should be placed close to VDRV and PGND pins
3. Various ceramic capacitor values and package sizes to reduce effects of trace impedance and provide
should be used to cover entire decoupling spectrum e.g. maximum instantaneous driver current for low side
1210 and 0603 MOSFET during switching cycle
4. Smaller capacitance values, closer to VIN pin(s), provide Step 4: BOOT Resistor and Capacitor Placement
better high frequency response
Step 2: SW Plane
Rboot Cboot
Snubber

PGND plane

SW

1. Connect output inductor to device with large plane to


1. CBOOT and RBOOT need to be placed very close to the
lower resistance
device, between PHASE and BOOT pins
2. If a snubber network is required, place the components
2. In order to reduce parasitic inductance, it is
on the bottom layer as shown above
recommended to use 0402 chip size for the resistor and
the capacitor

S20-0679-Rev. D, 27-Aug-2020 21 Document Number: 75921


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Step 5: Signal Routing 3. SW pad is a noise source and it is not recommended to
place vias on this pad
4. 8 mil vias on pads and 10 mil vias on planes are ideal via
sizes. The vias on pad may drain solder during assembly
and cause assembly issues. Please consult with the
assembly house for guideline

AGND Step 7: Ground Connection
plane

PGND

V
o
u
t
Vias
s
i
g
n
a
l
Vias
1. Separate the small analog signal from high current path.
As shown above, the high paths with high dv/dt, di/dt are
placed on the left side of the IC, while the small control 1. In order to minimize the ground voltage drop due to high
signals are placed on the right side of the IC. All the current, it is recommended to place vias on the PGND
components for small analog signal should be placed planes. Make use of the inner ground layers to lower the
closer to IC with minimum trace length impedance
2. IC analog ground (AGND), pin 16, should have a single 
connection to PGND. The AGND ground plane connected Step 7: Ground Layer
to pin16 helps to keep AGND quiet and improves noise
immunity
3. The output signal can be routed through inner layers. AGND plane
Make sure this signal is far away from SW node and
shielded by an inner ground layer

Step 6: Thermal Management
VIN plane PGND plane

PGND plane
1. It is recommended to make the whole inner 1 layer (next
to top layer) ground plane
2. This ground plane provides shielding between noise
SW source on top layer and signal trace within inner layer
3. The ground plane can be broken into two section, PGND
1. Thermal relief vias can be added to the VIN and PGND and AGND
pads to utilize inner layers for high current and thermal
dissipation
2. To achieve better thermal performance, additional vias
can be placed on VIN and PGND planes. It is also
necessary to duplicate the VIN and ground plane at
bottom layer to maximize the power dissipation
capability of the PCB

S20-0679-Rev. D, 27-Aug-2020 22 Document Number: 75921


For technical questions, contact: [email protected]
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SiC437, SiC438
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PRODUCT SUMMARY
Part number SiC437A SiC437B SiC437C SiC437D
12 A, 4.5 V to 28 V input, 12 A, 4.5 V to 28 V input, 12 A, 3 V to 28 V input, 12 A, 3 V to 28 V input,
300 kHz, 500 kHz, 300 kHz, 500 kHz, 300 kHz, 500 kHz, 300 kHz, 500 kHz,
750 kHz, 1 MHz, 750 kHz, 1 MHz, 750 kHz, 1 MHz, 750 kHz, 1 MHz,
Description synchronous buck synchronous buck synchronous buck synchronous buck
regulator with regulator with regulator with regulator with
ultrasonic mode and power save mode and ultrasonic mode, power save mode,
internal 5 V bias internal 5 V bias requires external 5 V bias requires external 5 V bias
Input voltage min. (V) 4.5 4.5 3 3
Input voltage max. (V) 28 28 28 28
Output voltage min. (V) 0.6 0.6 0.6 0.6
Output voltage max. (V) 0.9 x VIN 0.9 x VIN 0.9 x VIN 0.9 x VIN
Continuous current (A) 12 12 12 12
Switch frequency min. (kHz) 300 300 300 300
Switch frequency max. (kHz) 1000 1000 1000 1000
Pre-bias operation (yes / no) Yes Yes Yes Yes
Internal bias reg. (yes / no) Yes Yes No No
Compensation Internal Internal Internal Internal
Enable (yes / no) Yes Yes Yes Yes
PGOOD (yes / no) Yes Yes Yes Yes
Over current protection Yes Yes Yes Yes
OVP, OCP, UVP/SCP, OVP, OCP, UVP/SCP, OVP, OCP, UVP/SCP, OVP, OCP, UVP/SCP,
Protection
OTP, UVLO OTP, UVLO OTP, UVLO OTP, UVLO
Light load mode Selectable ultrasonic Selectable powersave Selectable ultrasonic Selectable powersave
Peak efficiency (%) 97 97 97 97
Package type PowerPAK MLP44-24L PowerPAK MLP44-24L PowerPAK MLP44-24L PowerPAK MLP44-24L
Package size (W, L, H) (mm) 4 x 4 x 0.75 4 x 4 x 0.75 4 x 4 x 0.75 4 x 4 x 0.75
Status code 1 1 1 1
microBUCK (step down microBUCK (step down microBUCK (step down microBUCK (step down
Product type
regulator) regulator) regulator) regulator)
Computing, consumer, Computing, consumer, Computing, consumer, Computing, consumer,
Applications industrial, healthcare, industrial, healthcare, industrial, healthcare, industrial, healthcare,
networking networking networking networking

S20-0679-Rev. D, 27-Aug-2020 23 Document Number: 75921


For technical questions, contact: [email protected]
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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PRODUCT SUMMARY
Part number SiC438A SiC438B SiC438C SiC438D
8 A, 4.5 V to 28 V input, 8 A, 4.5 V to 28 V input, 8 A, 3 V to 28 V input, 8 A, 3 V to 28 V input,
300 kHz, 500 kHz, 300 kHz, 500 kHz, 300 kHz, 500 kHz, 300 kHz, 500 kHz,
750 kHz, 1 MHz, 750 kHz, 1 MHz, 750 kHz, 1 MHz, 750 kHz, 1 MHz,
Description synchronous buck synchronous buck synchronous buck synchronous buck
regulator with regulator with regulator with regulator with
ultrasonic mode and power save mode and ultrasonic mode, power save mode,
internal 5 V bias internal 5 V bias requires external 5 V bias requires external 5 V bias
Input voltage min. (V) 4.5 4.5 3 3
Input voltage max. (V) 28 28 28 28
Output voltage min. (V) 0.6 0.6 0.6 0.6
Output voltage max. (V) 0.9 x VIN 0.9 x VIN 0.9 x VIN 0.9 x VIN
Continuous current (A) 8 8 8 8
Switch frequency min. (kHz) 300 300 300 300
Switch frequency max. (kHz) 1000 1000 1000 1000
Pre-bias operation (yes / no) Yes Yes Yes Yes
Internal bias reg. (yes / no) Yes Yes No No
Compensation Internal Internal Internal Internal
Enable (yes / no) Yes Yes Yes Yes
PGOOD (yes / no) Yes Yes Yes Yes
Overcurrent protection Yes Yes Yes Yes
OVP, OCP, UVP/SCP, OVP, OCP, UVP/SCP, OVP, OCP, UVP/SCP, OVP, OCP, UVP/SCP,
Protection
OTP, UVLO OTP, UVLO OTP, UVLO OTP, UVLO
Light load mode Selectable ultrasonic Selectable powersave Selectable ultrasonic Selectable powersave
Peak efficiency (%) 97 97 97 97
Package type PowerPAK MLP44-24L PowerPAK MLP44-24L PowerPAK MLP44-24L PowerPAK MLP44-24L
Package size (W, L, H) (mm) 4 x 4 x 0.75 4 x 4 x 0.75 4 x 4 x 0.75 4 x 4 x 0.75
Status code 2 2 2 2
microBUCK (step down microBUCK (step down microBUCK (step down microBUCK (step down
Product type
regulator) regulator) regulator) regulator)
Computing, consumer, Computing, consumer, Computing, consumer, Computing, consumer,
Applications industrial, healthcare, industrial, healthcare, industrial, healthcare, industrial, healthcare,
networking networking networking networking

























Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?75921.

S20-0679-Rev. D, 27-Aug-2020 24 Document Number: 75921


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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
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Vishay Siliconix
PowerPAK® MLP44-24L Case Outline
A 0.08 C
(5) (6) 2x
e x 3 = 1.35 e x 2 = 0.9
A 0.10 C A A1 K5 e1 K5
Pin 1 dot D A2 b1
by marking 18 19 20 21 22 23 24

E2-2 K4 E2-1 K4 L
K6
K4 E2-4 K4
K4 D2-2 K D2-1 L1
17

0.10 M C A B
16 1

e
e x 6 = 2.7
MLP44-24L 15
L1
2
E

D2-3

e2
(4 mm x 4 mm) 14 K1
13 3

K2
K3

E2-3
(4)

e
12 D2-4 4

L K4
D2-5

E2-5
B 11

K7
0.10 C A

10 9 8 6 5
K8 e e e1 7 K5
e x 2 = 0.9

Top view Side view Bottom view


2x

MILLIMETERS INCHES
DIM.
MIN. NOM. MAX. MIN. MAX. NOM.
A (8) 0.70 0.75 0.80 0.027 0.031 0.029
A1 0.00 - 0.05 0.000 0.002 -
A2 0.20 ref. 0.008 ref.
b (4) 0.20 0.25 0.30 0.008 0.012 0.010
b1 0.15 0.20 0.25 0.006 0.010 0.008
D 3.90 4.00 4.10 0.155 0.159 0.157
e 0.45 BSC 0.018 BSC
e1 0.70 BSC 0.028 BSC
e2 0.90 BSC 0.035 BSC
E 3.90 4.00 4.10 0.154 0.161 0.157
L 0.35 0.40 0.45 0.014 0.018 0.016
N (3) 24 24
D2-1 1.00 1.05 1.10 0.039 0.043 0.041
D2-2 1.45 1.50 1.55 0.057 0.061 0.059
D2-3 2.68 2.73 2.78 0.106 0.110 0.108
D2-4 2.02 2.07 2.12 0.079 0.083 0.081
D2-5 0.47 0.52 0.57 0.018 0.022 0.020
E2-1 0.95 1.00 1.05 0.037 0.041 0.039
E2-2 1.10 1.15 1.20 0.043 0.047 0.045
E2-3 0.33 0.38 0.43 0.013 0.017 0.015
E2-4 0.95 1.00 1.05 0.037 0.041 0.039
E2-5 0.27 0.32 0.37 0.011 0.015 0.013
K 0.40 ref. 0.016 ref.
K1 0.57 ref. 0.022 ref.
K2 0.35 ref. 0.014 ref.
K3 0.35 ref. 0.014 ref.
K4 0.35 ref. 0.014 ref.
K5 0.525 ref. 0.021 ref.
K6 0.725 ref. 0.029 ref.
K7 0.575 ref. 0.023 ref.
K8 0.975 ref. 0.038 ref.
ECN: T17-0551-Rev. B, 16-Oct-17
DWG: 6055
Notes
(1) Use millimeters as the primary measurement
(2) Dimensioning and tolerances conform to ASME Y14.5M. - 1994
(3) N is the number of terminals
(4) Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip
(5) The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body
(6) Exact shape and size of this feature is optional
(7) Package warpage max. 0.08 mm
(8) Applied only for terminals

Revision: 16-Oct-17 1 Document Number: 74345


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PAD Pattern
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Recommended Land Pattern PowerPAK® MLP44-24L

24 18

17

11

5 10
4
0.45 x 2 = 0.9 0.7 0.45 x 3 = 1.35
0.525 0.525

0.45 0.3
24 18
0.3

0.725

0.725
1.175

0.3

0.25 1.15 0.3 1.575 0.3 17


0.3

0.3
1.05

1
0.45

0.45 x 6 = 2.7
0.3

2.825 0.5
4

0.9

0.3

0.3

0.455
0.27

0.65

0.27 0.58
0.45

1.2

0.3
0.38

4
11
0.73 0.39

0.45
1.025

0.55 2.175
0.575
0.725

0.3
0.45
0.3

0.725
5 10
0.3

0.7 0.45 0.45


0.525 0.9 0.975

All dimensions are in millimeters

Revision: 15-Aug-17 1 Document Number: 78231


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Legal Disclaimer Notice
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Disclaimer

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Revision: 01-Jan-2021 1 Document Number: 91000

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