SiC437
SiC437
www.vishay.com
Vishay Siliconix
3 V to 28 V Input, 8 A, 12 A
microBUCK® DC/DC Converter
FEATURES
• Versatile
- Operation from 3 V to 28 V input voltage
- Adjustable output voltage down to 0.6 V
- Scalable solution 8 A (SiC438), 12 A (SiC437),
and 24 A (SiC431)
LINKS TO ADDITIONAL RESOURCES - Output voltage tracking and sequencing with pre-bias
start up
Simulation Evaluation Design Tools - ± 1 % output voltage accuracy at -40 °C to +125 °C
Tool Boards
• Highly efficient
DESCRIPTION - 97 % peak efficiency
The SiC43x are synchronous buck regulators with
integrated high side and low side power MOSFETs. Its - 1 μA supply current at shutdown
power stage is capable of supplying 12 A (SiC437) and 8 A - 50 μA operating current not switching
(SiC438) continuous current at up to 1 MHz switching • Highly configurable
frequency. This regulator produces an adjustable output
voltage down to 0.6 V from 3 V to 28 V input rail to - Four programmable switching frequencies available:
accommodate a variety of applications, including 300 kHz, 500 kHz, 750 kHz, and 1 MHz
computing, consumer electronics, telecom, and industrial.
- Adjustable soft start and adjustable current limit
SiC437’s and SiC438’s architecture delivers ultrafast
transient response with minimum output capacitance and - Three modes of operation: forced continuous
tight ripple regulation at very light load. The device is conduction, power save (SiC43xB, SiC43xD), or
internally compensated and is stable with any capacitor. No ultrasonic (SiC43xA, SiC43xC)
external ESR network is required for loop stability purposes.
The device also incorporates a power saving scheme that • Robust and reliable
significantly increases light load efficiency. - Cycle-by-cycle current limit
The regulator family integrates a full protection feature set, - Output overvoltage protection
including output overvoltage protection (OVP), cycle by
cycle overcurrent protection (OCP) short circuit protection - Output undervoltage / short circuit protection with auto
(SCP) and thermal shutdown (OTP). It also has UVLO and a retry
user programmable soft start. - Power good flag and over temperature protection
The SiC437 and SiC438 are available in lead (Pb)-free power
enhanced MLP-44L package in 4 mm x 4 mm dimension. • Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
APPLICATIONS
• 5 V, 12 V, and 24 V input rail POLs
• Desktop, notebooks, server, and industrial computing
• Industrial and automation
• consumer electronics
PGOOD
INPUT 96
BOOT
3.0 VDC to 24 VDC
CBOOT 94
eff - Efficiency (%)
VDD SiC43x SW 90
CIN VDRV GL
88
MODE1 VOUT VOUT = 1.2 V, L = 0.56 µH 100
86
MODE2 VFB
RUP
PGND
AGND
84
RDOWN COUT 82
80 10
0 1 2 3 4 5 6 7 8 9 10 11 12
IOUT - Output Current (A)
Fig. 1 - Typical Application Circuit Fig. 2 - Efficiency vs. Output Current
(VIN = 12 V, fsw = 500 kHz, Power Saving Mode)
21 MODE1
20 MODE2
20 MODE2
21 MODE1
24 PHASE
24 PHASE
23 BOOT
23 BOOT
18 VOUT
18 VOUT
19 EN
19 EN
22 VIN
22 VIN
Pin 1 indicator
17 FB FB 17
VIN 1 16 AGND AGND 16 25 26 1 VIN
AGND VIN
VIN 2 15 VDD VDD 15 2 VIN
14 PGOOD PGOOD 14
PGND 3 13 PGND PGND 13 27 3 PGND
PGND
PGND 4 12 VDRV VDRV 12 4 PGND
11 GL GL 11
28
SW 5
SW 6
SW 7
SW 8
SW 9
GL 10
GL 10
SW 9
SW 8
SW 7
SW 6
SW 5
GL
PIN DESCRIPTION
PIN NUMBER SYMBOL DESCRIPTION
1, 2, 22, 26 VIN Input voltage
3, 4, 13, 27 PGND Power signal return ground
5 to 9 SW Switching node signal; output inductor connection point
10, 11, 28 GL Low side power MOSFET gate signal
12 VDRV Supply voltage for internal gate driver. Connect a 2.2 μF decoupling capacitor to PGND
14 PGOOD Power good signal output; open drain
15 VDD Supply voltage for internal logic. Connect a 1 μF decoupling capacitor to AGND
16, 25 AGND Analog signal return ground
17 FB Output voltage feedback pin; connect to VOUT through a resistor divider network.
18 VOUT Output voltage sense pin
19 EN Enable pin
20 MODE2 Soft start and current limit selection; connect a resistor to VDD or AGND per table 2
21 MODE1 Operating mode and switching frequency selection; connect a resistor to VDD or AGND per table 1
23 BOOT Bootstrap pin; connect a capacitor to PHASE pin for HS power MOSFET gate voltage supply
24 PHASE Switching node signal for bootstrap return path
ORDERING INFORMATION
OPERATING
PART MAXIMUM LIGHT LOAD
PART NUMBER VDD, VDRV JUNCTION PACKAGE
MARKING CURRENT MODE
TEMPERATURE
SiC437AED-T1-GE3 SiC437A Ultrasonic
Internal
SiC437BED-T1-GE3 SiC437B Power saving
12 A
SiC437CED-T1-GE3 SiC437C Ultrasonic
External
SiC437DED-T1-GE3 SiC437D Power saving
-40 °C to +125 °C PowerPAK® MLP44-24L
SiC438AED-T1-GE3 SiC438A Ultrasonic
Internal
SiC438BED-T1-GE3 SiC438B Power saving
8A
SiC438CED-T1-GE3 SiC438C Ultrasonic
External
SiC438DED-T1-GE3 SiC438D Power saving
ELECTRICAL SPECIFICATIONS (VIN = 12 V, VEN = 5 V, TJ = -40 °C to +125 °C, unless otherwise stated)
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Power Supplies
VIN = 6 V to 28 V
VDD supply VDD 4.75 5 5.25
(SiC43xA, SiC43xB) V
VDD UVLO threshold, rising VDD_UVLO 3.3 3.6 3.9
VDD UVLO hysteresis VDD_UVLO_HYST - 300 - mV
Maximum VDD current IDD VIN = 6 V to 28 V 3 - - mA
VIN = 6 V to 28 V
VDRV supply VDRV 4.75 5 5.25 V
(SiC43xA, SiC43xB)
Maximum VDRV current IDRV VIN = 6 V to 28 V 50 - - mA
Input current IVIN Non-switching, VFB > 0.6 V - 50 120
μA
Shutdown current IVIN_SHDN VEN = 0 V - 0.5 3
Controller and Timing
TJ = 25 °C 597 600 603
Feedback voltage VFB m/V
TJ = -40 °C to +125 °C (1) 594 600 606
VFB input bias current IFB - 2 - nA
Minimum on-time tON_MIN. - 50 65 ns
tON accuracy tON_ACCURACY -10 - 10 %
On-time range tON_RANGE 65 - 2250 ns
Ultrasonic version (SiC43xA, SiC43xC) 20 - 30
Minimum frequency, skip mode fSW_MIN. kHz
Power save version (SiC43xB, SiC43xD) 0 - -
Minimum off-time tOFF_MIN. 205 250 305 ns
Power MOSFETs (SiC437)
High side on resistance RON_HS - 10.1 -
VDRV = 5 V, TA = 25 °C m
Low side on resistance RON_LS - 3.9 -
Power MOSFETs (SiC438)
High side on resistance RON_HS - 10.1 -
VDRV = 5 V, TA = 25 °C m
Low side on resistance RON_LS - 5.5 -
Fault Protections
Over current protection
IOCL_P TJ = -10 °C to +125 °C -20 - 20
(inductor valley current)
%
Output OVP threshold VOVP - 20 -
VFB with respect to 0.6 V reference
Output UVP threshold VUVP - -80 -
TOTP_RISING Rising temperature - 150 -
Over temperature protection °C
TOTP_HYST Hysteresis - 25 -
Power Good
VFB_RISING_VTH_OV VFB rising above 0.6 V reference - 20 -
Power good output threshold %
VFB_FALLING_VTH_UV VFB falling below 0.6 V reference - -10 -
Power good hysteresis VFB_HYST - 40 - mV
Power good on resistance RON_PGOOD - 7.5 15
Power good delay time tDLY_PGOOD 15 25 35 μs
EN / MODE / Ultrasonic Threshold
EN logic high level VEN_H 1.6 - -
V
EN logic low level VEN_L - - 0.4
EN pull down resistance REN - 5 - M
Switching Frequency
fsw = 300 kHz - 51 55
fsw = 500 kHz 90 100 110
MODE1 (switching frequency) RMODE1 k
fsw = 750 kHz 180 200 220
fsw = 1000 kHz 450 499 550
ELECTRICAL SPECIFICATIONS (VIN = 12 V, VEN = 5 V, TJ = -40 °C to +125 °C, unless otherwise stated)
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Soft Start
Connect RMODE2 between
1.8 3 4.2
MODE2 and AGND
Soft start time tss ms
Connect RMODE2 between
3.6 6 8.4
MODE2 and VDD
Over Current Protection - SiC437
IOCP = 18 A 450 499 550
IOCP = 14 A 180 200 220
MODE 2 (over current protection) RMODE2 k
IOCP = 9.7 A 90 100 110
IOCP = 5.4 A - 51 55
Over Current Protection - SiC438
IOCP = 12 A 450 499 550
IOCP = 9.3 A 180 200 220
MODE 2 (over current protection) RMODE2 k
IOCP = 6.5 A 90 100 110
IOCP = 3.6 A - 51 55
Note
(1) Guaranteed by design
VIN VOUT
VDRV Sync
Regulator
rectifier
Rr
BOOT
VDD UVLO
EN Enable
MODE1
PH
Over voltage Control
under voltage logic SW
SW VDRV
VOUT Ramp On time
generator
FB
EA
Zero GL
Rc
Reference crossing
Cc PGOOD
Soft start
Over Over
MODE2 current temperature Power good
AGND PGND
Pre-Bias Start-Up
In case of pre-bias startup, output is monitored through FB
pin. If the sensed voltage on FB is higher than the internal
reference ramp value, control logic prevents high side and
low side MOSFETs from switching to avoid negative output
voltage spike and excessive current sinking through low
side MOSFET.
1000 1000
92 88
2nd line
2nd line
1st line
1st line
2nd line
2nd line
90 85
VOUT = 1.2 V, L = 0.56 µH
88 82
100 VOUT = 1.2 V, L = 0.56 µH 100
86 79
84 76
82 73
80 10 70 10
0 1 2 3 4 5 6 7 8 9 10 11 12 0.01 0.1 1
IOUT - Output Current (A) IOUT - Output Current (A)
Fig. 10 - SiC437 Efficiency vs. Output Current Fig. 13 - SiC437 Efficiency vs. Output Current
(VIN = 12 V, fsw = 500 kHz, Full Load) (VIN = 12 V, fsw = 500 kHz, Light Load)
1000 80 1000
92 VOUT = 1.2 V, L = 0.56 µH
75
2nd line
2nd line
1st line
1st line
2nd line
2nd line
90 70
VOUT = 1.2 V, L = 0.56 µH 65
88
100 60 100
86
55
84
50
82 45
80 10 40 10
0 1 2 3 4 5 6 7 8 9 10 11 12 0.01 0.1 1
IOUT - Output Current (A) IOUT - Output Current (A)
Fig. 11 - SiC437 Efficiency vs. Output Current Fig. 14 - SiC437 Efficiency vs. Output Current
(VIN = 12 V, fsw = 500 kHz, Ultrasonic Mode, Full Load) (VIN = 12 V, fsw = 500 kHz, Ultrasonic Mode, Light Load)
1000 1000
92 88
2nd line
2nd line
1st line
1st line
2nd line
2nd line
Fig. 12 - SiC437 Efficiency vs. Output Current Fig. 15 - SiC437 Efficiency vs. Output Current
(VIN = 5 V, fsw = 500 kHz, Full Load) (VIN = 5 V, fsw = 500 kHz, Light Load)
1000 1000
92 VOUT = 3.3 V, L = 0.56 µH 88
2nd line
2nd line
1st line
1st line
2nd line
2nd line
90 85 VOUT = 3.3 V, L = 0.56 µH
88 82
VOUT = 1.2 V, L = 0.36 µH 100 100
86 79
VOUT = 1.2 V, L = 0.36 µH
84 76
82 73
80 10 70 10
0 1 2 3 4 5 6 7 8 9 10 11 12 0.01 0.1 1
IOUT - Output Current (A) IOUT - Output Current (A)
Fig. 16 - SIC437 Efficiency vs. Output Current Fig. 19 - SiC437 Efficiency vs. Output Current
(VIN = 12 V, fsw = 1 MHz, Full Load) (VIN = 12 V, fsw = 1 MHz, Light Load)
1000 68 1000
92 60
2nd line
2nd line
1st line
2nd line
2nd line
1st line
90 52
88 44
VOUT = 1.2 V, L = 0.56 µH
100 36 100
86
28
84
20
82 12 VOUT = 1.2 V, L = 0.56 µH
80 10 4 10
0 1 2 3 4 5 6 7 8 9 10 11 12 0.001 0.01 0.1 1
IOUT - Output Current (A) IOUT - Output Current (A)
Fig. 17 - SiC437 Efficiency vs. Output Current Fig. 20 - SiC437 Efficiency vs. Output Current
(VIN = 12 V, fsw = 500 kHz, FCCM, Full Load) (VIN = 12 V, fsw = 500 kHz, FCCM, Light Load)
1000 1000
85 84 VOUT = 3.3 V, L = 1.5 µH
2nd line
2nd line
1st line
1st line
2nd line
2nd line
80 80
VOUT = 1.2 V, L = 0.56 µH
75 76
100 100
72
70
68
VOUT = 1.2 V, L = 0.56 µH
65 64
60 10 60 10
0 1 2 3 4 5 6 7 8 9 10 11 12 0.01 0.1 1
IOUT - Output Current (A) IOUT - Output Current (A)
Fig. 18 - SiC437 Efficiency vs. Output Current Fig. 21 - SiC437 Efficiency vs. Output Current
(VIN = 24 V, fsw = 500 kHz, Full Load) (VIN = 24 V, fsw = 500 kHz, Light Load)
2nd line
2nd line
1st line
2nd line
1st line
2nd line
90 85
VOUT = 1.2 V, L = 0.82 µH
88 82
100 VOUT = 1.2 V, L = 0.82 µH 100
86 79
84 76
82 73
80 10 70 10
0 1 2 3 4 5 6 7 8 0.01 0.1 1
IOUT - Output Current (A) IOUT - Output Current (A)
Fig. 22 - SiC438 Efficiency vs. Output Current Fig. 25 - SiC438 Efficiency vs. Output Current
(VIN = 12 V, fsw = 500 kHz, Full Load) (VIN = 12 V, fsw = 500 kHz, Light Load)
2nd line
1st line
1st line
2nd line
2nd line
90 70
VOUT = 1.2 V, L = 0.82 µH 65
88
100 60 VOUT = 1.2 V, L = 0.82 µH 100
86
55
84
50
82 45
80 10 40 10
0 1 2 3 4 5 6 7 8 0.01 0.1 1
IOUT - Output Current (A) IOUT - Output Current (A)
Fig. 23 - SiC438 Efficiency vs. Output Current Fig. 26 - SiC438 Efficiency vs. Output Current
(VIN = 12 V, fsw = 500 kHz, Ultrasonic Mode, Full Load) (VIN = 12 V, fsw = 500 kHz, Ultrasonic Mode, Light Load)
1000 1000
92 88
2nd line
2nd line
2nd line
1st line
1st line
2nd line
88 82
100 100
86 79
84 76
82 73
80 10 70 10
0 1 2 3 4 5 6 7 8 0.01 0.1 1
IOUT - Output Current (A) IOUT - Output Current (A)
Fig. 24 - SiC438 Efficiency vs. Output Current Fig. 27 - SiC438 Efficiency vs. Output Current
(VIN = 5 V, fsw = 500 kHz, Full Load) (VIN = 5 V, fsw = 500 kHz, Light Load)
1000 1000
88 88 VOUT = 3.3 V, L = 1 µH
2nd line
2nd line
1st line
1st line
2nd line
2nd line
85 85
VOUT= 1.2 V, L = 0.47 µH
82 82
100 100
79 79
76 76
VOUT = 1.2 V, L = 0.47 µH
73 73
70 10 70 10
0 1 2 3 4 5 6 7 8 0.01 0.1 1
IOUT - Output Current (A) IOUT - Output Current (A)
Fig. 28 - SiC438 Efficiency vs. Output Current Fig. 31 - SiC438 Efficiency vs. Output Current
(VIN = 12 V, fsw = 1 MHz, Full Load) (VIN = 12 V, fsw = 1 MHz, Light Load)
2nd line
2nd line
1st line
1st line
2nd line
2nd line
90 52
88 VOUT = 1.2 V, L = 0.82 µH 40
100 100
86
28
84
82 16
VOUT = 1.2 V, L = 0.82 µH
80 10 4 10
0 1 2 3 4 5 6 7 8 0.001 0.01 0.1 1
IOUT - Output Current (A) IOUT - Output Current (A)
Fig. 29 - SiC438 Efficiency vs. Output Current Fig. 32 - SiC438 Efficiency vs. Output Current
(VIN = 12 V, fsw = 500 kHz, FCCM, Full Load) (VIN = 12 V, fsw = 500 kHz, FCCM, Light Load)
1000 1000
85 84
2nd line
2nd line
1st line
2nd line
80 80
VOUT = 1.2 V, L = 1 µH
75 76
100 100
72
70
68
VOUT = 1.2 V, L = 0.82 µH
65 64
60 10 60 10
0 1 2 3 4 5 6 7 8 0.01 0.1 1
IOUT - Output Current (A) IOUT - Output Current (A)
Fig. 30 - SiC438 Efficiency vs. Output Current Fig. 33 - SiC438 Efficiency vs. Output Current
(VIN = 24 V, fsw = 500 kHz, Full Load) (VIN = 24 V, fsw = 500 kHz, Light Load)
2.00 1.2
Normalized On-State Resistance, RDS(on)
1.75 1.1
1.25 0.9
VIH_EN
1.00 0.8
0.75 0.7
0.50 0.6
VIL_EN
0.25 0.5
0.00 0.4
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C)
Temperature (°C)
Fig. 34 - On-Resistance vs. Junction Temperature Fig. 37 - EN Logic Threshold vs. Junction Temperature
608 100
606 90
Voltage Reference, VFB (mv)
604 80
Input Current, I VIN (uA)
602 70
600 60
598 50
596 40
594 30
592 20
-60 -40 -20 0 20 40 60 80 100 120 140 3 6 9 12 15 18 21 24 27 30 33
Temperature (°C) Input Voltage (V)
Fig. 35 - Voltage reference vs. Junction Temperature Fig. 38 - Input Current vs. Input Voltage
1.4 100
VEN = 5 V
1.3 90
1.2 80
EN Current, IEN (μA)
1.1 70
1.0 60
0.9 50
0.8 40
0.7 30
0.6 20
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C) Temperature (°C)
Fig. 36 - EN Current vs. Junction Temperature Fig. 39 - Input Current vs. Junction Temperature
3.0 1.00
2.8
0.75
2.5
Shutdown Current, IVIN_SHDN (uA)
2.3 0.50
Fig. 40 - Shutdown Current vs. Input Voltage Fig. 42 - Load Regulation vs. Output Current
1.2 1.00
1.1 0.75
Shutdown Current, IVIN_SHDN (μA)
0.9 0.50
0.8 0.25
Line Regulation (%)
0.6 0.00
0.5 -0.25
0.3 -0.50
0.2 -0.75
0.0 -1.00
-60 -40 -20 0 20 40 60 80 100 120 140 3 6 9 12 15 18 21 24 27 30 33
Temperature (°C) Input Voltage (V)
Fig. 41 - Shutdown Current vs. Junction Temperature Fig. 43 - Line Regulation vs. Input Voltage
Vin, 5V/div
VDD, 5V/div
Vo, 500mV/div
VPgood, 5V/div
Fig. 44 - Startup with VIN, t = 5 ms/div Fig. 47 - Shut down with VIN, t = 20 ms/div
VEN, 5V/div
VEN, 5V/div
VDD, 5V/div
VDD, 5V/div
Vo, 500mV/div
VPgood, 5V/div
Fig. 45 - Startup with EN, t = 1 ms/div Fig. 48 - Shut down with EN, t = 100 ms/div
Vo, 50mV/div
Vo, 50mV/div
Io, 10A/div
Io, 10A/div
Fig. 46 - Load Step, 6 A to 12 A, 1 A/μs, t = 10 μs/div Fig. 49 - Load Release, 12 A to 6 A, 1 A/μs, t = 10 μs/div
Io, 5A/div
Io, 5A/div
Fig. 50 - Load Step, 0.1 A to 6 A, 1 A/μs, t = 10 μs/div Fig. 53 - Load Release, 6 A to 0.1 A, 1 A/μs, t = 20 μs/div
Skip Mode Enabled Skip Mode Enabled
Vo, 50mV/div
Vo, 50mV/div
Io, 5A/div
Io, 5A/div
SW, 10V/div
SW, 10V/div
Fig. 51 - Load Step, 0.1 A to 6 A, 1 A/μs, t = 10 μs/div Fig. 54 - Load Release, 6 A to 0.1 A, 1 A/μs, t = 10 μs/div
Forced Continuous Conduction Mode Forced Continuous Conduction Mode
Fig. 52 - Output Ripple, 0.1 A, t = 20 μs/divSkip Mode Enabled Fig. 55 - Output Ripple, 6 A, t = 1 μs/div
Forced Continuous Conduction Mode
Vo, 500mV/div
Vo, 20mV/div
Vsw, 10V/div
Vsw, 10V/div
Fig. 56 - Output Ripple, 0.1 A, t = 2 μs/div Fig. 58 - Output Undervoltage Protection Behavior, t = 50 μs/div
Forced Continuous Conduction Mode
VPgood, 5V/div
Vo, 500mV/div
Iinductor, 10A/div
Vsw, 10V/div
EN
RBOOT PGOOD
CBOOT
2.2 Ω 0.1 μF RPGOOD
10 kΩ
PGOOD
BOOT
PHASE
EN
VIN 1
MODE2
VIN-PAD
VIN = 4.5 V to 28 V RMODE2 CVDD
VIN 2 499 kΩ 1 μF
VDD
VIN 3 RMODE1
CIN_D
100 nF 100 kΩ
AGND-PAD MODE1
PGND-PAD SiC437
AGND
PGND 1
R_FB_L
PGND 2
VFB
CIN PGND 10 kΩ
22 μF
x2
SW 1
SW 2
SW 3
SW 4
SW 5
GL 1
VOUT
GL 2
VDRV
AGND
R_FB_H
45 kΩ
LO VOUT = 3.3 V at 12 A
CVDRV 1.5 μH
4.7 μF 3 mΩ COUT_D COUT_C COUT_B COUT_A
47 μF 47 μF 47 μF 47 μF
* * Analog ground (AGND), and power ground (PGND) are tied internally
PGND
operation. The SiC431 will typically enter power save mode L O I OUT + 0.5 x I RIPPLE
2
when the load current decreases to 1/2 of the ripple current. C OUT_MIN. = ------------------------------------------------------------------------------
MAX.
2 2
For example, if ripple current is 4 A, power save operation V PK - V OUT
will be active for loads less than 2 A. If ripple current is set
at 40 % of maximum load current, power save will typically
start at a load which is 20 % of maximum current. Where IOUT is the output current, IRIPPLE_MAX. is the
The inductor value is typically selected to provide ripple maximum ripple current, VPK is the peak VOUT during load
current of 25 % to 50 % of the maximum load current. This release, VOUT is the output voltage.
provides an optimal trade-off between cost, efficiency, and The duration of the load release is determined by VOUT and
transient performance. During the on-time, voltage across the inductor. During load release, the voltage across the
the inductor is (VIN - VOUT). The equation for determining inductor is approximately -VOUT, causing a down-slope or
inductance is shown below. falling di/dt in the inductor. If the di/dt of the load is not
much larger than di/dt of the inductor, then the inductor
V IN - V OUT x D current will tend to track the falling load current. This will
L O = ------------------------------------------------------ reduce the excess inductive energy that must be absorbed
K x I OUT_MAX. x f SW
by the output capacitor; therefore a smaller capacitance can
where, K is the maximum percentage of ripple current, D is be used.
the duty cycle, IOUT_MAX. is the maximum load current and Under this circumstance, the following equation can be
fSW is the switching frequency. used to calculate the needed capacitance for a given rate of
load release (diLOAD/dt).
L x I PK
2
dT
--------------------- - I PK x I RELEASE x -------------------
V OUT di LOAD
C OUT = ----------------------------------------------------------------------------------------------------
2 V PK - V OUT
1
fZ = --------------------------------------------
-
2 x R FB1 x C FF The minimum input capacitance can then be found,
D x 1 - D
1
Where RFB1 is the upper feedback resistor, RFB2 is the lower If high ESR capacitors are used, it is good practice to also
feedback resistor CFF is the feed forward capacitor, fZ is the add low ESR ceramic capacitance. A 4.7 μF ceramic input
zero from feed forward capacitor, fP is the pole frequency capacitance is a suitable starting point.
generated from the feed forward capacitor. Care must be taken to account for voltage derating of the
A calculator is available to assist user to obtain the value of capacitance when choosing an all ceramic input
the feed forward capacitance value. capacitance.
From the calculator, obtain the crossover frequency (fC). Use
the equation below for the calculation of the feed forward
capacitance value.
fC = fZ x fP
1
C FF = -----------------------------------------------------------------------------------------------------
VIN plane
AGND
CVDD
PGND
CVDRV
PGND plane SW
PGND plane
SW
PGND
V
o
u
t
Vias
s
i
g
n
a
l
Vias
1. Separate the small analog signal from high current path.
As shown above, the high paths with high dv/dt, di/dt are
placed on the left side of the IC, while the small control 1. In order to minimize the ground voltage drop due to high
signals are placed on the right side of the IC. All the current, it is recommended to place vias on the PGND
components for small analog signal should be placed planes. Make use of the inner ground layers to lower the
closer to IC with minimum trace length impedance
2. IC analog ground (AGND), pin 16, should have a single
connection to PGND. The AGND ground plane connected Step 7: Ground Layer
to pin16 helps to keep AGND quiet and improves noise
immunity
3. The output signal can be routed through inner layers. AGND plane
Make sure this signal is far away from SW node and
shielded by an inner ground layer
Step 6: Thermal Management
VIN plane PGND plane
PGND plane
1. It is recommended to make the whole inner 1 layer (next
to top layer) ground plane
2. This ground plane provides shielding between noise
SW source on top layer and signal trace within inner layer
3. The ground plane can be broken into two section, PGND
1. Thermal relief vias can be added to the VIN and PGND and AGND
pads to utilize inner layers for high current and thermal
dissipation
2. To achieve better thermal performance, additional vias
can be placed on VIN and PGND planes. It is also
necessary to duplicate the VIN and ground plane at
bottom layer to maximize the power dissipation
capability of the PCB
PRODUCT SUMMARY
Part number SiC437A SiC437B SiC437C SiC437D
12 A, 4.5 V to 28 V input, 12 A, 4.5 V to 28 V input, 12 A, 3 V to 28 V input, 12 A, 3 V to 28 V input,
300 kHz, 500 kHz, 300 kHz, 500 kHz, 300 kHz, 500 kHz, 300 kHz, 500 kHz,
750 kHz, 1 MHz, 750 kHz, 1 MHz, 750 kHz, 1 MHz, 750 kHz, 1 MHz,
Description synchronous buck synchronous buck synchronous buck synchronous buck
regulator with regulator with regulator with regulator with
ultrasonic mode and power save mode and ultrasonic mode, power save mode,
internal 5 V bias internal 5 V bias requires external 5 V bias requires external 5 V bias
Input voltage min. (V) 4.5 4.5 3 3
Input voltage max. (V) 28 28 28 28
Output voltage min. (V) 0.6 0.6 0.6 0.6
Output voltage max. (V) 0.9 x VIN 0.9 x VIN 0.9 x VIN 0.9 x VIN
Continuous current (A) 12 12 12 12
Switch frequency min. (kHz) 300 300 300 300
Switch frequency max. (kHz) 1000 1000 1000 1000
Pre-bias operation (yes / no) Yes Yes Yes Yes
Internal bias reg. (yes / no) Yes Yes No No
Compensation Internal Internal Internal Internal
Enable (yes / no) Yes Yes Yes Yes
PGOOD (yes / no) Yes Yes Yes Yes
Over current protection Yes Yes Yes Yes
OVP, OCP, UVP/SCP, OVP, OCP, UVP/SCP, OVP, OCP, UVP/SCP, OVP, OCP, UVP/SCP,
Protection
OTP, UVLO OTP, UVLO OTP, UVLO OTP, UVLO
Light load mode Selectable ultrasonic Selectable powersave Selectable ultrasonic Selectable powersave
Peak efficiency (%) 97 97 97 97
Package type PowerPAK MLP44-24L PowerPAK MLP44-24L PowerPAK MLP44-24L PowerPAK MLP44-24L
Package size (W, L, H) (mm) 4 x 4 x 0.75 4 x 4 x 0.75 4 x 4 x 0.75 4 x 4 x 0.75
Status code 1 1 1 1
microBUCK (step down microBUCK (step down microBUCK (step down microBUCK (step down
Product type
regulator) regulator) regulator) regulator)
Computing, consumer, Computing, consumer, Computing, consumer, Computing, consumer,
Applications industrial, healthcare, industrial, healthcare, industrial, healthcare, industrial, healthcare,
networking networking networking networking
PRODUCT SUMMARY
Part number SiC438A SiC438B SiC438C SiC438D
8 A, 4.5 V to 28 V input, 8 A, 4.5 V to 28 V input, 8 A, 3 V to 28 V input, 8 A, 3 V to 28 V input,
300 kHz, 500 kHz, 300 kHz, 500 kHz, 300 kHz, 500 kHz, 300 kHz, 500 kHz,
750 kHz, 1 MHz, 750 kHz, 1 MHz, 750 kHz, 1 MHz, 750 kHz, 1 MHz,
Description synchronous buck synchronous buck synchronous buck synchronous buck
regulator with regulator with regulator with regulator with
ultrasonic mode and power save mode and ultrasonic mode, power save mode,
internal 5 V bias internal 5 V bias requires external 5 V bias requires external 5 V bias
Input voltage min. (V) 4.5 4.5 3 3
Input voltage max. (V) 28 28 28 28
Output voltage min. (V) 0.6 0.6 0.6 0.6
Output voltage max. (V) 0.9 x VIN 0.9 x VIN 0.9 x VIN 0.9 x VIN
Continuous current (A) 8 8 8 8
Switch frequency min. (kHz) 300 300 300 300
Switch frequency max. (kHz) 1000 1000 1000 1000
Pre-bias operation (yes / no) Yes Yes Yes Yes
Internal bias reg. (yes / no) Yes Yes No No
Compensation Internal Internal Internal Internal
Enable (yes / no) Yes Yes Yes Yes
PGOOD (yes / no) Yes Yes Yes Yes
Overcurrent protection Yes Yes Yes Yes
OVP, OCP, UVP/SCP, OVP, OCP, UVP/SCP, OVP, OCP, UVP/SCP, OVP, OCP, UVP/SCP,
Protection
OTP, UVLO OTP, UVLO OTP, UVLO OTP, UVLO
Light load mode Selectable ultrasonic Selectable powersave Selectable ultrasonic Selectable powersave
Peak efficiency (%) 97 97 97 97
Package type PowerPAK MLP44-24L PowerPAK MLP44-24L PowerPAK MLP44-24L PowerPAK MLP44-24L
Package size (W, L, H) (mm) 4 x 4 x 0.75 4 x 4 x 0.75 4 x 4 x 0.75 4 x 4 x 0.75
Status code 2 2 2 2
microBUCK (step down microBUCK (step down microBUCK (step down microBUCK (step down
Product type
regulator) regulator) regulator) regulator)
Computing, consumer, Computing, consumer, Computing, consumer, Computing, consumer,
Applications industrial, healthcare, industrial, healthcare, industrial, healthcare, industrial, healthcare,
networking networking networking networking
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?75921.
E2-2 K4 E2-1 K4 L
K6
K4 E2-4 K4
K4 D2-2 K D2-1 L1
17
0.10 M C A B
16 1
e
e x 6 = 2.7
MLP44-24L 15
L1
2
E
D2-3
e2
(4 mm x 4 mm) 14 K1
13 3
K2
K3
E2-3
(4)
e
12 D2-4 4
L K4
D2-5
E2-5
B 11
K7
0.10 C A
10 9 8 6 5
K8 e e e1 7 K5
e x 2 = 0.9
MILLIMETERS INCHES
DIM.
MIN. NOM. MAX. MIN. MAX. NOM.
A (8) 0.70 0.75 0.80 0.027 0.031 0.029
A1 0.00 - 0.05 0.000 0.002 -
A2 0.20 ref. 0.008 ref.
b (4) 0.20 0.25 0.30 0.008 0.012 0.010
b1 0.15 0.20 0.25 0.006 0.010 0.008
D 3.90 4.00 4.10 0.155 0.159 0.157
e 0.45 BSC 0.018 BSC
e1 0.70 BSC 0.028 BSC
e2 0.90 BSC 0.035 BSC
E 3.90 4.00 4.10 0.154 0.161 0.157
L 0.35 0.40 0.45 0.014 0.018 0.016
N (3) 24 24
D2-1 1.00 1.05 1.10 0.039 0.043 0.041
D2-2 1.45 1.50 1.55 0.057 0.061 0.059
D2-3 2.68 2.73 2.78 0.106 0.110 0.108
D2-4 2.02 2.07 2.12 0.079 0.083 0.081
D2-5 0.47 0.52 0.57 0.018 0.022 0.020
E2-1 0.95 1.00 1.05 0.037 0.041 0.039
E2-2 1.10 1.15 1.20 0.043 0.047 0.045
E2-3 0.33 0.38 0.43 0.013 0.017 0.015
E2-4 0.95 1.00 1.05 0.037 0.041 0.039
E2-5 0.27 0.32 0.37 0.011 0.015 0.013
K 0.40 ref. 0.016 ref.
K1 0.57 ref. 0.022 ref.
K2 0.35 ref. 0.014 ref.
K3 0.35 ref. 0.014 ref.
K4 0.35 ref. 0.014 ref.
K5 0.525 ref. 0.021 ref.
K6 0.725 ref. 0.029 ref.
K7 0.575 ref. 0.023 ref.
K8 0.975 ref. 0.038 ref.
ECN: T17-0551-Rev. B, 16-Oct-17
DWG: 6055
Notes
(1) Use millimeters as the primary measurement
(2) Dimensioning and tolerances conform to ASME Y14.5M. - 1994
(3) N is the number of terminals
(4) Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip
(5) The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body
(6) Exact shape and size of this feature is optional
(7) Package warpage max. 0.08 mm
(8) Applied only for terminals
24 18
17
11
5 10
4
0.45 x 2 = 0.9 0.7 0.45 x 3 = 1.35
0.525 0.525
0.45 0.3
24 18
0.3
0.725
0.725
1.175
0.3
0.3
1.05
1
0.45
0.45 x 6 = 2.7
0.3
2.825 0.5
4
0.9
0.3
0.3
0.455
0.27
0.65
0.27 0.58
0.45
1.2
0.3
0.38
4
11
0.73 0.39
0.45
1.025
0.55 2.175
0.575
0.725
0.3
0.45
0.3
0.725
5 10
0.3
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