11/22/2023

ECEg3104
Applied Electronics I Chapter-1 Semiconductor Theory

By: Behailu T.

Semiconductors … Here, there, everywhere!

In this chapter you will learn:
 Computers: Silicon (Si) MOSFETs, Integrated Circuits (ICs)
 The basic properties of semiconductors
In particular, silicon the material used to make most modern electronic circuits.  Anything “intelligent” : CMOS, RAM, DRAM, flash memory cells
 How doping a pure silicon crystal dramatically changes its  Cell phones, Solar Panels: Si ICs, GaAs FETs, BJTs
electrical conductivity
The fundamental idea in underlying the use of semiconductors in the implementation of electronic  TV remotes, mobile terminals: LEDs
devices.

 The two mechanisms by which current flows in  Satellite dishes: InGaAs MMICs
semiconductors  Optical fiber networks: InGaAsP, laser diodes, pin photodiodes
Drift and diffusion charge carriers

 The structure and operation of the pn-junction  Traffic signal: GaN LEDs
A basic semiconductor structure that implements the diode
They are very important !!!
Page  3 Page  4
 11/22/2023

Energy Band Theory Semiconductor

Conduction Band  A material whose conductivity lies between that of

conductors (copper) and insulators (glass).
Increasing Energy

 A crystal lattice structure that can have free electrons

Overlap Conduction Band
Band gap and/or free holes (which are an absence of electrons and
Conduction Band Band gap
are equivalent to positive carriers).
 Silicon is typically used in many electronic devices which is
Valance Band Valance Band Valance Band
an abundant element found, for example, in high
Conductors Semiconductors Insulators concentrations in sand.

Page  5 Page  6

Silicon: default example and main focus Intrinsic Silicon: - pure, perfect, R.T.
• Atomic no. 14
• Silicon forms strong  At room temp
covalent bonds with  some covalent bonds break, freeing an
4 neighbors
electron and creating hole, due to thermal
 At low temps energy
 all covalent bonds are  some electrons will wander from their
intact parent atoms, becoming available for
 no electrons are conduction
available for conduction  conductivity is greater than zero
 conductivity is zero

Page  7 Page  8
 11/22/2023

Intrinsic Silicon: - pure, perfect, R.T. Intrinsic Silicon: - pure, perfect, R.T.
 The intrinsic carrier concentration, ni, is very sensitive to
 In thermal equilibrium, the temperature, varying exponentially with 1/T:
concentration of free electrons
/ /
=
n0 is equal to the concentration
where:
of holes p0, B is a material-dependent parameter that is 7.3 10 /
for Si
T is the temperature in K
bandgap energy, is 1.12 electron volt (eV) for Si
= =
[NB: 1 eV = 1.6 10 J]
k is Boltzmann’s constant ( 8.62 10 eV/K)
where ni = intrinsic carrier concentration
 At R. T., 300K, ≈ 1.5 10
Page  9 Page  10

Doped Semiconductors Doped Semiconductors - carefully chosen impurities

 The intrinsic silicon crystal described has equal concentrations of free electrons
and holes, generated by thermal generation. p-type semiconductor
 These concentrations are far too small for silicon to conduct appreciable current  Silicon is doped with element having a
valence of 3 to increase the
at room temperature. concentration of holes (p).
 One example is boron, which is an
 The conductivity are strong functions of temperature, not a desirable property in
acceptor.
an electronic device.  If NA >> ni, then the concentration of
 A method was developed to change the carrier concentration in a holes in the p-type (Pp) is defined as:

semiconductor crystal substantially and in a precisely controlled manner.

 This process is known as doping, and the resulting silicon is referred to as
Where NA is concentration of acceptor atoms
doped silicon.
Page  11 Page  12
 11/22/2023

Doped Semiconductors - carefully chosen impurities Doped Semiconductors - carefully chosen impurities
p-type semiconductor
n-type semiconductor
 Concentration of electrons( ) will have the same  Silicon is doped with element having
a valence of 5 to increase the
dependence on temperature as concentration free electrons (n).
 One example is phosphorus, which is
 Concentration of holes ( ) will be much larger than a donor.
 If ND >> ni then the concentration of
electrons electrons in the n-type (nn) is defined
as:
 Holes are the majority charge carriers
Where ND is concentration of donor atoms
 Free electrons are the minority charge carrier
Page  13 Page  14

Doped Semiconductors - carefully chosen impurities Drift Current

 When an electrical field E is established in
n-type semiconductor a semiconductor crystal, holes are
 Concentration of holes( ) will have the same dependence on accelerated in the direction of E, and free
electrons are accelerated in the direction
temperature as opposite to that of E.
 Concentration of free electrons ( ) will be much larger than holes  The holes acquire a velocity
given by
 Electrons are the majority charge carriers
 Holes are the minority charge carrier
The key here in both types of materials is that number of free electrons/holes where μp is a constant called the hole mobility
(aka. conductivity) is dependent on doping concentration, not temperature For intrinsic silicon μp = 480 cm2/V ·s
Page  15 Page  16
 11/22/2023

Drift Current Drift Current

 The free electrons acquire a velocity
given by  Current component attributed to the flow Ip
of holes:

 The result is negative because the where

electrons move in the direction opposite A is the cross-sectional area of the silicon bar
to E. q is the magnitude of electron charge
 where μn is a constant called the electron mobility p concentration of holes
 For intrinsic silicon μn = 1350 cm2/V ·s  Substituting for νp-drift we obtain:
 Note that μn is about 2.5 times μp, signifying that electrons move with
much greater ease through the silicon crystal than do holes.
Page  17 Page  18

Drift Current Drift Current

 Usually interested in the current density  The current component due to the drift of
Jp free electrons can be found in a similar
Ip manner.
 Note, however, that electrons drifting
from right to left result in a current
In
component from left to right.
 This is because of the convention of taking
the direction of current flow as the
direction of flow of positive charge and
opposite to the direction of flow of
negative charge.
Page  19 Page  20
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Drift Current Drift Current

 Thus,  The total drift current density can now be
found by summing Jp and Jn

 Substituting for νn-drift , we obtain the

In  This relationship can be written as:
current density Jn

 where the conductivity σ is given by:

 And the resistivity ρ is given by:

Page  21 Page  22

Diffusion Current Diffusion Current

 Carrier diffusion is the flow of charge Take the following example
carriers from area of high concentration  Inject holes by some unspecified
to low concentration. process, one injects holes in to the left
 It requires non-uniform distribution of side of a silicon bar.
carriers.  Concentration profile arises because of
 Diffusion current is the current flow that this continuous hole inject, a
results from diffusion of charge carriers. concentration profile arises.
 Diffusion occurs because of this
concentration gradient, holes will flow
from left to right.

Page  23 Page  24
 11/22/2023

Diffusion Current Diffusion Current

 Q. How is diffusion current defined?  In the case of electron diffusion resulting
 The magnitude of the current at any from an electron concentration gradient, a
point is proportional to the slope of the similar relationship applies, giving the
concentration profile, or the electron-current density,
concentration gradient, at that point,

Jn = electron-current density (A/cm2 )

Jp = hole-current density (A/cm2 ) q = magnitude of electron charge
q = magnitude of electron charge Dn = diffusion constant of electrons = 35 cm2/s (intrinsic Si)
Dp = diffusion constant of holes = 12 cm2/s (intrinsic Si) n(x) = electron concentration at point x.
p(x) = hole concentration at point x. Page  25 Page  26

The pn-Junction Operation with Open-Circuit Terminals

 The pn junction structure  Bound Charge:
Physical Structure comprises
  charge of opposite polarity
• p-type semiconductor to free electrons / holes of a given
• n-type semiconductor material

• Metal contact for connection  neutralizes the electrical

 As the pn junction implements
charge of these majority
carriers
the junction diode, its
 does not affect
terminals are labeled anode concentration gradients
Fig. Simplified physical structure of the pn junction
and cathode
Page  27 Page  28
 11/22/2023

Operation with Open-Circuit Terminals Operation with Open-Circuit Terminals

 p-type material contains majority of
holes
 these holes are neutralized by Q: What happens when a pn-junction is newly formed aka.
equal amount of bound negative when the p-type and n-type semiconductors first touch one
charge another?
 n-type material contains majority of
A: Next slides
free electrons
 these electrons are neutralized

by equal amount of bound

positive charge

Page  29 Page  30

Operation with Open-Circuit Terminals Operation with Open-Circuit Terminals

 Step 1 The p-type and n-type semiconductors are joined at  Step 1A Bound charges are attracted by free electrons and
the junction. holes in the p-type and n-type semiconductors, respectively.
 p-type semiconductor filled with holes  They remain weakly bound to these majority carriers however, they do
 n-type semiconductor filled with free electrons junction not recombine.
p-type n-type

p-type n-type
Bound Charges
Fig. The pn junction with no applied voltage Fig. The pn junction with no applied voltage
(open-circuited terminals). (open-circuited terminals).

Page  31 Page  32
 11/22/2023

Operation with Open-Circuit Terminals Operation with Open-Circuit Terminals

 Step 2 Diffusion begins. Those free electrons and holes which are  Step 3 The depletion region begins to form as diffusion occurs and
closest to the junction will recombine and, essentially, eliminate one free electrons recombine with holes.
another.  The depletion region is filled with uncovered bound charges who have
p-type n-type
lost the majority carriers to which they were linked.
Depletion Region

Fig. The pn junction with no applied voltage

(open-circuited terminals).
p-type n-type
Fig. The pn junction with no applied voltage
(open-circuited terminals).

Page  33 Page  34

Operation with Open-Circuit Terminals Operation with Open-Circuit Terminals

 Q: Why does diffusion occur even when bound charges
neutralize the electrical attraction of majority carriers to one
another?  Step 4 The uncovered bound charges
 A: Diffusion current, is effected by a gradient in cause a voltage differential across the Depletion Region
E
depletion region. p-type n-type
concentration of majority carriers not an  As diffusion continues, the magnitude
electrical attraction of these particles to one of this barrier voltage (V0) differential
another. grows.
Fig. The pn junction with no applied voltage
(open-circuited terminals).

Page  35 Page  36
 11/22/2023

Operation with Open-Circuit Terminals Operation with Open-Circuit Terminals

Depletion Region  Step 6 Equilibrium is reached, and Depletion Region
E diffusion ceases, once the magnitudes E
p-type n-type p-type n-type
 Step 5 The barrier voltage (V0) is an of diffusion and drift currents (ID & IS)
electric field whose polarity equal one another resulting in no net
opposes the direction of diffusion flow.
Is Is
current (ID). ID  Once equilibrium is achieved, no net ID
 As the magnitude of V0 increases, the current flow exists i.e.
magnitude of ID decreases. Inet = ID = IS
within the pn-junction while under open-
circuit condition.
Fig. The pn junction with no applied voltage Fig. The pn junction with no applied voltage
(open-circuited terminals). (open-circuited terminals).

Page  37 Page  38

Operation with Open-Circuit Terminals Operation with Open-Circuit Terminals

 pn-junction built-in voltage (V0) is the equilibrium value of barrier
voltage.  Q: Is the depletion region always symmetrical as shown on
where is a thermal voltage given by:
= = 25.8mV @RT
previous slides?
= ln( ) k = Boltzmann’s constant (8.62E-5 eV/k)  A: No.
q = mag of electron charge (1.6E-19 C)
T = temperature in kelvin
 Q: Why?
 Typically NA > ND
 Generally, takes on a value between 0.6 and 0.9V for silicon at
room temperature.  And, because concentration of doping agents (NA, ND) is unequal,
the width of depletion region will differ from side to side.
 This voltage is applied across depletion region, not terminals of
 The depletion region will extend deeper in to the less doped
pn junction.
material, a requirement to uncover the same amount of charge.
 Power cannot be drawn from V0.

Page  39 Page  40
 11/22/2023

Operation with Biased Terminals Review on pn-junction

 If a voltage is supplied to the outside ends of a pn-crystal, the condition  Composition

is called biasing  The pn junction is composed of two silicon-based
semiconductors, one doped to be p-type and the other n-type.
narrow
 A majority carriers are generated by doping.
o Holes are present on p-side,
n-type p-type n-type p-type
- + - o Free electrons are present on n-side.
+

forward biased pn junction reverse biased pn junction

Page  41 Page  42

Review on pn-junction Review on pn-junction

 Bound Charges  Depletion region

 Charge of majority carriers are neutralized electrically by bound  As these carriers disappear, they release bound charges and
charges. effect a voltage differential V0.

 Diffusion Current ID  Depletion-layer voltage

 Those majority carriers close to the junction will diffuse across,  As diffusion continues, the depletion layer voltage (V0) grows,
resulting in their elimination. making diffusion more difficult and eventually bringing it to halt.

Page  43 Page  44
 11/22/2023

Review on pn-junction Reading Assignment

 Minority carriers
(Must be covered!)
 Are generated thermally.
Capacitive Effects in the pn Junction
 Free electrons are present on p-side, holes are present on n-side.
 Drift current IS
 The depletion-layer voltage (V0) facilitates the flow of minority
carriers to opposite side.
 Open circuit equilibrium
ID = I S
Page  45 Page  46

End of Chapter 1
 Islamic University of Gaza
Chapter 1:
Semiconductor Diodes Dr. Talal Skaik
Semiconductor Materials: Ge, Si, and GaAs
Semiconductors are a special class of elements having a
conductivity between that of a good conductor and
that of an insulator.
• They fall into two classes : single crystal and compound
• Single crystal : Germanium (Ge) and silicon (Si).
• Compound : gallium arsenide (GaAs),
cadmium sulfide (CdS),
gallium nitride (GaN),
gallium arsenide phosphide (GaAsP)
The three semiconductors used most frequently in the
construction of electronic devices are Ge, Si, and GaAs.
Electronic Devices and Circuit Theory, 10/e 2 Copyright ©2009 by Pearson Education, Inc.
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Group → 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

↓ Period

1 2
1
H He

3 4 5 6 7 8 9 10
2
Li Be B C N O F Ne

11 12
13 14 15 16 17 18
3 N M
Al Si P S Cl Ar
a g

21
19 20 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
4 S
K Ca Ti V Cr Mn Fe Co Ni Cu Zn Ga Ge As Se Br Kr
c

37
38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54
5 R
Sr Y Zr Nb Mo Tc Ru Rh Pd Ag Cd In Sn Sb Te I Xe
b

55 56 * 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
6
Cs Ba Hf Ta W Re Os Ir Pt Au Hg Tl Pb Bi Po At Rn

87 88 ** 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118
7
Fr Ra Rf Db Sg Bh Hs Mt Ds Rg Uub Uut Uuq Uup Uuh Uus Uuo

57 58 59 60 61 62 63 64 65 66 67 68 69 70 71
* Lanthanides
La Ce Pr Nd Pm Sm Eu Gd Tb Dy Ho Er Tm Yb Lu

89 90 91 92 93 94 95 96 97 98 99 100 101 102 103

** Actinides
Ac Th Pa U Np Pu Am Cm Bk Cf Es Fm Md No Lr

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 History
• Diode , in 1939 was using Ge
• Transistor, in 1947 was using Ge
• In1954 Si was used in Transistor because Si is less
temperature sensitive and abundantly available.
• High speed transistor was using GaAs in 1970 (which is 5
times faster compared to Si)
• Si, Ge and GaAs are the semiconductor of choice

Electronic Devices and Circuit Theory, 10/e 4 Copyright ©2009 by Pearson Education, Inc.
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 Atomic Structure
Valence shell (4 valence electrons) Valence shell (4 valence electrons)
Valence
shells electron

Valence
+ electron
+

Nucleus
orbiting
electrons
orbiting
Germanium electrons
Silicon
32 orbiting electrons 14 orbiting electrons
(tetravalent) (Tetravalent)

• Valence electrons: electrons in the outermost shell.

• Atoms with four valence electrons are called tetravalent.

Electronic Devices and Circuit Theory, 10/e 5 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Upper Saddle River, New Jersey 07458 • All rights reserved.
 Atomic Structure
Valence shell (3 valence electrons) Valence shell (5 valence electrons)
Valence Valence
shells electron electron
shells

+ +

Nucleus orbiting
electrons
Nucleus orbiting
electrons
Gallium
Arsenic

31 orbiting electrons 33 orbiting electrons

(trivalent) (pentavalent)

• Atoms with three valence electrons are called trivalent, and

those with five are called pentavalent.

Electronic Devices and Circuit Theory, 10/e 6 Copyright ©2009 by Pearson Education, Inc.
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 Covalent Bonding

Covalent bonding of Si crystal

This bonding of atoms, strengthened by the sharing of electrons,
is called covalent bonding
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 Covalent Bonding

There is sharing of
electrons, five electrons
provided by As atom and
three by the Ga atom.

Covalent bonding of GaAs crystal

Electronic Devices and Circuit Theory, 10/e 8 Copyright ©2009 by Pearson Education, Inc.
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Electronic Devices and Circuit Theory, 10/e 9 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Upper Saddle River, New Jersey 07458 • All rights reserved.
 Energy Levels

The farther an electron is from the nucleus, the higher is the

energy state.
Electronic Devices and Circuit Theory, 10/e 10 Copyright ©2009 by Pearson Education, Inc.
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 Energy Levels

An electron in the valence band of silicon must absorb more energy than
one in the valence band of germanium to become a free carrier. [free
carriers are free electrons due only to external causes such as applied
electric fields established by voltage sources or potential difference.
Electronic Devices and Circuit Theory, 10/e 11 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Upper Saddle River, New Jersey 07458 • All rights reserved.
 n-Type and p-Type materials
n-Type Material
n-Type materials are created by
adding elements with five valence
electrons such as antimony, arsenic,
and phosphorous.

There is a fifth electron due to

the (Sb) atom that is relatively free
to move in the n-Type material.

The atoms (in this case is

antimony (Sb)) are called donor
atoms.
Doping with Sb, (antimony)
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 n-Type and p-Type materials
n-Type Material

The free electrons due to the added atoms have higher energy
levels and require less energy to move to conduction band.

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Robert L. Boylestad and Louis Nashelsky Upper Saddle River, New Jersey 07458 • All rights reserved.
 n-Type and p-Type materials
p-Type Material p-Type materials are created by
adding atoms with three valence
electrons such as boron, gallium, and
indium.
In this case, an insufficient
number of electrons to complete the
covalent bonds.
The resulting vacancy is called a
“hole” represented by small circle or
plus sign indicating absence of a
negative charge.
The atoms (in this case boron(B))
Boron (B) are called acceptor atoms.
Electronic Devices and Circuit Theory, 10/e 14 Copyright ©2009 by Pearson Education, Inc.
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 Majority and Minority carriers
Two currents through a diode:
Majority Carriers
•The majority carriers in n-type materials are electrons.
•The majority carriers in p-type materials are holes.
Minority Carriers
•The minority carriers in n-type materials are holes.
•The minority carriers in p-type materials are electrons.

Electronic Devices and Circuit Theory, 10/e 15 Copyright ©2009 by Pearson Education, Inc.
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 p-n Junctions

One end of a silicon or germanium crystal can be doped as a p-

type material and the other end as an n-type material.

The result is a p-n junction.

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 p-n Junctions
At the p-n junction, the excess
conduction-band electrons on the
n-type side are attracted to the
valence-band holes on the p-type
side.

The electrons in the n-type

material migrate across the
junction to the p-type material
(electron flow).
The result is the formation of
The electron migration results in a a depletion region around
negative charge on the p-type side the junction.
of the junction and a positive
charge on the n-type side of the
junction.
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 Diodes
The diode is a 2-terminal device.

A diode ideally conducts in only

one direction.

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 • No bias
Diode Operating Conditions • Forward bias
• Reverse bias

Reverse bias Forward bias

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 Diode Operating Conditions
No Bias

• No external voltage is applied: VD = 0 V

• No current is flowing: ID = 0 A
• Only a modest depletion region exists

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 Diode Operating Conditions
Reverse Bias
External voltage is applied across the p-n junction in
the opposite polarity of the p- and n-type materials.

• The reverse voltage causes the

depletion region to widen.
• The electrons in the n-type material
are attracted toward the positive
terminal of the voltage source.
• The holes in the p-type material are
attracted toward the negative
terminal of the voltage source.

Electronic Devices and Circuit Theory, 10/e 21 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Upper Saddle River, New Jersey 07458 • All rights reserved.
 Diode Operating Conditions
Forward Bias
External voltage is applied across the p-n junction in
the same polarity as the p- and n-type materials.

• The forward voltage causes the

depletion region to narrow.
• The electrons and holes are pushed
toward the p-n junction.
• The electrons and holes have
sufficient energy to cross the p-n
junction.

Electronic Devices and Circuit Theory, 10/e 22 Copyright ©2009 by Pearson Education, Inc.
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 Actual Diode Characteristics
Note the regions for no
bias, reverse bias, and
forward bias conditions.
Carefully note the scale
for each of these
conditions.
The reverse saturation
current is seldom more
than a few microamperes.

Electronic Devices and Circuit Theory, 10/e 23 Copyright ©2009 by Pearson Education, Inc.
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Diode equation

where
VT : is called the thermal voltage.
Is : is the reverse saturation current.
VD : is the applied forward-bias voltage across the diode.
n : is a factor function of operation conditions and physical
construction. It has range between 1 and 2. assume n=1 unless
otherwise noted.
K : is Boltzman’s constant =1.38 x 10-23
T: is temperature in kelvins = 273+temperature in C.
q : is the magnitude of electron charge = 1.6 x 10-19 C.
Electronic Devices and Circuit Theory, 10/e 24 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Upper Saddle River, New Jersey 07458 • All rights reserved.
 Islamic University of Gaza
Chapter 1:
Semiconductor Diodes Dr. Talal Skaik
 Zener Region
The Zener region is in the diode’s reverse-bias region.
At some point the reverse bias voltage is so large the
diode breaks down and the reverse current increases
dramatically.
• The maximum reverse voltage
that won’t take a diode into the
zener region is called the peak
inverse voltage (PIV) or peak
reverse voltage (PRV).
• The voltage that causes a diode
to enter the zener region of
operation is called the zener
voltage (VZ).

Electronic Devices and Circuit Theory, 10/e 2 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
 Forward Bias Voltage
The point at which the diode changes from no-bias condition to
forward-bias condition occurs when the electrons and holes are
given sufficient energy to cross the p-n junction. This energy
comes from the external voltage applied across the diode.

The forward bias voltage required for a:

• gallium arsenide diode  1.2 V

• silicon diode  0.7 V
• germanium diode  0.3 V

Electronic Devices and Circuit Theory, 10/e 3 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
 Comparison Ge, Si, GaAs

Electronic Devices and Circuit Theory, 10/e 4 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
 Temperature Effects
As temperature increases it adds energy to the diode.
• It reduces the required forward bias voltage for forward-bias
conduction.
• It increases the amount of reverse current in the reverse-bias
condition.
Germanium diodes are more sensitive to temperature variations
than silicon or gallium arsenide diodes.

Electronic Devices and Circuit Theory, 10/e 5 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
 Temperature Effects

Electronic Devices and Circuit Theory, 10/e 6 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
 Resistance Levels
Semiconductors react differently to DC and AC currents.

There are three types of resistance:

• DC (static) resistance
• AC (dynamic) resistance
• Average AC resistance

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Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
 DC (Static) Resistance
For a specific applied DC voltage
VD, the diode has a specific current
ID, and a specific resistance RD.

VD
RD 
ID

Electronic Devices and Circuit Theory, 10/e 8 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
 AC (Dynamic) Resistance
The dynamic resistance is the resistance
offered by the diode to the AC signal. Is is
equal to the slope of the VI characteristics
(dV/dI or ΔV/ ΔI ) ,

change in voltage dV V
rD   
resulting change in current dI I

Electronic Devices and Circuit Theory, 10/e 9 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
 AC (Dynamic) Resistance
sin ce I D  I s e  V D / nV T
-1 , 
dI D

I s V D / nVT
dV D nV T
e

dI D 1 dI D ID
  I D  I s  , sin ce I D  I s , 
dV D nV T dV D nV T
dV D nV T
 rD 
dI D ID
for n=1, and at room temperature of 27o C, T=273+27=300K

VT 
KT

1.38 10 
 26mV
23

q 1.6 1019
26mV
rD 
ID
Electronic Devices and Circuit Theory, 10/e 10 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
 AC (Dynamic) Resistance
26 mV
In the forward bias region: rd   rB
ID
• The resistance depends on the amount of current (ID) in the diode.
• rD = 26 mV/ID is the resistance of the p-n junction and does not
include the resistance of the semiconductor material itself (the body
resistance).
• rB is added to account for body resistance and it ranges from a
typical 0.1  to 2 .

In the reverse bias region:

rd  
The resistance is effectively infinite. The diode acts like an open.
Electronic Devices and Circuit Theory, 10/e 11 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
 Average AC Resistance

ΔVd
rav  pt. to pt.
ΔId

AC resistance can be
calculated using the current
and voltage values for two
points on the diode
characteristic curve.

Electronic Devices and Circuit Theory, 10/e 12 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
 Diode Equivalent Circuit

Electronic Devices and Circuit Theory, 10/e 13 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
 Diode Specification Sheets
Data about a diode is presented uniformly for many different diodes.

1. Forward Voltage (VF) at a specified current and temperature

2. Maximum forward current (IF) at a specified temperature
3. Reverse saturation current (IR) at a specified voltage and
temperature
4. Reverse voltage rating, PIV or PRV or V(BR), at a specified
temperature
5. Maximum power dissipation at a specified temperature
6. Capacitance levels
7. Reverse recovery time, trr (is the time required for a diode to stop
conducting once it is switched from forward bias to reverse bias)
8. Operating temperature range

Electronic Devices and Circuit Theory, 10/e 14 Copyright ©2009 by Pearson Education, Inc.
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 Diode
Specification
Sheets

Electronic Devices and Circuit Theory, 10/e 15 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
 Diode Symbol and Packaging

The anode is abbreviated A

The cathode is abbreviated K

Electronic Devices and Circuit Theory, 10/e 16 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
 Diode Testing - Ohmmeter
An ohmmeter set on a low Ohms scale can be used
to test a diode. The diode should be tested out of
circuit.

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Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
 Other Types of Diodes
Zener diode
Light-emitting diode
Diode arrays

Electronic Devices and Circuit Theory, 10/e 18 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
 Zener Diode
•A Zener diode is a type of diode that permits current
not only in the forward direction like a normal diode,
but also in the reverse direction if the voltage is larger
than the breakdown voltage known as "Zener voltage“
(VZ).
•Common Zener voltages are between 1.8 V and 200 V.
•Zener diode is used as regulator (circuits will be shown
in chapter 2).

Electronic Devices and Circuit Theory, 10/e 19 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
 Light-Emitting Diode (LED)
•An LED emits photons when it is forward biased.
•These can be in the infrared or visible spectrum.
•The forward bias voltage is usually in the range of 2 V to 5 V.
Light-Emitting Diodes
Color Construction Typical Forward
Voltage (V)
Amber AlInGaP 2.1
Blue GaN 5.0
Green GaP 2.2
Orange GaAsP 2.0
Red GaAsP 1.8
White GaN 4.1
Yellow AlInGaP 2.1

Electronic Devices and Circuit Theory, 10/e 20 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
 Diode Arrays
Multiple diodes can be
packaged together in an
integrated circuit (IC). Common Anode

A variety of combinations
exist.
Common Cathode

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Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
 11/22/2023

Learning Objectives
IN THIS CHAPTER WE WILL LEARN:
 The characteristics of ideal diode

Chapter 2:  The details of i-v characteristics of the junction diode and how to use

Semiconductor Diodes and Their Application it to analyze diode circuits operating in the various bias regions:

B y : B e h a i l u T. forward, reverse, and breakdown

 Different models of diode
 A highlight of different categories of diode
 Application of the diode in rectifier circuits
DECE, COEME, AASTU 2

Outline Introduction: Ideal Diode

 Introduction  Ideal Diode is a most fundament nonlinear circuit

 Ideal Vs. Practical characteristics of diode element

 Two terminal device made of p-type and n- +
 Types of diodes
type semiconductor materials
 Applications of diode -
 Conduct electric current in one direction
 Special circuits involving diodes only
 Limiting Circuits
 The two terminals are called anode (+) and
 Clamping Circuits Fig.2.1: pn-structure and
cathode (-)
 Voltage Doupler circuit symbol of ideal diode

DECE, COEME, AASTU 3 DECE, COEME, AASTU 4

 11/22/2023

Ideal Diode : I-V Characteristics Practical Characteristics of Diodes

Ideal diode circuit symbol  Equivalent Ckt in the FB
ID  Most common implementation
i ID > 0,
Anode D Cathode
VD = 0, of a diode utilizes pn junction.
NB: The biasing VD
vD R=0
source is not
shown here  I-V curve consists of three
ID
 Equivalent Ckt in the RB characteristic regions
Forward Bias
ID ID = 0, ◦ Forward bias: v > 0
Reverse Bias (FB) VD < 0, ◦ Reverse bias: v < 0
(RB) VD R =∞ ◦ Breakdown: v << 0
0 VD discontinuity caused by
DECE, COEME, AASTU 5 differences in scale 6

The Forward-Biased Region The Forward-Biased Region

IS  constant for diode at given
 The forward-bias region of operation is entered temperature (aka. saturation current)  Equation (4.3) may be reversed to
when v > 0.

yield (4.4).
(eq4.1) i  IS (ev / VT  1) IS  constant for diode at given
 I-V relationship is closely approximated by  This relationship applies over as
temperature (aka. saturation current)

equations: VT  thermal voltage
k  Boltzmann's constant (8.62E -5 eV/K)
q  magnitude of electron charge (1.6E -19 C)
many as seven decades of current.  i 
 (eq4.4) v  VT ln  
kT
(eq4.2) VT   25.8 m
V  IS 
q  
at room
temperature
IS  constant for diode at given
(4.3) is a simplification temperature (aka. saturation current)

suitable for large v (eq4.3) i  IS ev / VT
DECE, COEME, AASTU 7 DECE, COEME, AASTU 8
 11/22/2023

step #1: consider two cases (#1 and #2)

  
I1  IS eV1 / VT and I2  IS eV2 / VT
step #2: divide I2 by I1
The Forward-Biased Region  The Forward-Biased Region
I2 IS eV2 / VT
Q: What is the relative effect of 
I1 IS eV1 / VT  Cut-in voltage – is voltage, below
current flow (i) on forward biasing step #3: combine two exponentials which, minimal current flows Cut-in voltage
voltage (v)?   
I2 (V2 V1 ) / VT
◦ approximately 0.5V
A: Very small. e
I1  Fully conducting region – is region
◦ 10x change in i, effects 60mV
change in v.
step #4: invert this expression
   in which Rdiode ≈ 0.
V2  V1  VT ln  I2 / I1  ◦ between 0.6 and 0.8V
step #5: convert to log base 10
  
V2  V1  2.3VT log  I2 / I1 

60 mV 2.3VT log10 / 1

DECE, COEME, AASTU 9 DECE, COEME, AASTU

fully conducting region
10

The Reverse-Biased Region The Reverse-Biased Region

this expression
applies for
 The reverse-bias region of operation negative voltages  A “real” diode exhibits reverse-

is entered when v < 0. i  IS e  v / VT bias current, although small,
action: invert exponential much larger than IS .
 I-V relationship, for negative  
◦ 10-9 vs. 10-14Amps
 1 
voltages with |v| > VT (25mV), is i  I S  v / V 
e   A large part of this reverse

T

closely approximated by equations 

0 for larger
voltage
current is attributed to leakage
to right. magnitudes
effects.
i  IS
DECE, COEME, AASTU 11 DECE, COEME, AASTU
Reverse biased region12
 11/22/2023

i  IS (ev / VT  1)

The Breakdown Region i << - i=- i≈ i= ⁄

 The breakdown region of

operation is entered when
v < VZK.
◦ Zener-Knee Voltage (VZK)
 This is normally non-
destructive.

V = -VZK V = -VT V ≈ 10VT

DECE, COEME, AASTU
breakdown region 13
Oxford University Publishing
Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)
DECE, COEME, AASTU 14

Modeling Diode Forward Characteristics The Exponential Diode Model

 The previous slides define a robust set of diode models.
 Most accurate
 Upcoming slides, however, discuss simplified diode models better
suited for use in circuit analyses:  Most difficult to employ in circuit analysis
◦ Exponential model
◦ Constant voltage-drop model ◦ due to nonlinear nature
◦ Ideal diode model
◦ Small-signal (linearization) model (eq4.6) ID  IS eVD / VT
 
VD  voltage across diode
ID  current through diode

DECE, COEME, AASTU 15 DECE, COEME, AASTU 16

 11/22/2023

The Exponential Diode Model Graphical Analysis Using Exponential Model

Q: How does one solve for ID in Step #1: Plot the relationships of eq(4.6)
circuit to right?
◦ VDD = 5V and (4.7) on single graph
◦ R = 1kOhm Step #2: Find intersection of the two…
A: Two methods exist… Fig.2.3: A simple circuit used to
◦ load line and diode characteristic
◦ Graphical method illustrate the analysis of circuits
◦ Iterative method in which the diode is forward intersect at operating point
conducting. Fig.2.4: Graphical analysis of the circuit in
previous slide using the exponential diode
V V
(eq4.7) ID  DD D model.
R
DECE, COEME, AASTU 17 DECE, COEME, AASTU 18

Graphical Analysis Using Exponential Model Iterative Analysis Using Exponential Model
Pro’s
Step #1: Start with initial guess of VD. step #4: Repeat these steps
 Intuitive ◦ VD(0) until VD(k+1) = VD(k).
◦ b/c of visual nature ◦ Upon convergence, the
Step #2: Use nodal / mesh analysis new and old values of VD
Con’s to solve ID. will match.
 Poor Precision Step #3: Use exponential model to
 Not Practical for complex update VD.
analyses
Fig.2.4: Graphical analysis of the circuit in
previous slide using the exponential diode
◦ VD(1) = f(VD(0))
model.
◦ multiple lines required
DECE, COEME, AASTU 19 DECE, COEME, AASTU 20
 11/22/2023

Iterative Analysis Using Exponential Model Reading Assignment

Pro’s
 High Precision ◦ Constant voltage-drop model
◦ Ideal diode model
Con’s ◦ Small-signal (linearization) model
 Not Intuitive
 Not Practical for Complex Analyses
◦ 10+ iterations may be required

DECE, COEME, AASTU 21 DECE, COEME, AASTU 22

Diode types : based on applications used for Diode types

 Signal diodes  Rectifier diodes
o small in size  Diodes used for different applications
o large in size
o low forward current rating  PIN Diodes
o can withstand high values of  Zener Diode
o low forward voltage drop reverse voltage and large
 Mostly used in : values of forward current  Light-Emitting Diode (LED)  Schottky Diodes
 lower voltage/lower current  Used in:
electronic circuits.
 power supply circuits (e.g.  Photo Diode  Laser Diodes
 high frequency applications rectifiers).
 clipping and switching applications  Varactor Diodes  Etc…
with short-duration pulse
waveforms  Tunnel Diodes Separate document is available for students
for review
DECE, COEME, AASTU 23 DECE, COEME, AASTU 24
 11/22/2023

DECE, COEME, AASTU 25 DECE, COEME, AASTU 26

Some Application Areas Diodes used: Rectifier Circuits

 Rectifiers in power supplies : Si diodes  One important application of diode is the rectifier –
◦ Part of dc power supply which converts alternating
 Switches in logical circuits current (AC) to direct current (DC).
 Signal Detectors in radio receiver: Ge diodes
 Voltage regulators in regulated power supplies : Si Zener diodes
 Oscillator – amplifiers in microwave equipment: Tunnel diodes

Block diagram of a dc power supply

DECE, COEME, AASTU 27 DECE, COEME, AASTU 28

 11/22/2023

step #1: decrease magnitude of AC voltage wave

via power transformer
step #2: convert full-wave AC to half-wave AC
(still time-varying and periodic)
The Half-Wave Rectifier
step #3: employ low-pass filter to reduce wave
amplitude by > 90%  Half-wave rectifier – utilizes
Block only alternate half-cycles of
step #4: employ voltage regulator to eliminate
diagram of a the input sinusoid
ripple
dc power
step #5: supply dc load
◦ Constant voltage drop
supply
. diode model is employed.

220V
50Hz

Fig. (a) Half-wave rectifier (b) Transfer characteristic of the rectifier

DECE, COEME, AASTU 29 circuit (c) Input and output waveforms
DECE, COEME, AASTU 30

The Half-Wave Rectifier The Half-Wave Rectifier

Two important parameters in selecting diodes for rectifier  Exponential model? It is possible to use the diode
design: exponential model in describing rectifier operation;
 Current-handling capability – what is maximum forward however, this requires too much work.
current diode is expected to conduct?  Small inputs? Regardless of the model employed, one
 Peak inverse voltage (PIV) – what is maximum reverse should note that the rectifier will not operate properly
voltage it is expected to block w/o breakdown? when input voltage is small (< 1V).
◦ Those cases require a precision rectifier.

DECE, COEME, AASTU 31 DECE, COEME, AASTU 32

 11/22/2023

The Full-Wave Rectifier

Q: How does full-wave The key here is
rectifier differ from half- center-tapping of
wave? the transformer,
◦A: It utilizes both allowing
halves of the input “reversal” of
◦ One potential is shown certain currents…
to right.

Full-wave rectifier utilizing a transformer Full-wave rectifier utilizing a transformer with a center-tapped secondary winding: (a) circuit; (b) transfer
with a center-tapped secondary winding. characteristic assuming a constant-voltage-drop model for the diodes; (c) input and output waveforms.

DECE, COEME, AASTU 33 DECE, COEME, AASTU 34

When instantaneous source voltage is positive, D1 when instantaneous source voltage is negative, D2
conducts while D2 blocks… conducts while D1 blocks

DECE, COEME, AASTU 35 DECE, COEME, AASTU 36

 11/22/2023

The Full-Wave Rectifier The Bridge Rectifier

Q: What are most important observation(s) from this  Most practically used
operation? implementation of the
A: full-wave rectifier is
 The direction of current flowing across load never bridge rectifier.
changes (both halves of AC wave are rectified).
 The full-wave rectifier produces a more “energetic”
waveform than half-wave. The bridge rectifier circuit.
 PIV for full-wave = 2VS – VD

DECE, COEME, AASTU 37 DECE, COEME, AASTU 38

when instantaneous source voltage is positive, D1 when instantaneous source voltage is negative, D3
and D2 conduct while D3 and D4 block and D4 conduct while D1 and D2 block

The bridge rectifier circuit. The bridge rectifier circuit.

DECE, COEME, AASTU 39 DECE, COEME, AASTU 40

 11/22/2023

The Bridge Rectifier (BR) The Rectifier with a Filter Capacitor

Q: What is the main advantage of BR?  Pulsating nature of
◦A: No need for center-tapped transformer. rectifier output makes
unreliable dc supply.
Q: What is main disadvantage?
◦A: Series connection of TWO diodes will reduce output  As such, a filter capacitor
voltage. is employed to remove
ripple.
PIV = VS – VD

Fig a) A simple circuit used to illustrate the effect of a

filter capacitor. (b) input and output waveforms
DECE, COEME, AASTU 41 DECE, COEME, AASTU assuming an ideal diode. 42

The Rectifier with a Filter Capacitor The Rectifier with a Filter Capacitor
step #1: source voltage is positive,
diode is forward biased, capacitor Q: Why is this example unrealistic?
charges.
◦A: Because for any practical application, the converter
step #2: source voltage is reverse,
diode is reverse-biased (blocking), would supply a load (which in turn provides a path for
capacitor cannot discharge.
step #3: source voltage is positive,
capacitor discharging).
diode is forward biased, capacitor
charges (maintains voltage).

Fig. (a) A simple circuit used to illustrate the effect…

DECE, COEME, AASTU 43 DECE, COEME, AASTU 44
 11/22/2023

The Rectifier
The Rectifier with a Filter Capacitor with a Filter Capacitor
Q: What happens when load The textbook outlines how Laplace
resistor is placed in parallel Transform may be used to define
with capacitor? behavior below.
circuit state #1
◦A: One must now consider output voltage for state #1

the discharging of vO  t   vI t   vD
capacitor across load. 
t
vO  t   Vpeak e RC

output voltage for state #2

circuit state #2: source free

DECE, COEME, AASTU 45 DECE, COEME, AASTU 46

Q: What happens when load resistor is Q: What happens when load resistor is placed in parallel with
placed in parallel with capacitor? capacitor?

 step #1: Analyze circuit state #1. step #3: Define output voltage
◦ When diode is forward biased and for state #1.
conducting. circuit state #1
 step #2: Input voltage (vI) will be vO
iL 
applied to output (vO), minus 0.7V R output voltage for state #1

drop across diode.
vO  vI  vD
iD  iC  iL circuit state #1
action: define capacitor
current differentially

 
dv0I
iD  C  iL
dt
DECE, COEME, AASTU 47 DECE, COEME, AASTU 48
 11/22/2023

Q: What happens when load resistor is placed in parallel with Q: What happens when load resistor is placed in parallel with
capacitor? capacitor?
step #4: Analyze circuit state #2. step #6: Use combination of circuit and Laplace Analysis to
◦ When diode is blocking and solve for vO(t) in terms of initial condition and time…
capacitor is discharging.
step #5: Define KVL and KCL for
this circuit.
◦ vO = RiL
◦ iL = –iC
circuit state #2:
source free

DECE, COEME, AASTU 49 DECE, COEME, AASTU 50

The Rectifier with a Filter Capacitor The Rectifier with a Filter Capacitor
action: take Laplace transform
    
action: eliminate RC from both sides

1 
vO  RiL 
L vO  RC O  0 
dv  
RC  s  VO  s   RCVO  0  Q: What is VO(0)?
 dt   RC 
action: replace
iL with -iC action: solve for VO  s 
  action: take Laplace transform 
vO  RiC

1 ◦A: Peak of vI, because the transition between state #1 and
VO  s   RC  sVO  s   VO  0    0 VO  s   VO  0 
action: define iC  1
s
differentially
 transform of O
dv
dt RC state #2 (aka. diode begins blocking) approximately as vI
 dv  action: seperate disalike / collect alike terms
vO  R  C O      action: take inverse Laplace

dt V  s   RCsV  s   RC V  0 

 
O O
 O 
1 
L VO  s   VO  0 
1  drops below vC.
iC
1RCs VO ( s ) initial 
action: change sides condition  s  1/  RC  
  action: pull out RC
dv   
action: solve
vO  RC O  0 
1  RCs VO  s   RCVO  0 
dt   
t
 1 
RC  s VO ( s ) vO  t   VO  0  e RC
 RC 

DECE, COEME, AASTU 51 DECE, COEME, AASTU 52

 11/22/2023

output voltage for state #1

  
The Rectifier vO  t   v I  t 
with a Filter Capacitor 
t
vO  t   Vpeak e RC

step #7: Define output voltage for output voltage for state #2
states #1 and #2.
circuit state #1

output voltage for state #1


vO  t   vI t   vD
t

vO  t   Vpeak e RC
 Fig.: Voltage and Current Waveforms in the Peak Rectifier Circuit
output voltage for state #2 circuit state #2 WITH RC >> T. The diode is assumed ideal.
DECE, COEME, AASTU 53 DECE, COEME, AASTU 54

A Couple of Observations A Couple of Observations

 The diode conducts for a brief interval (Dt) near the peak of the  During the diode off-interval, the capacitor C discharges through R
input sinusoid and supplies the capacitor with charge equal to that causing an exponential decay in the output voltage (vO). At the end
lost during the much longer discharge interval. The latter is of the discharge interval, which lasts for almost the entire period T,
approximately equal to T. voltage output is defined as follows – vO(T) = Vpeak – Vr.
 Assuming an ideal diode, the diode conduction begins at time t1 (at  When the ripple voltage (Vr) is small, the output (vO) is almost
which the input vI equals the exponentially decaying output vO). constant and equal to the peak of the input (vI). the average
Diode conduction stops at time t2 shortly after the peak of vI (the output voltage may be defined as below…
exact value of t2 is determined by settling of ID).
1
(eq4.27) avg VO   Vpeak  Vr  Vpeak if Vr is small
2

DECE, COEME, AASTU 55 DECE, COEME, AASTU 56

 11/22/2023

The Rectifier with a 

t

Filter Capacitor vO t   Vpeak e RC

The Rectifier with a Filter Capacitor
T is discharge interval
 
Q: How is ripple voltage (Vr) defined? Vpeak  Vr  vO (T ) step #5: Put expression in terms of
Vpeak
 step #1: Begin with transient response of frequency (f = 1/T).
  
T
◦ Observe that, as long as Vr << Vpeak, R
output during “off interval.” Vpeak  Vr  Vpeak   e  RC
IL Vpeak
 step #2: Note T is discharge interval.  the capacitor discharges as constant (eq4.29) Vr  
because RC T , current source (IL). fRC fC
 step #3: Simplify using assumption that we can assume...
T
 T
RC >> T. e RC  1
RC Q: How is conduction interval (Dt)
 step #4: Solve for ripple voltage Vr. action: solve for
ripple voltage Vr
defined?
 
◦ A: See following slides…
 T  expression to define
(eq4.28) Vr  Vpeak  
RC 
T
ripple voltage (Vr)
1 1
RC
DECE, COEME, AASTU 57 DECE, COEME, AASTU 58

cos(0O)
Q: How is conduction The Rectifier
interval (Dt) defined? with a Filter Capacitor
Vpeak
step #1: Assume that diode
conduction stops (very close to Q: How is peak-to-peak R
ripple (Vr) defined? VpeakIL
when) vI approaches its peak. (eq4.29) Vr  
Vpeak cos wDt   Vpeak  Vr ◦A: (4.29) fRC fC
step #2: With this assumption, 
one may define expression to note that peak of vI represents cos(0O ), Q: How is the conduction
therefore coswDt  represents variation
the right. around this value interval (Dt) defined?
◦A: (4.30) (eq4.30) wDt  2Vr / Vpeak
step #3: Solve for wDt. (eq4.30) wDt  2Vr / Vpeak   
   as assumed, conduction
interval Dt will be small
as assumed, conduction when Vr Vpeak
interval Dt will be small
when Vr Vpeak

DECE, COEME, AASTU 59 DECE, COEME, AASTU 60

 11/22/2023

The Rectifier with low-voltage input waveforms Limiting/Clipper Circuit (1/2)

Precision rectifier – is a device which facilitates rectification  used to clip off portions of signal voltages above or below certain
of low-voltage input waveforms. levels.
1) Limiting of the positive alternation: The diode is forward-biased
during the positive alternation (above 0.7 V) and reverse-biased
during the negative alternation.

Fig: The “Superdiode” Precision Half-Wave Rectifier and its almost-ideal transfer
characteristic.
DECE, COEME, AASTU 61 DECE, COEME, AASTU 62

Limiting/Clipper Circuit (2/2) Clamping Circuits

2) Limiting of the negative alternation: The diode is forward-biased ◦used to add or restore a dc level to an electrical signal.
during the negative alternation (below –0.7 V) and reverse-biased
during the positive alternation.

DECE, COEME, AASTU 63 DECE, COEME, AASTU 64

 11/22/2023

Clamping Circuits Voltage Doubler

◦used to add or restore a dc level to an electrical signal. Q: What is a voltage doubler?
◦A: One which multiplies the
amplitude of a wave or signal
by two.

Fig: Voltage doubler: (a) circuit; (b)

waveform of the voltage across D1.
DECE, COEME, AASTU 65 DECE, COEME, AASTU 66

Summary (1) Summary (2)

 In the forward direction, the ideal diode conducts any current  A silicon diode conducts a negligible current until the forward
forced by the external circuit while displaying a zero-voltage drop. voltage is at least 0.5V. Then, the current increases rapidly with
The ideal diode does not conduct in reverse direction; any applied the voltage drop increasing by 60mV for every decade of current
voltage appears as reverse bias across the diode. change.
 The unidirectional current flow property makes the diode useful in  In the reverse direction, a silicon diode conducts a current on the
the design of rectifier circuits. order of 10-9A. This current is much greater than IS and increases
 The forward conduction of practical silicon-junction diodes is with the magnitude of reverse voltage.
accurately characterized by the relationship i = ISeV/VT.

DECE, COEME, AASTU 67 DECE, COEME, AASTU 68

 11/22/2023

Summary (3) Summary (4)

 In many applications, a conducting diode is modeled as having a
 Beyond a certain value of reverse voltage (that depends on the
constant voltage drop – usually with value of approximately 0.7V.
diode itself), breakdown occurs and current increases rapidly with
a small corresponding increase in voltage.  A diode biased to operate at a dc current ID has small signal
resistance rd = VT/ID.
 Diodes designed to operate in the breakdown region are called
zener diodes. They are employed in the design of voltage  Rectifiers covert ac voltage into unipolar voltages. Half-wave
regulators whose function is to provide a constant dc voltage that rectifiers do this by passing the voltage in half of each cycle and
varies little with variations in power supply voltage and / or load blocking the opposite-polarity voltage in the other half of the cycle.
current.

DECE, COEME, AASTU 69 DECE, COEME, AASTU 70

Summary (5) Summary (6)

 The bridge-rectifier circuit is the preferred full-wave rectifier  Combination of diodes, resistors, and possible reference voltage
configuration. can be used to design voltage limiters that prevent one or both
extremities of the output waveform from going beyond
 The variation of the output waveform of the rectifier is reduced predetermined values – the limiting levels.
considerably by connecting a capacitor C across the output load
resistance R. The resulting circuit is the peak rectifier. The output  Applying a time-varying waveform to a circuit consisting of a
waveform then consists of a dc voltage almost equal to the peak of capacitor in series with a diode and taking the output across the
the input sine wave, Vp, on which is superimposed a ripple diode provides a clamping function.
component of frequency 2f (in the full-wave case) and of peak-to-  By cascading a clamping circuit with a peak-rectifier circuit, a
peak amplitude Vr = Vp/2fRC. voltage doubler is realized.
DECE, COEME, AASTU 71 DECE, COEME, AASTU 72
 11/22/2023

Summary (7) References

 Beyond a certain value of reverse voltage (that depends on the 1. Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith
diode itself), breakdown occurs and current increases rapidly with 2. Oxford University Publishing teaching materials (with permission for teaching
a small corresponding increase in voltage. purpose)

 Diodes designed to operate in the breakdown region are called 3. Microelectronic Devices and Circuits by Clifton G. Fonstand
zener diodes. They are employed in the design of voltage
regulators whose function is to provide a constant dc voltage that
varies little with variations in power supply voltage and / or load
current.

DECE, COEME, AASTU 73 DECE, COEME, AASTU 74

Chapter 2: Islamic University of Gaza
Diode Applications Dr. Talal Skaik
 Diode Applications

Diodes are used in many applications:

(a) Rectifiers
(b) Clippers or Limiters
(c) Clampers
(d) Voltage Multipliers

Dr. Talal Skaik 2014

Electronic Devices and Circuit Theory, 10/e Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky 2 Upper Saddle River, New Jersey 07458 • All rights reserved.
Sinusoidal Inputs: Half-Wave Rectification

Half-wave Rectifier

Dr. Talal Skaik 2014

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Robert L. Boylestad and Louis Nashelsky 3 Upper Saddle River, New Jersey 07458 • All rights reserved.
Sinusoidal Inputs: Half-Wave Rectification
For t= 0  T/2, the diode is on.
Diode is substituted with short-circuit equivalence for ideal diode
(reduce complexity).

Conduction region (0  T/2).

Dr. Talal Skaik 2014
Electronic Devices and Circuit Theory, 10/e Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky 4 Upper Saddle River, New Jersey 07458 • All rights reserved.
Sinusoidal Inputs: Half-Wave Rectification
For the period T/2  T, the diode is off.
Diode is substituted with an open circuit.

Nonconduction region (T/2  T).

Dr. Talal Skaik 2014

Electronic Devices and Circuit Theory, 10/e Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky 5 Upper Saddle River, New Jersey 07458 • All rights reserved.
Sinusoidal Inputs: Half-Wave Rectification

VDC=0.318 Vm

The DC output voltage is 0.318Vm, where Vm = the peak AC voltage.

Dr. Talal Skaik 2014

Electronic Devices and Circuit Theory, 10/e Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky 6 Upper Saddle River, New Jersey 07458 • All rights reserved.
Sinusoidal Inputs: Half-Wave Rectification
The effect of using a silicon diode with VK=0.7 is shown.
The diode is “on” when the applied signal is at least 0.7 V.

vo= vi –vK
For Vm>>Vk : VDC≈0.318 (Vm-VK)

Dr. Talal Skaik 2014

Electronic Devices and Circuit Theory, 10/e Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky 7 Upper Saddle River, New Jersey 07458 • All rights reserved.
 Example 2.16
a) Sketch dc output vo and determine the dc level of the output.
b) Repeat (a) if the ideal diode is replaced by silicon diode.

Dr. Talal Skaik 2014

Electronic Devices and Circuit Theory, 10/e Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky 8 Upper Saddle River, New Jersey 07458 • All rights reserved.
 Example 2.16 - Solution
VDC=-0.318 Vm
(a) VDC=-0.318 (20)
VDC=-6.36 V

(b)
VDC=-0.318 (Vm- 0.7)
VDC=-0.318 (19.3)
VDC=-6.14 V

Dr. Talal Skaik 2014

Electronic Devices and Circuit Theory, 10/e Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky 9 Upper Saddle River, New Jersey 07458 • All rights reserved.
 PIV (PRV)
Because the diode is only forward biased for one-half of the AC
cycle, it is also reverse biased for one-half cycle.

It is important that the reverse breakdown voltage rating of the

diode be high enough to withstand the peak, reverse-biasing AC
voltage and avoid entering the Zener region.

PIV (or PRV) > Vm

• PIV = Peak inverse voltage
• PRV = Peak reverse voltage
• Vm = Peak AC voltage

Dr. Talal Skaik 2014

Electronic Devices and Circuit Theory, 10/e Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky 10 Upper Saddle River, New Jersey 07458 • All rights reserved.
 Full-Wave Rectification
The rectification process can be improved by using a full-wave
rectifier circuit.

Full-wave rectification produces a greater DC output:

• Half-wave: Vdc = 0.318Vm

• Full-wave: Vdc = 0.636Vm

Dr. Talal Skaik 2014

Electronic Devices and Circuit Theory, 10/e Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky 11 Upper Saddle River, New Jersey 07458 • All rights reserved.
Full-Wave Rectification – Bridge Network

Network for the period 0  T/2

of the input voltage vi

Dr. Talal Skaik 2014

Electronic Devices and Circuit Theory, 10/e Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky 12 Upper Saddle River, New Jersey 07458 • All rights reserved.
Full-Wave Rectification – Bridge Network

Conduction path for the positive region of vi

Conduction path for the negative region of vi

Dr. Talal Skaik 2014
Electronic Devices and Circuit Theory, 10/e Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky 13 Upper Saddle River, New Jersey 07458 • All rights reserved.
Full-Wave Rectification – Bridge Network

The DC level is now twice that of half wave rectifier=2(0.318Vm)

VDC=0.636Vm

Dr. Talal Skaik 2014

Electronic Devices and Circuit Theory, 10/e Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky 14 Upper Saddle River, New Jersey 07458 • All rights reserved.
Full-Wave Rectification – Bridge Network
If silicon diode is used, vi –VK – vo - VK=0
vo = vi - 2VK

Vo max= Vm - 2VK
For Vm>>2Vk : VDC≈0.636 (Vm - 2VK)
Dr. Talal Skaik 2014
Electronic Devices and Circuit Theory, 10/e Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky 15 Upper Saddle River, New Jersey 07458 • All rights reserved.
 Full-Wave Rectification
Center Tapped Transformer Rectifier

VDC=0.636Vm

Electronic Devices and Circuit Theory, 10/e Dr. Talal Skaik 2014 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky 16 Upper Saddle River, New Jersey 07458 • All rights reserved.
 Center Tapped Transformer Rectifier

Network conditions for the positive region of vi

Network conditions for the negative region of vi

Dr. Talal Skaik 2014
Electronic Devices and Circuit Theory, 10/e Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky 17 Upper Saddle River, New Jersey 07458 • All rights reserved.
 Summary of Rectifier Circuits
Rectifier Ideal VDC Realistic VDC

Half Wave Rectifier VDC = 0.318Vm VDC = 0.318(Vm – 0.7)

Bridge Rectifier VDC = 0.636Vm VDC = 0.636(Vm – 2(0.7))

Center-Tapped Transformer
VDC = 0.636Vm VDC = 0.636(Vm – 0.7 )
Rectifier

Vm = peak of the AC voltage.

In the center tapped transformer rectifier circuit, the peak AC voltage

is the transformer secondary voltage to the tap.

Dr. Talal Skaik 2014

Electronic Devices and Circuit Theory, 10/e Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky 18 Upper Saddle River, New Jersey 07458 • All rights reserved.
Example 2.17
Determine the output
waveform for the network
and calculate the output
dc level.
Solution

Network for the positive region of vi

Dr. Talal Skaik 2014
Electronic Devices and Circuit Theory, 10/e Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky 19 Upper Saddle River, New Jersey 07458 • All rights reserved.
Example 2.17 - Solution

vo=(1/2) vi
Vomax=(1/2) Vimax =(1/2) 10=5V
VDC=0.636(5V)=3.18 V.

For the negative part the roles of

the diodes are interchanged and
Resulting output
vo appears as shown in figure.
Dr. Talal Skaik 2014
Electronic Devices and Circuit Theory, 10/e Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky 20 Upper Saddle River, New Jersey 07458 • All rights reserved.
Full Wave Rectifier with Smoothing Capacitor
(AC to DC Converter)

Dr. Talal Skaik 2014

Electronic Devices and Circuit Theory, 10/e Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky 21 Upper Saddle River, New Jersey 07458 • All rights reserved.
Chapter 2: Islamic University of Gaza
Diode Applications Dr. Talal Skaik
Load-Line Analysis (graphical solution)
The analysis of diode can follow one of two paths: using the
actual characteristics or applying an approximate model for the
device.
Load Line Analysis: is used to analyze diode circuit using its
actual characteristics.

Dr. Talal Skaik 2014

Electronic Devices and Circuit Theory, 10/e Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky 2 Upper Saddle River, New Jersey 07458 • All rights reserved.
Load-Line Analysis (graphical solution)

•A straight line is defined by the parameters of the network.

•It is called the load line because the intersection on the vertical
axes is defined by the applied load R.
Dr. Talal Skaik 2014
Electronic Devices and Circuit Theory, 10/e Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky 3 Upper Saddle River, New Jersey 07458 • All rights reserved.
 Load-Line Analysis (graphical solution)

•The maximum ID equals E/R, and the maximum VD equals E.

•The point where the load line and the characteristic curve intersect
is the Q-point, which identifies ID and VD for a particular diode in a
given circuit.
Dr. Talal Skaik 2014
Electronic Devices and Circuit Theory, 10/e Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky 4 Upper Saddle River, New Jersey 07458 • All rights reserved.
 Example 2.1
For the given diode configuration and diode characteristics,
determine: VDQ , IDQ and VR.

Dr. Talal Skaik 2014

Electronic Devices and Circuit Theory, 10/e Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky 5 Upper Saddle River, New Jersey 07458 • All rights reserved.
 Example 2.1 - Solution

•The load line is firstly drawn between VD=E=10 V and

ID=E/R=10/0.5k=20mA. The intersection between the load line and
characteristics defines the Q-point as VDQ=0.78 and IDQ=18.5mA.
•VR=IDQ R=(18.5mA)(1K)=18.5 V.
Dr. Talal Skaik 2014
Electronic Devices and Circuit Theory, 10/e Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky 6 Upper Saddle River, New Jersey 07458 • All rights reserved.
 Diode Configurations
The forward resistance of the diode is usually so small
compared to the other series elements of the network that it can
be ignored.
In general, a diode is in the “on” state if the current
established by the applied sources is such that its direction
matches that of the arrow in the diode symbol, and VD≥0.7V for
silicon, VD≥0.3V for germanium, and VD≥1.2V for gallium
arsenide.
You may assume the diode is “on”, and then find the current
in the diode. If the current flows into the positive terminal of the
diode, then the assumption is right, otherwise, the diode is “off”.
Dr. Talal Skaik 2014
Electronic Devices and Circuit Theory, 10/e Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky 7 Upper Saddle River, New Jersey 07458 • All rights reserved.
Series Diode Configurations
Forward Bias

Constants
• Silicon Diode: VD = 0.7 V
• Germanium Diode: VD = 0.3 V

Analysis (for silicon)

• VD = 0.7 V (or VD = E if E < 0.7 V)
• VR = E – VD
• ID = IR = IT = VR / R= (E-VD) / R

Equivalent circuit for the “on” diode

Dr. Talal Skaik 2014
Electronic Devices and Circuit Theory, 10/e Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky 8 Upper Saddle River, New Jersey 07458 • All rights reserved.
Series Diode Configurations
Reverse Bias
Diodes ideally behave as open circuits

Analysis
• VD = E
• VR = 0 V
• ID = 0 A

Equivalent circuit for the “off” diode

Dr. Talal Skaik 2014
Electronic Devices and Circuit Theory, 10/e Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky 9 Upper Saddle River, New Jersey 07458 • All rights reserved.
 Example 2.4
•Determine VD, VR and ID.

Dr. Talal Skaik 2014

Electronic Devices and Circuit Theory, 10/e Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky 10 Upper Saddle River, New Jersey 07458 • All rights reserved.
 Example 2.5
Determine VD, VR and ID.

Solution

Dr. Talal Skaik 2014

Electronic Devices and Circuit Theory, 10/e Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky 11 Upper Saddle River, New Jersey 07458 • All rights reserved.
 Source Notation

Dr. Talal Skaik 2014

Electronic Devices and Circuit Theory, 10/e Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky 12 Upper Saddle River, New Jersey 07458 • All rights reserved.
 Example 2.6
Determine VD, VR and ID.
Solution

Dr. Talal Skaik 2014

Electronic Devices and Circuit Theory, 10/e Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky 13 Upper Saddle River, New Jersey 07458 • All rights reserved.
 Example 2.7
Determine Vo and ID. The forward bias voltage for red LED is 1.8 V.
Solution

Dr. Talal Skaik 2014

Electronic Devices and Circuit Theory, 10/e Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky 14 Upper Saddle River, New Jersey 07458 • All rights reserved.
 Example 2.8
Determine ID ,VD2 and Vo.
Solution

Dr. Talal Skaik 2014

Electronic Devices and Circuit Theory, 10/e Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky 15 Upper Saddle River, New Jersey 07458 • All rights reserved.
 Example 2.9
Determine I , V1 ,V2 and Vo
Solution

Dr. Talal Skaik 2014

Electronic Devices and Circuit Theory, 10/e Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky 16 Upper Saddle River, New Jersey 07458 • All rights reserved.
Parallel and Series-Parallel Configurations
Example 2.10
Determine VO , I1, ID1, and ID2
Solution

Dr. Talal Skaik 2014

Electronic Devices and Circuit Theory, 10/e Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky 17 Upper Saddle River, New Jersey 07458 • All rights reserved.
Example 2.11 : Find the resistor R to ensure a current of 20 mA
through the “on” diode for the given circuit. Both diodes have
reverse breakdown voltage of 3V and average turn-on voltage of 2V.

Solution

Dr. Talal Skaik 2014

Electronic Devices and Circuit Theory, 10/e Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky 18 Upper Saddle River, New Jersey 07458 • All rights reserved.
Example 2.12 Determine the voltage Vo.

Solution

Dr. Talal Skaik 2014

Electronic Devices and Circuit Theory, 10/e Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky 19 Upper Saddle River, New Jersey 07458 • All rights reserved.
Example 2.13 Determine the currents I1, I2 and ID2

Solution

Dr. Talal Skaik 2014

Electronic Devices and Circuit Theory, 10/e Copyright ©2009 by Pearson Education, Inc.
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AND/OR Gates
Example 2.14 Determine Vo

Logic OR gate

Solution

Dr. Talal Skaik 2014

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AND/OR Gates: Example 2.15
Determine the output level for the logic
AND gate

Logic AND gate

Solution

Dr. Talal Skaik 2014

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 Chapter Three

Bipolar Junction Transistors

 3.1: Introduction
Transistors are manufactured by sandwiching one of
the semiconductor (p-type or N-type) materials
between two layers of the other semiconductor
materials. Transistors are basically grouped into two
broad classifications.
 Bipolar Junction Transistor (BJT) type: As the name implies
that the output current is the contribution of both minority
and majority charge carriers. BJT is a current controlled
device which means the output current is controlled by the
input current.
 Field Effect Transistor (FET) : is a unipolar three terminal
device, in such type of transistor , the output current is as a
result of either holes or electrons flow i.e majority charge
carriers only . The Output current is controlled by the input
voltage, hence FET is called voltage controlled device
Introduction (cont)…
 BJT Construction
• The Bipolar junction transistor is a three-layer semiconductor
device consisting of;
two n-type and one p-type layers of material(npn
transistor) or
two p-type and one n-type layers of material(pnp
transistor)
 Emitter: It is more heavily doped than any of the other
regions because its main function is to supply majority charge
carries (either electrons or holes) to the base.
 Base: It forms the middle section of the transistor. It is very
thin (10–6m) as compared to either the emitter or collector
and is very lightly-doped.
 Collector: Its main function (as indicated by its name) is to
collect majority charge carriers coming from the emitter and
passing through the base
 Contd…

a) NPN Bipolar Junction Transistor b) PNP Bipolar

Junction Transistor

Figure 3.1 Symbols and simplified models for (a) NPN and (b) PNP
bipolar junction transistors
Contd…

a) NPN transistor construction b) PNP transistor construction

Figure 3.2 Construction Feature of Bipolar Junction Transistor

 BJT Operating Regions
 A BJT has two junctions i.e. base-emitter and base-
collector junctions either of which could be forward-
biased or reverse-biased. With two junctions, there are
four possible combinations of bias condition.
 Both junctions reverse-biased
 Both junctions forward-biased
 BE junction forward-biased, BC junction reverse-biased.
 BE junction reverse-biased, BC junction forward-biased.
 Since the last condition is generally not used, the
remain is tabulated below.
 BJT Operating region cont…

Based on the biasing arrangement of the junctions, the

transistor operates in three regions , These are
 Active Region
 Saturation Region
 Cut-off regions
 BJT Operating region cont…
 Cut-off: This condition corresponds to reverse-bias for both base-
emitter and base-collector junctions. In fact, both diodes act like
open circuits under these conditions as shown in fig below which is
true for an ideal transistor. The reverse leakage current has been
neglected. As seen, the three transistor terminals are uncoupled
from each other. In cut-off, VCE = VCC.
 Saturation: This condition corresponds to forward-bias for both
base-emitter and base-collector junctions. The transistor becomes
saturated i.e. there is perfect short-circuit for both base-emitter
and base-collector diodes. The ideal case, where the three
transistor terminals have been connected together thereby
acquiring equal potentials. In this case, VCE = 0.
 Active Region: This condition corresponds to forward-bias for base-
emitter junction and reverse bias for base-collector junction. In this,
VCE > 0.
 BJT operation

• In normal operation, the base-emitter is forward-

biased and the base-collector is reverse-biased.
• For the npn type ;
– the collector is more positive than the base, which is
more positive than the emitter.

• For the pnp type, the voltages are reversed to

maintain the forward-reverse bias.
Contd…

Figure 3.3: Bias voltages and current flow for (a) NPN and (b)
PNP bipolar junction transistors
 BJT operation(npn type)

Electrons from the emitter flowing to the base

Contd…
• When the base to emitter junction is forward
biased;
– The free electrons start to cross from the emitter to base
region
• Since emitter is highly doped a large number of
electrons crosses the junction
• But the base is very thin and also lightly doped,
and all electrons do not recombine with the holes
in this region
• Only a 2 % to 5% of electrons recombine with holes
Contd…

• Only a few electrons recombines with the holes in base

Contd…
• This electron hole recombination contributes a
base current.
• the base current circulates through base, emitter
and the voltage source.
 Contd…
• The rest 95% to 98% of the free electrons cross the
base to collector junction;
– due to the kinetic energy gained from the
electrostatic force of base to emitter voltage.
Contd…
• The excess free electrons in the base region can
easily cross the reverse-biased base-collector
junction.
• Because this free electrons in the base region are
minority carriers and the reverse –biased base to
collector junction do not oppose the flow of
minority charge carriers
• If the base to emitter forward-biased voltage
increases;
– the number electrons crossing the junctions also
increases proportionally
 Contd

• The ratio of collector current to base current is

called current gain in common emitter mode.
Contd…
• The base region is very narrow so that carriers are
swept across it from emitter to collector and

• only a relatively small current flow in the base

• To put this into context, the current flowing in the

emitter circuit is typically 100 times greater than
that flowing in the base.
Contd…
• The equation that relates current flow in the
collector, base, and emitter currents is;
IE = IB + IC

• Where IE is the emitter current, IB is the base

current, and
• IC is the collector current (all expressed in the same
units).
Contd…
• The collector current, however, comprises two
components;
– the majority and the minority carriers
• The minority-current component is called the
leakage current and is given the symbol ICO (IC
current with emitter terminal Open).
• The collector current, therefore, is determined in
total by;
.

Biasing For Cutoff Biasing For Active

Biasing For saturation

 BJT Transistor Circuit Configurations
 Basically, there are three types of circuit connections
(called configurations) for operating a transistor.
1. Common-base (CB) 2. Common-emitter (CE)
3. Common-collector (CC).
 The term ‘common’ is used to denote the electrode
that is common to the input and output circuits.
Because the common electrode is generally grounded,
these modes of operation are frequently referred to as
grounded-base, grounded-emitter and grounded-
collector configuration.
 Since a transistor is a 3-terminal (and not a 4-terminal)
device, one of its terminals has to be common to the
input and output circuits.
 CB Configuration
In this configuration, emitter current IE is the
input current and collector current IC is the
output current. The input signal is applied
between the emitter and base whereas
output is taken out from the collector and
base as shown in Fig. 3.6. The collector
current is the summation of part of Emitter
current 𝛼 𝐼𝐸 collected by collector plus
current due to minority charge carriers 𝐼𝐶𝑂
 CB Configuration cont’

Fig 3.6

𝐼𝐶 = 𝛼𝐼𝐸 + 𝐼𝐶𝑂

The ratio of the collector current to the emitter current is called

alpha 𝛼 of a transistor is given by
𝛼 = 𝐼𝐶 − 𝐼𝐶𝑂 𝐼𝐸
Since 𝐼𝐸 = 𝐼𝐶 + 𝐼𝐵 , Neglecting 𝐼𝐶𝑂 ,

𝐼𝐸 = 𝛼𝐼𝐸 + 𝐼𝐵 i.e, 𝐼𝐵 = 1 − 𝛼 𝐼𝐸
 Common Base Static Characteristics
(a) Input Characteristic
It shows how IE varies with VBE when voltage VCB is held constant. The method of
determining this characteristic is as follows: First, voltage VCB is adjusted to a suitable
value with the help of adjustable resistance and next, voltage VBE is increased in a
number of discrete steps and corresponding values of IE are noted from the millimeter
connected for the purpose. When plotted, we get the input characteristic shown in
Fig.3.7

Fig 3.7 input characteristics

CB configuration

Input characteristics
VCB=constant
A small change VBE there will be a large change in IE
𝛥𝑉𝐵𝐸
Input resistance Rin is given by, 𝑅𝑖𝑛 = , VCB=constant, Rin is very small
𝛥𝐼𝐸
IE is almost independent of VCB
 Output Characteristic (CB)
 It shows the way IC varies with VCB when IE is held constant.
The method of obtaining this characteristic is as follows:
 First, the adjustable resistance is changed to get a suitable
value of VBE and hence that of IE. While keeping IE constant
at this value, VCB is increased from zero in a number of
steps and the corresponding collector current IC that flows
is noted. Next, VCB is reduced back to zero, IE is increased to
a value a little higher than before and the whole procedure
is repeated. In this way, whole family of curves is obtained,
a typical family being shown in Fig. 3.8

• Fig 3.8
 Output Characteristic (CB)
Output characteristics
1. The reciprocal of the near horizontal part of the characteristic gives the
output resistance Rout of the transistor which it would offer to an input signal.
Since the characteristic is linear over most of its length (meaning that IC is
virtually independent of VCB). Rout is very high, a typical value being 500k
𝟏
𝑹𝒐𝒖𝒕 =
𝛥𝐼C
𝛥𝑉BC
2. Another important feature of the characteristic is that a small amount of
collector current flows even when emitter current IE = 0, this due to collector
leakage current ICBO.
3. This characteristic may be used to find (α) the transistor as shown in
Fig.3.8
𝛥𝐼C
𝛼=
𝛥𝐼 E
4. Another point worth noting is that although IC is practically independent of
VC B over the working range of the transistor, yet if VCB is permitted to
increase beyond a certain value, IC eventually increases rapidly due to
avalanche breakdown as shown in Fig 5.8
.

Common Emitter
 Here, input signal is applied between the base and emitter and
output signal is taken out from the collector and emitter circuit.
As seen from Fig. 3.9, IB is the input current and IC is the
output current. The ratio of the d.c. collector current to dc base
current is called beta (β). 𝐼𝐶 = 𝛽𝐼𝐵
Fig 3.9

Note when the input is AC , the current ratio is given by

Δ𝐼
βac = 𝐶 , The relationship between β and α, we have
Δ𝐼B
β
α=
β+1
 Common Emitter Static Characteristics
(a) Input Characteristic
It shows how IB varies with changes in VBE when VCE is held constant at a
particular value. To begin with, voltage VCE is maintained constant at a
convenient value and then VBE is increased in steps. Corresponding values of IB
are noted at each step. The procedure is then repeated for a different but
constant value of VCE. A typical input characteristic is shown in Fig.3.9 like CB
connection, the overall shape resembles the forward characteristic of a P-N
diode.
Fig 3.9

𝟏 𝛥VBE
𝑹in = 𝛥IB = 𝛥IB
𝛥VBE

The reciprocal of the slope gives the input resistance Rin of the transistor.
Due to initial non-linearity of the curve, Rin varies considerably from a value of 4 k
Ω near the origin to a value of 600 Ω over the more linear part of the curve.
 Output or Collector Characteristic
It indicates the way in which IC varies with changes in VCE when IB
is held constant. For obtaining this characteristic, first IB is set to
a convenient value and maintained constant and then VCE is
increased from zero in steps, IC being noted at each step. Next,
VCE is reduced to zero and IB increased to another convenient
value and the whole procedure repeated. In this way, a family of
curves (Fig.3.10) is obtained.
• Fig 3.10
 Output Characteristic (cont)..
 It is seen that as VCE increases from zero, IC rapidly increases
to a near saturation level for a fixed value of IB. As shown, a
small amount of collector current flows even when IB= 0. It is
called ICEO . Since, main collector current is zero, the transistor
is said to be cut-off. It may be noted that if VCE is allowed to
increase too far, .C/B junction completely breaks down and
due to this avalanche breakdown, IC increases rapidly and may
cause damage to the transistor. When VCE has very low value
(ideally zero), the transistor is said to be saturated and it
operates in the saturation region of the characteristic. Here,
change in IB does not produce a corresponding change in IC.
keeping IB constant
𝛥VCE
𝑹out =
𝛥IC
.

CC Configuration
 In this case, input signal is applied between base and collector
and output signal is taken out from emitter-collector circuit
[Fig. 3.11 (a)]. Conventionally speaking, here IB is the input
current and IE is the output current as shown in Fig. 3.11(b).

IE
ɣ= = (1 + β)
IB

As shown in Fig. 3.11, in this case, collector terminal is common carrier to both the
input (CB) and output (CE) carriers circuits. The output characteristic is IE versus VCE
for several fixed values of IB. Since IC ≅ IE, this characteristic is practically identical to
that of the CE circuit and is shown in Fig.3.12
 Common Collector Static
Characteristics

Common collector is characterized by high current gain,

nearly unit voltage gain, high input resistance, and low
output resistance. Hence, it is used for impedance matching
circuit.
BJT Modes of Operation

Mode EBJ CBJ

Cutoff Reverse Reverse

Active Forward Reverse

(forward)
Reverse Reverse Forward
Active
Saturation Forward Forward

35
 Operating Limits for Each
Configuration
• VCE is at maximum and IC is at minimum
(ICmax= ICEO) in the cutoff region.

• IC is at maximum and VCE is at minimum

(VCE min = VCEsat = VCEO) in the saturation
region.

• The transistor operates in the active region

between saturation and cutoff.
 Operating Limits for Each
Configuration
• For each transistor there is a region of operation on
the characteristics that will ensure that;
– the maximum ratings are not being exceeded
– and the output signal exhibits minimum
distortion.

• Some of the limits of operation are;

– maximum collector current;
– maximum collector-to-emitter voltage (often
abbreviated as BV CEO or V(BR)CEO)
 Power Dissipation

Common-base:
PCmax  VCB I C

Common-emitter:
PCmax  VCE I C

Common-collector:

PCmax  VCE I E
 3.4. Biasing methods
The term biasing is the application of dc voltages to
establish a fixed level of current and voltage in a
transistor .
For transistor amplifiers the resulting dc current and
voltage establish an operating point on the
characteristics
Because the operating point is a fixed point on the
characteristics, it is also called the quiescent point
(abbreviated Q -point).
By definition, quiescent means quiet, still.

• The analysis of a transistor amplifier requires a

knowledge of both the dc and the ac response of the
system.
 Biasing methods (cont)…
Need for DC biasing
To determine the operating point of the
transistor so that transistor used as an amplifier
The input voltage should exceed cut-in
voltage for the transistor to be ON.
The BJT should be in the active region, to be
operated as an amplifier.
 Biasing methods (cont)…
Factors affecting the operating point
The main factor that affect the operating point is the
temperature. The operating point shifts due to change
in temperature.
As temperature increases, the values of ICE, β, VBE gets
affected.
ICBO gets doubled (for every 10o rise)
VBE decreases by 2.5mv (for every 1o rise)
Operating point should be made independent of
the temperature so as to achieve stability. To
achieve this, biasing circuits are introduced.
 Biasing methods (cont)…
 Need for Stabilization
 Stabilization of the operating point has to be achieved due
to the following reasons.
 Temperature dependence of IC
 Individual variations: As the value of β and the value of VBE are
not same for every transistor, whenever a transistor is replaced,
the operating point tends to change. Hence it is necessary to
stabilize the operating point.
 Thermal runaway : As the expression for collector current IC is
IC=βIB+ICEO =βIB+(β+1)ICBO
The flow of collector current and also the collector leakage
current causes heat dissipation. If the operating point is not
stabilized, there occurs a cumulative effect which increases
this heat dissipation.
 Biasing methods (cont)…
Stability Factor (S)
It is understood that IC should be kept constant in spite of
variations of ICBO or ICO.
Stability factor , biasing circuit should maintain constant IC
regardless of variation of ICBO or ICO

The stability factor should be as low as possible so that the

collector current doesn’t get affected, S=1 is the ideal value.

Hence the stability factor S depends on β, IB and IC.

 1, FIXED-BIAS CONFIGURATION
The fixed-bias circuit shown below provides a
relatively straightforward and simple introduction
to transistor dc bias analysis.

(a) (b)
Figure 3.21: (a) Fixed-bias circuit, (b):DC equivalent circuit
 Input characteristics
 Writing Kirchhoff’s voltage equation in the
clockwise direction for the loop, we obtain
+VCC - IBRB – VBE = 0

Substituting this expression in

stability equation we have

Base–emitter loop
Output characteristics
VCE + ICRC - VCC = 0
VCE = VCC – ICRC
VCE = VC - VE
VCE = VC, for VE = 0
VBE = VB – VE
VBE = VB, for VE = 0
 1. FIXED-BIAS CONFIGURATION
Advantages
The circuit is simple.
Only one resistor RE is required.
Biasing conditions are set easily.
No loading effect as no resistor is present at base-emitter
junction.
 Disadvantages
 The stabilization is poor as heat development can’t be
stopped.
 The stability factor is very high. So, there are strong
chances of thermal run away.
 Hence, this method is rarely employed.
1.FIXED-BIAS CONFIGURATION (cont)…
Example 1:
• Determine the following for the fixed-bias
configuration of Figure shown below.
• (a) IBQ and ICQ
• (b) VCEQ
• (c) VB and VC
• (d)VBC
1.FIXED-BIAS CONFIGURATION (cont)…

Figure 3.22: DC fixed-bias circuit for Example 1

1.FIXED-BIAS CONFIGURATION (cont)…
Solution
• a,

• b,

• c,

• d,
 Load-Line Analysis
• In the previous analysis the value of β is used to find
the operating point(Q-point) of the fixed-bias
configuration.
• We will now investigate how the network
parameters define the possible range of Q-points.
and how the actual Q-point is determined.
• The network of the Figure shown below establishes
an output equation that relates the variables IC and
VCE in the following manner:
VCE = VCC - ICRC
• The output characteristics of the transistor also
relate the two variables IC and VCE
1.FIXED-BIAS CONFIGURATION (cont)…
• Now let us draw the straight line defined by the
above equation on the characteristics.
• The most direct method of plotting the above
equation on the output characteristics is to use the
fact that a straight line is defined by two points.
VCE = VCC
FIXED-BIAS CONFIGURATION (cont)…

Figure 3.26: Fixed-bias load line

1.FIXED-BIAS CONFIGURATION (cont)…
Example 2
• Given the load line of the Figure shown below and
the defined Q-point, determine the required values
of VCC, RC, and RB for a fixed-bias configuration.
1.FIXED-BIAS CONFIGURATION (cont)…
Solution
2. Collector-feedback bias.
+VCC VCC   I C  I B  RC  I B RB  VBE
VCC  VBE
IB 
(hFE  1) RC  RB
RC
RB
ICQ  hFE I B

VCEQ  VCC   hFE  1 I B RC

IC
IB
 VCC  I CQ RC

IE

56
 2. Collector-feedback bias (contd)…
Example Determine the values of ICQ and VCEQ for the
amplifier .
+10 V
VCC  VBE
IB 
RB   hFE  1 RC
RC
10V  0.7V
1.5 k   28.05μA
RB 180kΩ  1011.5kΩ
ICQ  hFE I B  100  28.05μA
180 k
 2.805mA
hFE = 100
VCEQ  VCC  (hFE  1) I B RC
 10V  101 28.05μA 1.5kΩ
 5.75V 57
 2. Circuit Stability of
Collector-Feedback Bias (contd)…
+VCC hFE increases
(𝛽+1)(𝑅𝐵 +𝑅𝐶 )
S=
𝑅𝐵 +(𝛽+1)𝑅𝐶
IC increases (if IB is the same)
RC
RB VCE decreases

IC
IB
IB decreases

IE
IC does not increase that much.
Good Stability. Less dependent
on hFE and temperature.
58
 Collector-Feedback
Characteristics (contd)…
+VCC
Circuit recognition: The base
resistor is connected between
the base and the collector
RC terminals of the transistor.
RB Advantage: A simple circuit
with relatively stable Q-point.
IC Disadvantage: Relatively poor
IB
ac characteristics.
Applications: Used primarily to
IE
bias linear amplifiers.

59
3.Emitter-Stabilized Bias Configuration
This dc bias network contains an emitter resistor to
improve the stability level over that of the fixed-bias
configuration. The analysis will be performed by first
examining the base–emitter loop and then using the
results to investigate the collector–emitter loop.
 Input characteristics
Base–Emitter Loop
Writing Kirchhoff’s voltage law around the
indicated loop in the clockwise direction will
result in the following equation:

Base–emitter
loop
Input characteristics (Contd)…
+VCC – IBRB – VBE – IERE= 0
IE = (β + 1) IB
Substitute for IE in the above equation will result
+VCC – IBRB – VBE – (β + 1) IB RE= 0
Grouping terms will then provide the following:
- IB (RB + (β + 1) RE) + VCC - VBE = 0
Multiplying through by (-1) we have
IB (RB + (β + 1) RE) - VCC + VBE = 0
IB (RB + (β + 1) RE) = VCC - VBE
Solve for IB
 Input characteristics (Contd)…
𝑑𝐼𝐵 𝑅𝐸
=− →
𝑑𝐼𝐶 𝑅𝐸 +𝑅𝐵

Substituting the derivative expression in stability

factor expression we have ,
1+β
S= 𝑅𝐸
1+β 𝑅 +𝑅
𝐸 𝐵

This expression shows improvement in the stability with

cost of reducing gain as compared with fixed biasing
Output characteristics (Contd)…
Collector–Emitter Loop
• Writing Kirchhoff’s voltage law for the indicated
loop in the clockwise direction will result in
+ IERE + VCE + ICRC - VCC = 0
• Substituting IE ≈ IC and grouping terms gives

• While the voltage from collector to ground can be

determined from;
Output characteristics (Contd)…

• The voltage at the base with

respect to ground can be
determined from

Collector–emitter loop.
 3. Emitter-Stabilized Bias
Configuration
Advantages
 The circuit is simple as it needs only one resistor.
 This circuit provides some stabilization, for lesser changes.
Disadvantages
 The circuit doesn’t provide good stabilization.
 The circuit provides negative feedback.
Emitter-Stabilized configuration(Contd)…
Example 3
• For the emitter bias network of shown below
determine:
(a) IB, (b) IC, (c) VCE
(d) VC (e) VE (f) VB (g) VBC

Figure 3.29: Emitter-stabilized

bias circuit for Example 3
Emitter-Stabilized configuration(Contd)…
Solution
Emitter-Stabilized configuration(Contd)…

Saturation Level
The collector saturation level or maximum collector current for an
emitter-bias design can be determined using the same approach
applied to the fixed-bias configuration:
Apply a short circuit between the collector–emitter terminals and
calculate the resulting collector current
Emitter-Stabilized configuration(Contd)…

EXAMPLE 4
Determine the saturation current for
the network of the above Example.
Solution

This is about three times of the level

of ICQ for the above Example

Figure 3.30: Determining ICsat for the emitter stabilized

bias configuration.
 Load-Line Analysis
• The load-line analysis of the emitter-bias
network is only slightly different from that
encountered for the fixed-bias configuration.
• The collector–emitter loop equation that defines
the load line is given by;

Load line for the emitter-bias

configuration
 4. Voltage divider bias
The name voltage divider comes from the voltage divider formed by
R1 and R2. The voltage drop across R2 forward biases the base-emitter
junction. This causes the base current and hence collector current
flow in the zero signal conditions.
Assume that I2 > 10IB.
+VCC
R2
VB  VCC = 𝑉2
R1  R2

IC RC VE  VB  0.7V
I1 R1
VE
IE 
IB
Output
RE
Assume that ICQ  IE (or
Input
hFE >> 1). Then
I2 R2
IE RE
𝑉𝐵 − 𝑉𝐵𝐸
𝐼𝐶 =
𝑅𝐸 72
 4. Voltage divider bias (contd). ..
 From equation of IC above voltage divider circuit is almost
independent of transistor parameters and hence good
stabilization is achieved.
Base input resistance. (1)
VCC VCC

VE  I E RE  I B (hFE  1) RE
VE
I1 R1
IC RC
I1 R1
RIN (base)   (hFE  1) RE
IB
0.7 V
IB
 hFE RE

I2 R2 I2 R2 IB RIN(base)
RE
IE
RIN(base)
 4. Voltage divider bias (contd). ..
Base input resistance. (2)
R2 // RIN (base)
VCC VB  VCC
R1  R2 // RIN (base)
R2 //  hFE RE 
 VCC
R1  R2 //  hFE RE 
I1 R1
IB
VB
REQ
 VCC
R1  REQ REQ  R2 //  hFE RE 
I2 R2 IB RIN(base)

74
 4.Voltage divider bias (contd). ..

Collector-Emitter Voltage, VCE

𝑉𝐶𝐶 = 𝐼𝐶 𝑅𝐶 + 𝑉𝐶𝐸 + 𝐼𝐶 𝑅𝐸 𝐴𝑠𝑠𝑢𝑚𝑖𝑛𝑔 𝐼𝐶 ≅ 𝐼𝐸
𝑉𝐶𝐶 = 𝐼𝐶 𝑅𝐶 + 𝑅𝐸 + 𝑉𝐶𝐸
→ 𝑉𝐶𝐸 = 𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶 + 𝑅𝐸

RE provides excellent stabilization in this circuit.

Suppose there is a rise in temperature, then the collector
current IC decreases, which causes the voltage drop across
RE to increase. As the voltage drop across R2 is V2, which is
independent of IC, the value of VBE decreases. The reduced
value of IB tends to restore IC to the original value.
 4.Voltage divider bias (contd)…
Stability Factor
 The equation for Stability factor of this circuit is
obtained as

If the ratio R0/RE is very small, then R0/RE can be neglected

as compared to 1 and the stability factor becomes

This is the smallest possible value of S and leads to the

maximum possible thermal stability.
 4.Voltage divider bias (contd). ..
VCC
I C (sat) 
Circuit recognition: The
Load line RC  RE
equations:
voltage divider in the base VCE (off )  VCC
circuit.
Advantages: The circuit Q-point Q-point equations (assume
values are stable against changes that hFERE > 10R2):
in hFE.
R2
VB  VCC
Disadvantages: Requires more R1  R2
components than most other
VE  VB  0.7V
biasing circuits.
VE
Applications: Used primarily to I CQ  I E 
bias linear amplifier. RE
VCEQ  VCC  I CQ  RC  RE 
 Example1 (1)
Determine the values of ICQ and VCEQ for the circuit shown in Fig. 7.15.
+10 V R2
VB  VCC
R1  R2
4.7kΩ
 10V   2.07V
22.7kΩ
RC
R1
IC
3 k VE  VB  0.7V
I1
18 k  2.07V  0.7V  1.37V
IB Because ICQ  IE (or hFE >> 1),
hFE = 50 VE 1.37V
ICQ    1.25mA
RE 1.1kΩ
R2
I2
4.7 k
RE VCEQ  VCC  I CQ  RC  RE 
1.1 k
IE  10V  1.25mA  4.1kΩ   4.87V

78
 Example1 (2)
Verify that I2 > 10 IB.
+10 V
VB 2.07V
I2    440.4μA
R2 4.7kΩ
IE 1.25mA
RC IB  
R1
IC
3 k hFE  1 50+1
I1
18 k  24.51μA

IB  I 2  10 I B
hFE = 50

R2
I2 RE
4.7 k
1.1 k
IE

79
3.5: Small Signal BJT Amplifiers and Parametric
Representations
Introduction
• The transistor models is used to perform a small
signal ac analysis of a number of standard
transistor network configurations.

• The networks analyzed represent the majority of

those appearing in practice today.

• Modifications of the standard configurations will be

relatively easy to examine.
Contd…
BJT Transistor Modeling
• A model is an equivalent circuit that represents
the AC characteristics of the transistor.

• A model uses circuit elements that approximate

the behavior of the transistor.

• There are two models commonly used in small

signal AC analysis of a transistor:

re model
Hybrid equivalent model
 The re Transistor Model
•BJTs are basically current-controlled devices;

•Therefore the re model uses a diode and a current

source to duplicate the behavior of the transistor.

•Recall that a current-controlled current source is one

where the parameters of the current source are
controlled by a current elsewhere in the network.
•In fact, in general:

BJT transistor amplifiers are referred to as

current-controlled devices.
Common-Base Configuration
• Recall from Chapter 2 that the ac resistance of a
diode can be determined by the equation
rac =26 mV/ID,
• where ID is the dc current through the diode at
the Q (quiescent) point.
• The same equation can be used to find the ac
resistance of the diode in the re model;
– if we simply substitute the emitter current instead of
diode current
Contd…
26 mV
I c  I e re 
Ie

Input impedance:
Z i  re

Output impedance:
Z o  

Voltage gain:
R L R L
AV  
re re

Current gain:
A i    1

Figure 3.31 (a) Common-Base BJT transistor;

(b) approximate model for the configuration
Contd…
• Due to the isolation that exists between input
and output circuits,
• the input impedance Zi for the common-base
configuration of a transistor is simply re.
• That is,

• The output impedance is;

Contd…
• The output resistance of the common-base
configuration is determined by the slope of the
characteristic lines of the output characteristics.

• Assuming the lines to be perfectly horizontal (an

excellent approximation) would result an
infinite output impedance.

• If care were taken to measure Zo graphically or

experimentally, levels typically in the range 1- to
2-MΩ would be obtained.
Contd…
The voltage gain will now be as;
 Common-Emitter Configuration
• For the common-emitter configuration;

– the input terminals are the base and emitter

terminals,
– but the output set is now the collector and
emitter terminals.

• In addition, the emitter terminal is now common

between the input and output ports of the
amplifier.
Contd…
• Substituting the re model equivalent circuit for the
npn transistor;

– It result that the controlled-current source is still

connected between the collector and base
terminals
– and the diode between the base and emitter
terminals.
Contd…

Figure 3.32 (a) Common-emitter BJT transistor; (b)

approximate model for the configuration
Contd…
• In this configuration, the base current is the input
current , while the output current is still Ic.
• the base and collector currents are related by the
following equation:

• However, since the ac beta is typically much greater

than 1, we will use the following approximation for
the current analysis:
Contd…

• The voltage Vbe is across the diode resistance as

shown in Figure below.
• The level of re is still determined by the dc current
Ie.
• Using Ohm’s law gives
Contd…

Determining Zi using
the approximate model.
Contd…
• For the output impedance, the characteristics of
interest are the output set of characteristics.
• Note that the slope of the curves increases with
increase in collector current.
• The steeper the slope, the less the level of output
impedance (Zo).

• The output impedance is;

Contd…

Defining ro for the common-emitter configuration

Contd…
• The voltage gain for the common-emitter
configuration will now be determined for the
configuration of Figure shown below.
• using the assumption that Zo =∞Ω
• For the defined direction of Io and polarity of Vo

Vo=-IoRL

Figure 3.33: Determining the voltage and current gain for the
common-emitter transistor amplifier.
Contd…

• The resulting minus sign for the voltage gain reveals

that the output and input voltages are 180° out of
phase.
• The current gain is;
Contd…
• The common-emitter configuration has;
– a moderate level of input impedance,

– a high voltage and current gain,

– and an output impedance that may have to be

included in the network analysis.
 Contd…

Figure 3.34: re model for the common-emitter

transistor configuration.
 Common-Collector Configuration
• For the common-collector configuration,

– The model defined for the common-emitter

Configuration is normally applied;

– rather than defining a model for the common-

collector configuration.
 The Hybrid Equivalent Model
The following hybrid parameters are developed
and used for modeling the transistor.
These parameters can be found on the
specification sheet for a transistor.
• hi = input resistance
• hr = reverse transfer voltage
ratio (Vi/Vo)  0
• hf = forward transfer current
ratio (Io/Ii)
• ho = output conductance

Figure 3.35: Hybrid

Equivalent Model
Contd…

Simplified General h-Parameter Model

• hi = input resistance
• hf = forward transfer current ratio (Io/Ii)
 re vs. h-Parameter Model
Common-Emitter
h ie   re
h fe   ac

Common-Base

h ib  re
h fb     1
Contd…

The hybrid p model is most useful for

analysis of high-frequency transistor
applications.
At lower frequencies the hybrid p model
closely approximate the re parameters, and
can be replaced by them.
 Common-Emitter Fixed-Bias Configuration

• The input is applied to the

base
• The output is from the
collector
• High input impedance
• Low output impedance
• High voltage and current
gain
• Phase shift between input
and output is 180
Contd…
• In addition, recognize that the input current Ii is not
the base current but the source current;

• while the output current Io is the collector current.

•
• The small-signal ac analysis begins by removing the
dc effects of VCC ,

• and replacing the dc blocking capacitors C1 and C2

by short-circuit equivalents.
 Contd…

Figure 3.36: Common- Figure 3.37: Network following the removal

of the effects of VCC, C1, and C2
emitter fixed-bias
configuration
 Contd…
• Substituting the re model for the common-emitter
configuration will result in the network of Figure
below.

Figure 3.38: substituting the re model into the

network
Contd…
• Assuming that β, re, and ro have been determined
will result in the following equations for the
important two-port characteristics of the system.
• Zi(input impedance):

• Zo: the output impedance of any system is defined

as the impedance Zo determined;
– when Vi = 0, Ii = Ib = 0, resulting in an open-
circuit equivalence for the current source.
• The result configuration is;
Contd…

Determining Zo

Av: The resistors ro and RC are in parallel;

If ro ≥ 10RC,
Contd…
Ai: The current gain
Current gain is determined in the following manner:
Applying the current-divider rule to the input and
output circuits,
Contd…
• However, if ro ≥ 10RC and RB ≥ 10βre, which is often
the case,

Phase Relationship:
• The negative sign in the resulting equation for Av
reveals that a 180° phase shift occurs between the
input and output signals.
Contd…

Figure 3.39: Demonstrating the 180° phase shift

between input and output waveforms
Contd…
EXAMPLE 1
For the network of Fig. 3.40:
(a) Determine re.
(b) Find Zi (with ro = ∞ Ω).
(c) Calculate Zo (with ro = ∞ Ω).
(d) Determine Av (with ro = ∞ Ω).
(e) Find Ai (with ro = ∞ Ω).
(f) Repeat parts (c) through (e) including ro = 50 kΩ in
all calculations and compare results.
Contd…
Solution
Contd…
 Voltage-Divider Bias Configuration
• The next configuration to be analyzed is the
voltage-divider bias network.
• Recall that the name of the configuration is a result
of the voltage-divider bias at the input side to
determine the dc level of VB.

Figure 3.40; Voltage-divider

bias configuration
Contd…
• Substituting the re model equivalent circuit results
the network shown in Figure below.
• The absence of RE is due to the low-impedance
shorting effect of the bypass capacitor, CE.
• That is, at the frequency (or frequencies) of
operation,
– The reactance of the capacitor is so small compared to
RE that it is treated as a short circuit across RE.
 Contd…

Figure 3.41: Substituting the re equivalent circuit into the ac

equivalent network of the voltage divider bias Configuration
Contd…
• When VCC is set to zero, it places one end of R1 and
RC at ground potential.
• In addition, note that R1 and R2 remain part of the
input circuit
• while RC is part of the output circuit.
• The parallel combination of R1 and R2 is defined by;
Contd…
Zo: with Vi set to 0 V resulting in Ib = 0 µA and βIb = 0
mA,

• If ro ≥ 10RC,
Av: Since RC and ro are in parallel,
Contd…
Ai:

and if R’ ≥ 10βre,
Contd…
EXAMPLE 2
For the network shown in Figure below. Determine;
(a) re.
(b) Zi.
(c) Zo (ro = ∞Ω).
(d) Av (ro = ∞Ω).
(e) Ai (ro = ∞Ω).
(f) The parameters of parts (b) through (e) if ro =
1/hoe = 50 kΩ and compare results.
Contd…
Contd…
Solution
Contd…
Contd…
 Islamic University of Gaza
Chapter 3:
Bipolar Junction Transistors Dr. Talal Skaik
 Transistor Construction
There are two types of transistors:
• pnp
• npn
The terminals are labeled:
• E - Emitter
• B - Base
• C - Collector

•The npn BJT consists of three semiconductor regions: the

emitter region (n type), the base region (p type), and the collector
region (n type).
•The pnp BJT consists of three semiconductor regions: the
emitter region (p type), the base region (n type), and the collector
region (p type).
Electronic Devices and Circuit Theory, 10/e 2 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
 Transistor Construction

The transistor consists of two pn junctions, the emitter–base

junction (EBJ) and the collector–base junction (CBJ).
Electronic Devices and Circuit Theory, 10/e 3 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
 Transistor Construction
Emitter: The portion on one side of transistor that supplies charge
carriers (i.e. electrons or holes) to the other two portions.
The emitter is a heavily doped region.
Emitter of PNP transistor supplies hole charges to its junction with
the base. Similarly, the emitter of NPN transistor supplies free
electrons to its junction with the base.

Electronic Devices and Circuit Theory, 10/e 4 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
 Transistor Construction
Collector is the portion on the other side of the transistor (i.e. the
side opposite to the emitter) that collects the charge carriers (i.e.
electrons or holes).
The doping level of the collector is in between the heavily doping
of emitter and the light doping of the base.

Base: The middle portion which forms two PN junctions between

the emitter and the collector is called the base.
The base of transistor is thin, as compared to the emitter and is a
lightly doped portion.
The function of base is to control the flow of charge carrier.

Electronic Devices and Circuit Theory, 10/e 5 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
 BJT Modes Of Operation
There are two junctions in bipolar junction transistor.
Each junction can be forward or reverse biased independently.
Thus there are different modes of operations:
Forward Active.
Cut off.
Saturation.

Electronic Devices and Circuit Theory, 10/e 6 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
 BJT Modes Of Operation
FORWARD ACTIVE
Emitter-base junction is forward biased and collector-base
junction is reverse biased.
The BJT can be used as an amplifier and in analog circuits.

CUTT OFF
When both junctions are reverse biased it is called cut off mode.
In this situation there is nearly zero current and transistor behaves
as an open switch.
SATURATION
In saturation mode both junctions are forward biased.
Large collector current flows with a small voltage across collector
base junction.
Transistor behaves as an closed switch.

Electronic Devices and Circuit Theory, 10/e 7 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
Operation of pnp transistor in active mode

Forward-biased junction of Reverse-biased junction of

a pnp transistor. a pnp transistor

Electronic Devices and Circuit Theory, 10/e 8 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
Operation of pnp transistor in active mode
With the external sources, VEE and VCC, connected as shown:
• The emitter-base junction is forward biased
• The base-collector junction is reverse biased

Electronic Devices and Circuit Theory, 10/e 9 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
Currents in a Transistor
Emitter current is the sum of the
collector and base currents:

IE  IC  IB

The collector current is comprised of two currents:

IC  IC  I CO
majority minority

The minority current is called the leakage current and is given by

the symbol ICO (IC current with emitter terminal Open).

Electronic Devices and Circuit Theory, 10/e 10 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
 Common Base Configuration

The base is common to both

input (emitter–base) and
output (collector–base) of
the transistor.

Electronic Devices and Circuit Theory, 10/e 11 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
 Common-Base Configuration
Input Characteristics
This curve shows the relationship
between of input current (IE) to
input voltage (VBE) for three output
voltage (VCB) levels.

VBE=0.7 V

Electronic Devices and Circuit Theory, 10/e 12 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
 Common-Base Configuration

Output Characteristics
This graph demonstrates the output current (IC) to an output voltage
(VCB) for various levels of input current (IE).
Electronic Devices and Circuit Theory, 10/e 13 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
 Operating Regions
• Active – Operating range of the amplifier. It is noticed that IE
is approximately equal to IC (IC≈ IE ).
• Cutoff – the region where the collector current is
approximately 0A (IC=ICBO). The amplifier is basically off.
There is voltage, but little current.

• Saturation – Region to the left of VCB=0. Note the

exponential increase in collector current as the voltage VCB
increases toward 0 V. There is current but little voltage.

Electronic Devices and Circuit Theory, 10/e 14 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
 Approximations

Emitter and collector currents:

I I
C E

Base-emitter voltage:

VBE  0.7 V (for Silicon)

Electronic Devices and Circuit Theory, 10/e 15 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
 Alpha (a)
Alpha (a) is the ratio of IC to IE :

IC
αdc 
IE

IC  αI E  I CBO

Ideally: a = 1
In reality: a is between 0.9 and 0.998

Alpha (a) in the AC mode:

ΔIC
α ac 
ΔI E V
CB constant

Electronic Devices and Circuit Theory, 10/e 16 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
 Chapter Four

Multistage Amplifier
 Multi-Stage Transistor Amplifier(1)
 In practical applications, the output of a single state
amplifier is usually insufficient, though it is a voltage or
power amplifier. Hence. they are replaced by Multi-stage
transistor amplifiers.
 In Multi-stage amplifiers, the output of first stage is
coupled to the input of next stage using a coupling
device. These coupling devices can usually be a capacitor
or a transformer. This process of joining two amplifier
stages using a coupling device can be called as Cascading.
 The following figure shows a two-stage amplifier
connected in cascade.
Multi-Stage Transistor Amplifier(2)
• The overall gain is the product of voltage gain of individual
stages.

Where AV = Overall gain, AV1 = Voltage gain of 1st stage, and

AV2 = Voltage gain of 2nd stage.
If there are n number of stages, the product of voltage gains of
those n stages will be the overall gain of that multistage
amplifier circuit.
Purpose of coupling device is to transfer the AC from the output
of one stage to the input of next stage and to block the DC to
pass from the output of one stage to the input of next stage,
which means to isolate the DC conditions.
 Types of Coupling
There are four basic methods of coupling,
using these coupling devices such as resistors,
capacitors, transformers etc.
Resistance-Capacitance(RC) Coupling
Impedance Coupling
Transformer Coupling
Direct Coupling
 Resistance-Capacitance(RC) Coupling
 This is the mostly used method of coupling, formed using
simple resistor-capacitor combination.
 The capacitor which allows AC and blocks DC is the main
coupling element used here.
 The coupling capacitor passes the AC from the output of
one stage to the input of its next stage. While blocking the
DC components from DC bias voltages to effect the next
stage.
 The capacitor CC is the coupling capacitor that connects two
stages and prevents DC interference between the stages
and controls the operating point from shifting. This is also
called as blocking capacitor because it does not allow the
DC voltage to pass through it.
 Construction of a Two-stage RC Coupled
Amplifier
 The two stage amplifier circuit has two transistors,
connected in CE configuration and a common power
supply VCC is used. The potential divider network R1 and
R2 and the resistor Re form the biasing and stabilization
network. The emitter by-pass capacitor Ce offers a low
reactance path to the signal.
 The resistor RL is used as a load impedance. The input
capacitor Cin present at the initial stage of the amplifier
couples AC signal to the base of the transistor. The
capacitor CC is the coupling capacitor that connects two
stages and prevents DC interference between the stages
and controls the shift of operating point..
 Operation of RC Coupled Amplifier
 When an AC input signal is applied to the base of first
transistor, it gets amplified and appears at the collector load
RL which is then passed through the coupling capacitor CC to
the next stage. This becomes the input of the next stage,
whose amplified output again appears across its collector
load. Thus the signal is amplified in stage by stage action.
 AC Analysis Of RC-Coupled Amplifier (1)
Common-Emitter
h ie   re
h fe   ac

R  R // R
B 1 2
 AC Analysis Of RC-Coupled Amplifier (2)

AC analysis𝑉 = 𝛽𝐼𝐵 × 𝑅𝐶 //𝑟𝑜 //𝑅𝐵 //β𝑟𝑒 , 𝑉𝑖 = 𝐼𝐵 𝛽𝑟𝑒

𝑜1

𝑉𝑜1 𝛽𝐼𝐵 𝑅𝐶 //𝑟𝑜 //𝑅𝐵 //β𝑟𝑒

𝐴𝑣1 = =
𝑉𝑖 𝐼𝐵 𝛽𝑟𝑒
𝑅𝐶 //𝑟𝑜 //𝑅𝐵 //β𝑟𝑒
=
𝑟𝑒
𝑉𝑜 = 𝛽𝐼𝐵 𝑅𝐶 //𝑟𝑜 , 𝑉𝑖2 = 𝐼𝐵 𝛽𝑟𝑒
𝑉𝑜 𝛽𝐼𝐵 𝑅𝐶 //𝑟𝑜 𝑅𝐶 //𝑟𝑜
𝐴𝑣2 = = =
𝑉𝑖2 𝐼𝐵 β𝑟𝑒 𝑟𝑒

𝐴𝑣 =𝐴𝑣2 × 𝐴𝑣1
RC Coupled multistage amplifier
example
RC Coupled multistage amplifier example (2)
RC Coupled multistage amplifier
example (3)
 AC Analysis Of RC-Coupled Amplifier (7)
 Advantages of RC Coupled Amplifier
 The following are the advantages of RC coupled amplifier.
 The frequency response of RC amplifier provides constant gain over a wide frequency range,
hence most suitable for audio applications.
 The circuit is simple and has lower cost because it employs resistors and capacitors which are
cheap.
 It becomes more compact with the upgrading technology.
 Disadvantages of RC Coupled Amplifier
 The following are the disadvantages of RC coupled amplifier.
 The voltage and power gain are low because of the effective load resistance.
 They become noisy with age.
 Due to poor impedance matching, power transfer will be low.
 Applications of RC Coupled Amplifier
 The applications of a RC coupled amplifier include:
 RF Communications.
 Optical Communications
 Public address systems as pre-amplifiers.
 Radio or TV Receivers as small signal amplifiers
 Impedance Coupling
The coupling network that
uses inductance and capacitance as coupling
elements can be called as Impedance
coupling network.
In this impedance coupling method, the
impedance of coupling coil depends on its
inductance and signal frequency which is jwL.
This method is not so popular and is seldom
employed.
 Impedance Coupling(2)

Fig . Circuit diagram

of Impedance
Coupling amplifier

Fig . AC equivalent circuit diagram of

Impedance Coupling amplifier
Impedance Coupling(3)
 Impedance Coupling(4)

Advantages
• No DC drops across L
Disadvantages

 Large heavier and costlier than RC Coupling

 Since inductor depends on frequency the frequency characteristics of
this coupling are not as good .At low frequency gain increased due to
large capacitance and at large frequency gain drops because of
increasing capacitance .
 Transformer Coupling(1)
 We have observed that the main drawback of RC coupled amplifier
is that the effective load resistance gets reduced. the high output
impedance of one stage comes in parallel with the low input
impedance of next stage. Hence, effective load resistance is
decreased. This problem can be overcome by a transformer
coupled amplifier
 When they are coupled to make a multistage amplifier, The
coupling method that uses a transformer as the coupling device
can be called as Transformer coupling. There is no capacitor used in
this method of coupling because the transformer itself conveys the
AC component directly to the base of second stage.
 The secondary winding of the transformer provides a base return
path and hence there is no need of base resistance. This coupling is
popular for its efficiency and its impedance matching and hence it
is mostly used.
Construction of Transformer Coupled Amplifier(2)
 The coupling transformer T1 is used to feed the output of 1st stage to the
input of 2nd stage. The collector load is replaced by the primary winding of
the transformer. The secondary winding is connected between the
potential divider and the base of 2nd stage, which provides the input to the
2nd stage. Instead of coupling capacitor like in RC coupled amplifier, a
transformer is used for coupling any two stages, in the transformer
coupled amplifier circuit.
Construction of Transformer Coupled Amplifier(2)
 Instead of coupling capacitor like in RC coupled amplifier, a
transformer is used for coupling any two stages, in the
transformer coupled amplifier circuit.
 The transformer which is used as a coupling device in this
circuit has the property of impedance changing, which
means the low resistance of a stage (or load) can be
reflected as a high load resistance to the previous stage.
Hence the voltage at the primary is transferred according to
the turns ratio of the secondary winding of the
transformer.
 This transformer coupling provides good impedance
matching between the stages of amplifier. The transformer
coupled amplifier is generally used for power amplification
Frequency Response of Transformer Coupled
Amplifier
 The gain of the amplifier is constant only for a small range of
frequencies. The output voltage is equal to the collector
current multiplied by the reactance of primary.
At low frequencies, the reactance of
primary begins to fall, resulting in
decreased gain. At high frequencies, the
capacitance between turns of windings
acts as a bypass condenser to reduce
the output voltage and hence gain.

• So, the amplification of audio signals will not be

proportionate and some distortion will also get
introduced, which is called as Frequency
distortion.
Transformer coupled Multistage amplifier
 Advantages of Transformer Coupled Amplifier
 An excellent impedance matching is provided.
 Gain achieved is higher.
 There will be no power loss in collector and base resistors.
 Efficient in operation.
 Disadvantages of Transformer Coupled Amplifier
 Though the gain is high, it varies considerably with frequency. Hence a
poor frequency response.
 Frequency distortion is higher.
 Transformers tend to produce hum noise.
 Transformers are bulky and costly.
Applications
 Mostly used for impedance matching purposes.
 Used for Power amplification.
 Used in applications where maximum power transfer is needed.
AC Analysis for Transformer Coupled
Amplifier(1)
AC Analysis for Transformer Coupled
Amplifier(2)
 Direct Coupling(1)
 There are many applications in which extremely low frequency
(< 10 Hz) signals are to be amplified e.g. amplifying photo-electric
current, thermo-couple current etc. The coupling devices such as
capacitors and transformers cannot be used because the electrical
sizes of these components become very large at extremely low
frequencies. Under such situations, one stage is directly connected to
the next stage without any intervening coupling device. This type of
coupling is known as direct coupling.

 The direct coupling method is mostly used when the load is

connected in series, with the output terminal of the active circuit
element. For example, head-phones, loud speakers etc.
 Direct Coupling(2)

Any signal current at the base of Q1 is amplified 𝛽1 times and appears at the collector of
Q1 and becomes base signal for Q2. Hence ,it is further amplified 𝛽2 times . Obviously
signal current gain of the amplifier is 𝐴𝑖 = 𝛽1 × 𝛽2
Direct Coupling(3)

AC equivalent Circuit
 Direct Coupling(4)
 Advantages
 Simple circuit components
 It is inexpensive
 Very good for DC amplification and low frequency signal.
 IT doesn’t have coupling and bypass capacitors which causes gain
reduction. I,e flat gain frequency response at low frequencies .
 Disadvantage
 It can’t amplify high frequency
 It has poor temperature stability
 Application
 Regulator circuit in power supply
 Differential amplifier
 Electronic instrumentation
 Pulse amplifier
Direct Coupling(5)
 Islamic University of Gaza
Chapter 4
DC Biasing–BJTs Dr. Talal Skaik
 Biasing
Biasing: The DC voltages applied to a transistor in
order to turn it on so that it can amplify the AC signal.

Recall the following basic relationships for a transistor:

V BE  0.7 V
I E  (   1)I 
IC   I 

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 Operating Point

The DC input
establishes an
operating or
quiescent point
called the Q-point.

Various operating points within the

limits of operation of a transistor.
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 The Three States of Operation

• Active or Linear Region Operation

Base–Emitter junction is forward biased
Base–Collector junction is reverse biased

• Cutoff Region Operation

Base–Emitter junction is reverse biased

• Saturation Region Operation

Base–Emitter junction is forward biased
Base–Collector junction is forward biased

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 DC Biasing Circuits

• Fixed-bias circuit
• Emitter-stabilized bias circuit
• Collector-emitter loop
• Voltage divider bias circuit
• DC bias with voltage feedback

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 Fixed Bias configuration

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 Fixed Bias configuration

Fixed bias circuit DC equivalent

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 The Base-Emitter Loop

From Kirchhoff’s voltage

law:

+VCC – IBRB – VBE = 0

Solving for base current:

VCC  VBE
IB 
RB

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 Collector-Emitter Loop

Collector current:
I C  I B

From Kirchhoff’s voltage law:

VCE  VCC  I C R C

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Example 4.1
Find IBQ , ICQ , VCEQ , VB
, VC , VBC.

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 Load Line Analysis

V CE V CC  I C RC

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 Load Line Analysis

V CE V CC  I C RC

V CE V CC I C  0 mA

V CC
IC 
RC V CE  0V

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 Load Line Analysis

Movement of the Q-point with increasing level of IB.

(The level of IB is changed by varying the value of RB)

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 Load Line Analysis

Effect of an increasing level of RC on the load line and the Q-point.

(VCC fixed)
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 Load Line Analysis

Effect of lower values of VCC on the load line and the Q-point.

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Example 4.3
Find VCC , RC , RB for
the fixed biasing
configuration

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 Emitter-Stabilized Bias Circuit

Adding a resistor
(RE) to the emitter
circuit stabilizes the
bias circuit.

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 Base-Emitter Loop
From Kirchhoff’s voltage law:
 VCC - I E R E - VBE - I E R E  0

Since IE = ( + 1)IB:

VCC - I B R B - (  1)I B R E  0

Solving for IB:

VCC - VBE
IB 
R B  (  1)R E

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Collector-Emitter Loop
From Kirchhoff’s voltage law:
I R V I R V 0
E E CE C C CC
Since IE  IC:
VCE  VCC – I C (R C  R E )

Also:
VE  I E R E
VC  VCE  VE  VCC - I C R C
VB  VCC – I R R B  VBE  VE

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Example 4.4
Find IB , IC , VCE , VC , VE , VB , VBC .

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 Improved Biased Stability

Stability refers to a circuit condition in which the

currents and voltages will remain fairly constant over
a wide range of temperatures and transistor Beta ()
values.

Adding RE to the emitter improves the stability of a transistor.

Electronic Devices and Circuit Theory, 10/e Copyright ©2009 by Pearson Education, Inc.
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 Improved Biased Stability

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 Load Line Analysis
V CE V CC  I C (RC  R E )

V CE V CC I C  0 mA

V CC
IC 
RC  R E V CE  0V

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 CHAPTER 5
POWER and TUNED
AMPLIFIERS
 POWER AMPLIFIERS
INTRODUCTION
• An amplifier receives a signal from an input source and provides a larger
version of the signal to some output device or to another amplifier stage.
• In small signal amplifiers, the main factors are usually amplification,
linearity, and magnitude of gain.
• Since signal voltage and current are small in a small-signal amplifier;
 The amount of power-handling capacity and power efficiency are of
little concern, however this is a concern in Power amplifier
 A power amplifier is one that is designed to deliver a large amount of
power to a load. To perform this function ,a power amplifier must
itself be capable dissipating large amounts of power.
The characteristics of a power amplifier
 The base of transistor is made thicken to handle large currents. The value
of β being (β > 100) high.
 The size of the transistor is made larger, in order to dissipate more heat,
which is produced during transistor operation.
 Transformer coupling is used for impedance matching.
 Collector resistance is made low.
 High efficiency
HEATmeans less
= PIN - Pheat.
OUT

Input signal Output signal

Power
POUT
Amplifier

POUT
Efficiency =
PIN PIN
 Classification and analysis of Power
amplifier
• One method used to categorize amplifiers is by class.
• Basically, amplifier classes represent the amount the output signal
varies over one cycle of operation for a full cycle of input signal.
 Class A Amplifier
• The output of a class A amplifier conducts for the full 360 of the
input cycle.
• The Q-point is set at the middle of the load line so that the AC signal
can swing a full cycle.

• Remember that the DC load line indicates the maximum and minimum limits
set by the DC power supply.
 Class A Amplifier
• All the small-signal amplifiers have been designed so that
output voltage can vary in response to both positive and
negative input never saturates or cuts off. An amplifier that
has that property is called a Class-A amplifier . More precisely , an
amplifier is a class A if its output remains in the active region during
a complete cycle (one null period) of a sine-wave input signal.
• As shown fig if the transistor is based at VCE=VCC/2. which is
midway between saturation and cutoff, and which permits
maximum output voltage swing. The output can vary through
(approximately ) at full Vcc volts, peak-to-peak. The output is in the
transistor’s active region during a full cycle(3600) of the input sine
wave
 Class B Amplifier
• A class B amplifier output only conducts for 180 or one-half of
the AC input signal.
• The Q-point is at 0V on the load line, so that the AC signal can
only swing for one-half cycle.
 Class B Amplifier
Transistor operation is said to be class B when
output current varies during only one half-cycle
of a sine –wave input. In other words, the
transistor is in its active region ,responding to in
signal input. In practical amplifier, two transistor
operated Class B. One to amplifier positive signal
variations and the other to amplifier negative
signal variation. The amplifier output is the
composite waveform obtained by combining the
waveforms produced by each Class-B transistor.
 Push-Pull Amplifier
 A push-pull amplifier uses two devices to drive a load the name is derived
from the fact that one device is primarily (or entirely) responsive for
driving current through the load in one direction(pushing).While the other
device derives current through the load in the opposite direction (Pulling).
The output devices are typically two transistors, each operated Class B,
one of which conducts only when the input is positive, and the other of
which conducts only when the input is negative. This arrangement is
called a class-B push-pull amplifier and its principle is described below.
 Class AB Amplifier
• This amplifier is a compromise between the class A and class B
amplifier—the Q-point is above that of the Class B but below the
class A.
• For class AB operation, the output signal swing occurs between 180°
and 360° and is neither class A nor class B operation.
 Class AB Amplifier
Crossover distortion can be reduced or eliminated in a push-pull amplifier by biasing
each transistor slightly into conduction. When a small forward-biasing voltage is
applied across each base-emitter junction, and a small base current flows under no-
signal conditions. It is not necessary for the base drive signal to overcome the built-in
junction potential before active operation can occur.
When a transistor is biased slightly into conduction, output current will flow during
more than one-cycle of a sine-wave as shown in fig below. As can be seen in the
figure conduction occurs for more than one-half but les than a full cycle of the input.
This operation which is neither class A nor class B is called Class-AB operations

Class –AB operation

reduces crossover
distortion in a Push-
Pull amplifier, it has
the disadvantage of
reducing amplifier
efficiency
 Class C Amplifier
• The output of a class C amplifier is biased for operation at less than
180° of the cycle.
• The output of the class C conducts for less than 180 of the AC cycle.
• The Q-point is below cutoff.
 Class C
A class –C amplifier one whose output conducts load
current during less than one-half cycle of an input sine
wave. Its output is highly distorted version of its input. It
can’t be used in an application requiring high fidelity such as
an audio amplifier. It is used primly in high power , high
frequency applications such as radio-frequency transmitters.
The principle advantage is that it has very high efficiency.
 Class D Amplifier
• This operating class is a form of amplifier operation using pulse
(digital) signals,

 which are on for a short interval and off for a longer interval.

• The major advantage of class D operation is that;

 the amplifier is on (using power) only for short intervals and
 the overall efficiency can practically be very high.
 Amplifier Power Efficiency
• The power efficiency of an amplifier, defined as the ratio of power
output to power input,
• This table provides a relative comparison of the output cycle operation
and power efficiency for the various class types.
 Series-Fed Class A Amplifier
• The simple fixed-bias circuit connection shown below can be used to
discuss the main features of a class A series-fed amplifier.
• The only differences between this circuit and the small-signal version
considered previously is that the signals handled by the large-signal
circuit are in the range of volts and the transistor used is a power
transistor that is capable of operating in the range of a few to tens of
watts.
Contd…
DC Bias Operation
• The dc bias set by VCC and RB fixes the dc base-bias current at;

• The collector current,

• The collector–emitter voltage,
• This sets the operating point (Q-point) for the circuit.

AC Operation
• When an input ac signal
is applied to the
amplifier, the output
will vary from its dc
bias operating voltage
and current (Q-point).
 Power Efficiency
• The power into an amplifier is provided by the dc supply.
• With no ac input signal, the dc current drawn is the collector bias
current, ICQ.
• The power then drawn from the supply is:
• Even with an ac signal applied, the average current drawn from the
supply remains the same.
• So the above equation represents the input power supplied to the class
A series fed amplifier.

• The efficiency of an amplifier represents the amount of ac power

delivered (transferred) from the dc source.

• The efficiency of the amplifier is calculated using

Contd…

• Using the maximum voltage swing and maximum current swing;

the maximum output power is given by;
Contd…

NOTE: The maximum efficiency of a class A series-fed amplifier is thus seen to be 25%.
• The maximum efficiency will occur only for ideal conditions.
• But both voltage swing and current swing can not be maximum practically.
• So most series-fed circuits will provide efficiencies of much less than 25%.
Example 1
Calculate the input power, output power, and efficiency of the amplifier
circuit below for an input voltage that results in a base current of 10
mA peak.
Example 1
Solution
the Q-point can be determined to be;

Using the above Power equations;

 CLASS B AMPLIFIER OPERATION
• Class B operation is provided when the dc bias of the transistor
leaves biased just off and the transistor is turned on when the ac signal
is applied.
• This is essentially no bias, and the transistor conducts current for only
one-half of the signal cycle.

• To obtain output for the full cycle of the input signal;

– it is necessary to use two transistors and have each conduct on
opposite half-cycles,
– the combined operation providing a full cycle of output signal.
Contd…
• Since one part of the circuit pushes the signal high during one half-
cycle ;
• and the other part pulls the signal low during the other half-cycle -the
circuit is referred to as a push-pull circuit.
Contd…
Complementary-Symmetry Class B Amplifier Circuits

• Using complementary transistors (npn and pnp);

 it is possible to obtain a full cycle output across a load using half-
cycles of operation from each transistor,
• A single input signal is applied to the base of both transistors.
Contd…
Input (DC) Power
• The power supplied to the load by an amplifier is drawn from the dc
power supply.
• The amount of this input power can be calculated using:

Where, Idc is the average or dc current drawn from the power

supplies. IC

0A
Contd…
Input (DC) Power
• In class B operation, the current drawn from a single power supply
has the form of a full-wave rectified signal;
• While the current drawn from two power supplies has the form of a
half wave rectified signal from each supply.
• In either case, the value of the average current drawn from each
supplies is expressed as:

• where I(p) is the peak value of the output current waveform.

• Using the average current equation, the power input equation results
in:
Contd…
Output (AC) Power;
• The power delivered to the load (usually referred to as a resistance,
RL) can be calculated using any one of a number of equations.
• If one is using an rms meter to measure the voltage across the load,
the output power can be calculated as;

• If one is using an oscilloscope, the peak, or peak-to-peak, output

voltage measured can be used:

• The larger the rms or peak output voltage, the larger the power
delivered to the load.
Contd…
Efficiency
• The efficiency of the class B amplifier can be calculated using:

• Using the above power equations;

• Using I(p) = VL(p)/RL, the maximum output power is delivered to the

load when; VL(p) = VCC
• This maximum efficiency is then given by;

• When the input signal results in less than the maximum output signal
swing; the circuit efficiency is less than 78.5%.
 Power Dissipated by the Transistors
• The power dissipated (as heat) by the power transistors is; the
difference between the input power delivered by the supplies,and the
output power delivered to the load.
– where P2Q is the power dissipated by the two power transistors.

• The dissipated power handled by each transistor is then;

 CLASS C AMPLIFIERS
• A class C amplifier is biased to operate for less than 180° of the input
signal cycle.
• In order to produce a full sine wave output, the class C uses a tuned
circuit (LC tank) to provide the full AC sine wave.
• Class C amplifiers are used extensively in radio communications
circuits.
• Advantage - more efficient than either class A or push-pull class B &
class AB, which means that more output power can be obtained from
class C operation.
Contd…
• For class C operation, the transistor is biased below cutoff.
• So it only conducts when the input signal overcomes the bias supply
plus VBE.
• This means that the transistor conducts for only a short period of time
during each input cycle.
• The output voltage is a nonlinear function of the input voltage,
• So class C amplifiers are not used for linear amplification.
• They are generally used in radio frequency (RF) applications,
including circuits, such as
 oscillators,
 modulators,
Contd…

Figure: Class C amplifier circuit

Contd…
• A common-emitter class C amplifier with resistive load is shown in
the above Figure.
• It is biased below cutoff with the negative VBB supply.

• The AC source voltage has a peak value that is slightly greater than
VBB + VBE
• So that the base voltage exceeds the barrier potential of the base-
emitter junction, for a short time near the positive peak of each cycle
• During this short interval, the transistor is turned on.
Contd…

 The power dissipation averaged over the entire cycle is;

Contd…

Figure: Class C waveforms.

 Tuned Amplifiers
• Class C amplifiers are also called Tuned Amplifiers.
• An amplifier which amplifies a specific frequency (
or a narrow band of frequencies) is called a tuned
voltage amplifier.
• It has two purposes:
Selection of a desired radio frequency signal.
Amplification of the selected signal to a suitable
voltage level.
Contd…
Usage of Parallel Resonance Circuit as Load
• Because the collector voltage (output) is not a
replica of the input,
• The resistively loaded class C amplifier alone is of
no value in linear applications.
• It is therefore necessary to use a class C amplifier
with a parallel resonant circuit.
Contd….

Figure 7.11: Tuned Class C amplifiers

Contd…
• The short pulse of collector current on each cycle
of the input initiates the resonant circuit;
– and sustains the oscillation of the resonant
circuit,
– so that an output sinusoidal voltage is
produced.
• The resonant circuit has high impedance only
near the resonant frequency,
• so the gain is large only at this frequency.
 Resonant Circuit Action

Figure 7.12: Resonant circuit actions

Contd…

Figure 7.12: Resonant circuit actions

Contd…

Figure 7.12: Resonant circuit actions

Contd…

Figure 7.13 : Resonant circuit oscillations, Vr is the

voltage across the resonant circuit
Contd…
Contd…
 Islamic University of Gaza
Chapter 5:
BJT AC Analysis Dr. Talal Skaik
BJT Transistor Modeling
• A model is an equivalent circuit that represents the AC
characteristics of the transistor.

• A model uses circuit elements that approximate the

behavior of the transistor.

• There are two models commonly used in small signal

AC analysis of a transistor:

– re model
– Hybrid equivalent model

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 BJT Transistor Modeling
Capacitors chosen with very
small reactance at the frequency
of application → replaced by
low-resistance or short circuit.

Removal of the dc supply and

insertion of the short-circuit
equivalent for the capacitors.
Electronic Devices and Circuit Theory, 10/e Dr. Talal Skaik 2014 Copyright ©2009 by Pearson Education, Inc.
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 BJT Transistor Modeling
Circuit redrawn for small-
signal ac analysis

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The re Transistor Model Common Emitter Configuration

V i V be
Zi  
Ib Ib
V be  I e re   I c  I b  re    I b  I b  re
    1 I b re
V be    1 I b re
Zi       1 re  re
Ib Ib
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The re Transistor Model Common Emitter Configuration

26 mV
re 
IE

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The re Transistor Model
Common Emitter Configuration

I C 1
slope  
V CE r0
V CE
r0 
I C

The output resistance r is

typically in the range of
40 kΩ to 50 kΩ

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 Common-Base Configuration

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 Common-Base
Configuration

The output resistance

r0 is quite high.
typically extend into
the megaohm range.

Common Base re
equivalent circuit

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 Common Emitter Fixed Bias Configuration

Network after the removal of the effects

Common-emitter fixed-bias of VCC, C1 and C2.
configuration.

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Common Emitter Fixed Bias Configuration

Substituting the re model into the network.

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 Common Emitter Fixed Bias Configuration
Input impedance:
Z i  R B ||  re
Z i   re R E  10 re

Output impedance:
Z o  R C || rO
Z o  R C ro  10R C Voltage gain:
Vi  Vi 
Vo    I b (R C ||ro ) , I b  , Vo      (R C ||ro )
 re   re 
Vo (R C ||ro ) RC
Av   , Av   ro 10R C
Vi re re

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 Common Emitter Fixed Bias Configuration

Vo (R ||r )
Av   C o
Vi re

Demonstrating the 180°phase shift between input and

output waveforms.

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Example 5.1
Determine re, Zi (with ro=∞), Zo (with ro=∞),
Av (with ro=∞).
Repeat with ro=50 kΩ.

Electronic Devices and Circuit Theory, 10/e Dr. Talal Skaik 2014 Copyright ©2009 by Pearson Education, Inc.
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Example 5.1 - Solution

Electronic Devices and Circuit Theory, 10/e Dr. Talal Skaik 2014 Copyright ©2009 by Pearson Education, Inc.
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Common-Emitter
Voltage-Divider Bias

re model requires you to determine , re, and ro.

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 Common-Emitter Voltage-Divider Bias
Input impedance:
R   R 1 || R 2
Z i  R  ||  re

Output impedance:
Z o  R C || ro
Z o  R C ro  10R C
Voltage gain:
Vi  Vi 
Vo    I b (R C ||ro ) , I b  , Vo      (R C ||ro )
 re   re 
Vo (R ||r ) RC
Av   C o , Av   ro 10R C
Vi re re

Electronic Devices and Circuit Theory, 10/e Dr. Talal Skaik 2014 Copyright ©2009 by Pearson Education, Inc.
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Example 5.2
Determine re, Zi , Zo (with ro=∞), Av (with
ro=∞). Repeat with ro=50 kΩ.

Electronic Devices and Circuit Theory, 10/e Dr. Talal Skaik 2014 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky 18 Upper Saddle River, New Jersey 07458 • All rights reserved.
Example 5.2 - Solution

Electronic Devices and Circuit Theory, 10/e Dr. Talal Skaik 2014 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky 19 Upper Saddle River, New Jersey 07458 • All rights reserved.
Common-Emitter
Emitter-Bias Configuration

Electronic Devices and Circuit Theory, 10/e Dr. Talal Skaik 2014 Copyright ©2009 by Pearson Education, Inc.
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Impedance Calculations
Input impedance:
V i  I b  re  I e R E
V i  I b  re     1 I b R E
Vi
Zb    re     1 R E
Ib
Z b   re   R E    re  R E 
Z b   RE for R E  re
Output impedance:
Zi  R B ||Zb Zo  R C

Electronic Devices and Circuit Theory, 10/e Dr. Talal Skaik 2014 Copyright ©2009 by Pearson Education, Inc.
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Gain Calculations
Voltage gain:
Vo  I o RC    I b RC
Vi 
Vo      RC
 Zb 
Vo  RC
Av  
Vi Zb
substituting Zb   (re  R E )
Vo RC
Av  
Vi re  R E
and for the approximation Zb   R E
Vo R
Av   C
Vi RE

Electronic Devices and Circuit Theory, 10/e Dr. Talal Skaik 2014 Copyright ©2009 by Pearson Education, Inc.
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Example 5.3 Without CE (unbypassed):
Determine re, Zi , Zo , Av . ignore ro for ro ≥ 10(RC+RE)

Electronic Devices and Circuit Theory, 10/e Dr. Talal Skaik 2014 Copyright ©2009 by Pearson Education, Inc.
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 Emitter-Follower Configuration

• This is also known as the common-collector configuration.

• The input is applied to the base and the output is taken from the emitter.
• There is no phase shift between input and output.

Electronic Devices and Circuit Theory, 10/e Dr. Talal Skaik 2014 Copyright ©2009 by Pearson Education, Inc.
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Impedance Calculations

Input impedance:

Zi  R B ||Zb
Zb   re  (  1)R E
Zb   (re  R E )
Zb   R E (for R E >>re )

Electronic Devices and Circuit Theory, 10/e Dr. Talal Skaik 2014 Copyright ©2009 by Pearson Education, Inc.
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Impedance Calculations
Output impedance:
Vi
Ib  , Ie =( +1)I b
Zb
Vi
 ( +1)
Zb
( +1)V i
Ie 
 re  (  +1)R E
sin ce ( +1)  
Vi
Ie 
re  R E
To determine Zo , V i is set to zero
Zo  R E ||re , Zo  re R E  re

Electronic Devices and Circuit Theory, 10/e Dr. Talal Skaik 2014 Copyright ©2009 by Pearson Education, Inc.
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Gain Calculations
Voltage gain:

RE
Vo  Vi
R E  re
Vo RE
Av  
Vi R E  re
Vo
Av  1 R E  re , R E  re  R E
Vi

Electronic Devices and Circuit Theory, 10/e Dr. Talal Skaik 2014 Copyright ©2009 by Pearson Education, Inc.
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Example 5.7 Determine re, Zi , Zo , Av .

Electronic Devices and Circuit Theory, 10/e Dr. Talal Skaik 2014 Copyright ©2009 by Pearson Education, Inc.
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Example 5.7 - solution

Electronic Devices and Circuit Theory, 10/e Dr. Talal Skaik 2014 Copyright ©2009 by Pearson Education, Inc.
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 Islamic University of Gaza
Chapter 5:
BJT AC Analysis Dr. Talal Skaik
 Common-Base Configuration
• The input is applied to the
emitter.
• The output is taken from the
collector.
• Low input impedance.
• High output impedance.
• Very high voltage gain.
• No phase shift between input
and output.

Electronic Devices and Circuit Theory, 10/e Dr. Talal Skaik 2014 Copyright ©2009 by Pearson Education, Inc.
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 Calculations
Input impedance:
Z i  R E || re

Output impedance:
Zo  R C

Voltage gain:
Vo  I o RC  (I C )RC Current gain:
  I e RC
Assuming R E  re
Vi V i 
Ie   Vo     RC Ie  I i
re  re 
V  RC RC I o   I e   I i
Av  o  
Vi re re Io
A i     1
Ii
Av positive… Vi and Vo in phase.
Electronic Devices and Circuit Theory, 10/e Dr. Talal Skaik 2014 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky 3 Upper Saddle River, New Jersey 07458 • All rights reserved.
Example 5.8
Determine re, Zi , Zo , Av , Ai

Electronic Devices and Circuit Theory, 10/e Dr. Talal Skaik 2014 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky 4 Upper Saddle River, New Jersey 07458 • All rights reserved.
Common-Emitter Collector Feedback Configuration

• This is a variation of the common-emitter fixed-bias configuration

• Input is applied to the base
• Output is taken from the collector
• There is a 180 phase shift between input and output

Electronic Devices and Circuit Theory, 10/e Dr. Talal Skaik 2014 Copyright ©2009 by Pearson Education, Inc.
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Calculations
Output impedance:
Zo  R C ||R F

Voltage gain:
Io  Ib  I '
For  I b  I '  I o   I b
V o   I o RC     I b  RC
Vi Vi
Ib  V o    RC
 re  re
Vo RC Defining Zo
Av  
Vi re

Electronic Devices and Circuit Theory, 10/e Dr. Talal Skaik 2014 Copyright ©2009 by Pearson Education, Inc.
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Calculations Input impedance:
Vi V
Zi  , V o   i RC
Ii re
V o V i V o V i RV V 1  RC 
I '    C i  i  1  V i
RF RF RF re R F R F RF  re 
V i  I b  re  (I i  I ')  re  I i  re  I '  re
1  RC 
V i  I i  re  1    rV
e i
RF  re 
  re  RC  
or Vi 1  1     I i  re
 RF  re  
V  re
Zi  i 
Ii  re  RC 
1 1
R F  re 
re
R R  re Zi 
1 C  C  Z i  1 RC
re re  RC 
1
RF  RF
Electronic Devices and Circuit Theory, 10/e Dr. Talal Skaik 2014 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky 7 Upper Saddle River, New Jersey 07458 • All rights reserved.
Determining the current gain using the voltage gain

Io Vi Vo
Current Gain Ai  , Ii  , Io  
Ii Zi RL
Vo

I RL Vo Z i
Ai L  o   .
Ii Vi V i RL
Zi
Zi
A iL  Av L
RL

Electronic Devices and Circuit Theory, 10/e Dr. Talal Skaik 2014 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky 8 Upper Saddle River, New Jersey 07458 • All rights reserved.
Determining the current gain using the voltage gain
From example 5.2
Zi=1.35 kΩ.
Av=-368.76
Io
Current Gain A i  ,
Ii
Vi Vo
Ii  , Io  
1.35k 6.8k
Vo

I V 1.35k
A i L  o  6.8k   o .
Ii Vi V i 6.8k
1.35k
1.35k
 (368.76)  73.2
6.8k
Z 1.35k
or A iL  Av L i  (368.76)  73.2
RL 6.8k

Electronic Devices and Circuit Theory, 10/e Dr. Talal Skaik 2014 Copyright ©2009 by Pearson Education, Inc.
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 Effect of RL and RS

Vo Vo
AvNL  , AvL  , with R L
Vi Vi
Vo
AvS  , with R L and R S
Vs

Electronic Devices and Circuit Theory, 10/e Dr. Talal Skaik 2014 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky 10 Upper Saddle River, New Jersey 07458 • All rights reserved.
 Effect of RL and RS

Vi
Vo    I b (R C ||ro ||R L ) =   I b (R C ||R L ) , I b  ,
 re
 Vi  Vo (R C ||R L )
Vo      (R C ||R L )  A vL  
  re  Vi re

Electronic Devices and Circuit Theory, 10/e Dr. Talal Skaik 2014 Copyright ©2009 by Pearson Education, Inc.
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 Effect of RL and RS

Input impedance: Zi  R B || re

Output Impedance: Zo  R C ||rO
Z iV s Vi Zi
To find overall gain: V i  , 
Z i  Rs V S Z i  Rs
Vo Vo Vi Zi Zi
AvS   .  AvL  AvS  AvL
VS Vi VS Z i  Rs Z i  Rs
Electronic Devices and Circuit Theory, 10/e Dr. Talal Skaik 2014 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky 12 Upper Saddle River, New Jersey 07458 • All rights reserved.
 Darlington Connection

•The Darlington circuit provides a very high current gain—the

product of the individual current gains: D = 12
•A Darlington transistor connection provides a transistor having a
very large current gain, typically a few thousand.
•Darlington pairs are available as complete packages.
•A Darlington pair is sufficiently sensitive to respond to the small
current.
Electronic Devices and Circuit Theory, 10/e Dr. Talal Skaik 2014 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky 13 Upper Saddle River, New Jersey 07458 • All rights reserved.
 DC Bias of Darlington Circuits
Base current:
VCC  VBE
IB 
R B   DR E

Emitter current:
I E  ( D  1)I B   DI B

Emitter voltage:
VE  I E R E

Base voltage:
VB  VE  VBE
Electronic Devices and Circuit Theory, 10/e Dr. Talal Skaik 2014 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky 14 Upper Saddle River, New Jersey 07458 • All rights reserved.
 Darlington Circuits

When light falls on the LDR,

its resistance reduces.
The bias voltage is supplied to
the transistor and this voltage is
enough to make the transistor
and relay work.
A variable resistor is also
connected on the base of
transistor to adjust the
sensitivity.

Electronic Devices and Circuit Theory, 10/e Dr. Talal Skaik 2014 Copyright ©2009 by Pearson Education, Inc.
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 CHAPTER 6

Field Effect Transistors

 4.1 INTRODUCTION
• The field-effect transistor (FET) is a three-terminal
device used for a variety of applications that match,
to a large extent, those of the BJT transistor.

• Although there are important differences between

the two types of devices, there are also many
similarities that will be pointed out in the sections
to follow.
Contd…
FETs vs. BJTs

Similarities:
 Amplifiers , Switching devices , Impedance matching circuits
Differences:
 FETs are voltage controlled devices. BJTs are current controlled devices.
 The BJT transistor is a bipolar device, The FET is a unipolar device
 FETs have a higher input impedance because reverse biased of gate
source. BJTs have higher current gains.
 FETs are less sensitive to temperature variations and are more easily integrated
on ICs.
 FETs are generally more static sensitive than BJTs.
 In JFET, there are no junctions as in an ordinary transistor. The conduction is
through an n- type or p-type semi-conductor material. For this reason, noise level in
3
JFET is very small.
Contd…
• In BJT a current level and in the FET an applied
voltage.
• For the FET an electric field is established by the
charges present that will control the conduction path
of the output circuit;
Without the need for direct contact between
the controlling and controlled quantities.
Contd…

BJT and JFET Transistor

Contd…
FET types
• JFET: Junction FET
• MOSFET: Metal–Oxide–Semiconductor FET
 D-MOSFET: Depletion MOSFET
 E-MOSFET: Enhancement MOSFET
N-Channel JFET
Symbol P-Channel JFET
Symbol
 JFET Construction
• The n-channel is more widely used.
• There are three terminals:
• Drain (D) and Source (S) are connected to the
n-channel, Gate (G) is connected to the p-type
material
 JFET Operation: The Basic Idea
• JFET operation can be compared to a
water spigot.
• The source of water pressure is the
accumulation of electrons at the
negative pole of the drain-source
voltage.

• The drain of water is the electron

deficiency (or holes) at the positive
pole of the applied voltage.

• The control of flow of water is the gate

voltage that controls the width of the
n-channel and, therefore, the flow of
charges from source to drain.
Water analogy for the JFET
control mechanism.
 JFET Operation (cont).
 Since the n-channel JFET is a normally-ON device and if VGS is
sufficiently negative enough, the drain-source conductive
channel closes (cut-off) and the drain current reduces to zero.
 For the n-channel JFET, the closing of the conductive channel
between drain and source is caused by the widening of the p-
type depletion region around the gate until it completely
closes the channel. N-type depletion regions close the
channel for a p-channel JFET.
 So by setting the gate-source voltage to some pre-determined
fixed negative value, we can cause the JFET to conduct
current through its channel at a certain value between zero
amperes and IDSS respectively making it an ideal FET current
source.
 Hence, JFET is always operated with the gate-source pn
junction reverse-biased otherwise the JFET will operate ID
beyond its maximum value
 JFET Operating Characteristics
There are three basic operating conditions for
a JFET:
VGS = 0 V, VDS Some Positive Value and
increasing to some value
VGS < 0, VDS at some positive value
Voltage-controlled resistor
Case I: VGS = 0 V, VDS Some Positive Value
Contd…
• If a positive voltage VDS has been applied across the channel and the
gate has been connected directly to the source to establish the
condition VGS =0 V.
• The result is a gate and source terminal at the same potential and a
depletion region in the low end of each p-material similar to the
distribution of the no-bias conditions

JFET in the VGS=0 V

and VDS > 0 V.
Contd…
 The instant the voltage VDD ( VDS) is applied, the
electrons will be drawn to the drain terminal,
establishing the conventional current ID
The path of charge flow clearly reveals that the drain and
source currents are equivalent (ID = IS).
 It is important to note that the depletion region is
wider near the top of both p type materials.
 Assuming a uniform resistance in the n-channel, the
resistance of the channel can be broken down to the
divisions appearing in Figure below.
 The current ID will establish the voltage levels through
the channel as indicated on the same figure.
Contd…
The result is that the upper region of the p-type
material will be reverse biased by about 1.5 V,
And the lower region is only reverse-biased by 0.5
V.

Figure: Varying reverse-

bias potentials across
the p-n junction of an n-
channel JFET.
Contd…
• Recall from the discussion of the diode operation
that the greater the applied reverse bias,
 The wider the depletion.
• The fact that the p-n junction is reverse-biased for
the length of the channel; results in a gate current
of zero amperes.
• The fact that IG = 0 A is an important characteristic
of the JFET.
Contd….
Case II: VGS = 0 V and VDS increasing to some
positive value
• Three things happen when VGS = 0 and VDS is increased from
0 to a more positive voltage
1, The depletion region between p-gate and n-channel increases
as electrons from n-channel combine with holes from p-gate.
2, Increasing the depletion region, decreases the size of
the n-channel which increases the resistance of the n-
channel.
3, Even though the n-channel resistance is increasing,
• The current (ID) from source to drain through the
n-channel is increasing. This is because Vds is
increasing.
Contd…

VGS = 0 V and VDS increasing to some positive value

JFET Operating Characteristics: Pinch Off
• As the voltage VDS is increased from 0 to a few volts;
the current will increase as determined by Ohm’s
law and the plot of ID versus VDS is relatively straight
line
• The relative straightness of the plot reveals that for
the region of low values of VDS; the resistance is
essentially constant.
• As VDS increases and approaches a level referred to as
VP;the depletion regions will widen and causing a
noticeable reduction in the channel width.
Contd…
• The reduced path of conduction causes the
resistance to increase.
• If VDS is increased to a level where; it appears
that the two depletion regions would “touch” a
condition referred to as pinch-off will result.
• The level of VDS that establishes this condition
is referred to as the pinch-off voltage(VP)
• When VDS reaches VP; ID maintains a saturation
level defined as IDSS.
• In reality a very small channel still exists, with a
current of very high density
Contd…
• The fact that ID does not drop off at pinch-off and maintains the
saturation level is verified by the following fact:
• The absence of a drain current would remove the possibility of
different potential levels through the n-channel material; to establish
the varying levels of reverse bias along the p-n junction.
• The result would be a loss of the depletion region distribution that
caused pinch-off in the first place.

Pinch-off (VGS =0 V, VDS =VP).

JFET Operating Characteristics: Saturation
• At the pinch-off point:
• Any further increase in VDS does not produce any increase in ID.
VDS at pinch-off is denoted as Vp. ID is at saturation or maximum.
It is referred to as IDSS. The ohmic value of the channel is
maximum.

ID versus VDS for

VGS = 0 V.
 Plotting the JFET Transfer Curve
• Using IDSS and Vp (VGS(off)) values found in a
specification sheet,
– the transfer curve can be plotted according to these
three steps:
Step 1
2
 VGS 
I D  I DSS 1  
 V 
 GS(Off) 

Solving for VGS = 0V ID = IDSS

Step 2  VGS 
2

I D  I DSS 1   Step 3
 V 
 GS(Off)  2
 VGS 
I D  I DSS 1  
 V 
Solving for VGS = -Vp = VGS(off), ID = 0A  GS(Off) 
Solving for VGS = 0V to Vp
Contd…
• Therefore, once VDS > VP the JFET has the
characteristics of a current source.
• As shown in Figure below, the current is fixed at ID =
IDSS, but the voltage VDS (for levels > VP) is
determined by the applied load.

Figure : Current source

equivalent for VGS = 0 V, VDS > VP.
 Case III: VGS < 0, VDS at some positive value
• As VGS becomes more negative, the depletion region
increases.
Application of a negative
voltage to the gate of a
JFET.
As VGS becomes more negative:
The JFET experiences pinch-off at a
lower voltage value of VDS. The
effect of the applied negative-bias
VGS is; to establish depletion
regions similar to those obtained
with VGS = 0 V but at lower levels of
VDS.
Contd…
• Therefore, the result of applying a negative bias
to the gate is to reach the saturation level at a
lower level of VDS
• As VGS is made more and more negative;
The resulting saturation level for ID has been
reduced and in fact will continue to decrease.
• Eventually, when VGS=-VP, It will be sufficiently
negative to establish a IDSS saturation level that is
essentially 0 mA, and for all practical purposes
the device has been “turned off.”
Contd…

Figure: n-Channel JFET characteristics with IDSS = 8 mA

and VP=4 V ( for VGS = 0 V)
Contd…
• At point where ID reaches 0 A. VGS is equal to -Vp
or VGS(off)(Cut-off voltage)
• Also note that at high levels of VDS the JFET
reaches a breakdown situation. ID increases
uncontrollably if VDS > VDSmax.
• The region to the right of the pinch-off Locus is
the region typically employed in linear
amplifiers. linear amplifiers(amplifiers with
minimum distortion of the applied signal).
 JFET as Voltage-Controlled Resistor
• The region to the left of the pinch-off point is called the
ohmic region.
• The JFET can be used as a variable resistor, where VGS
controls the drain-source resistance (rd).As VGS
becomes more negative, the resistance (rd)
increases.
ro where ro is the resistance with VGS
rd  2 = 0 V, and
 
1  VGS  rd the resistance at a particular
 V 
 GS(Off)  level of VGS.
 p-Channel JFETS
• The p-channel JFET behaves the same as the n-
channel JFET, except the voltage polarities and
current directions are reversed.

p-Channel JFET.
Contd…
p-Channel JFET Characteristics
• As VGS increases more positively
• The depletion zone increases(I.e resistance increases)
• ID decreases (ID < IDSS)
• Eventually ID = 0 A
• Also note that at high levels of VDS the JFET reaches a
breakdown situation: ID increases uncontrollably if VDS >
VDSmax.
Contd…

p-Channel JFET characteristics with IDSS = 6 mA and

VP=6 V(VGS = 0 V)
 JFET Transfer Characteristics
• The transfer characteristic of input-to-output is not as
straightforward in a JFET as it is in a BJT.
In a BJT,  indicates the relationship between IB (input)
and IC (output).
• In a JFET, the relationship of VGS (input) and ID
(output) is a little more complicated:
2
 
 
 V  Shockley’s
ID  I 1
DSS 
GS 


V 
 equation
 GS(Off) 
 JFET Transfer Characteristics Curve

This graph shows the value of ID for a given

value of VDS.
Example 1.Figure below shows the transfer characteristic curve of a JFET. Write the
equation for drain current.

Solution.
Referring to the transfer characteristic curve
we have,

Example 2. A JFET has the following parameters: IDSS = 32 mA ; VGS (off) = – 8V ;

VGS = – 4.5 V. Find the value of drain current.

12/26/2024 Dessie Fentaw 34

Example 3. A JFET has a drain current of 5 mA. If IDSS = 10 mA and VGS (off) = – 6 V,
find the value of (i) VGS and (ii) VP.

12/26/2024 Dessie Fentaw 35

 Example 4. For the JFET in Figure below VGS (off) = – 4V and IDSS = 12 mA.
Determine the minimum value of VDD required to put the device in the constant-current
region of operation.

Solution.
Since VGS (off) = – 4V, VP = 4V. The minimum
value of VDS for the JFET to be in
constant-current region is
VDS = VP = 4V
In the constant current region with VGS = 0V,
ID = IDSS = 12 mA
Applying Kirchhoff’s voltage law around the drain
circuit, we have,
VDD = VDS +V RD = VDS + ID RD
= 4V + (12 mA) (560Ω) = 4V + 6.72V = 10.72V
This is the value of VDD to make VDS = VP and put
the device in the constant-current region.
12/26/2024 Dessie Fentaw 36
 FET Small-Signal Model
Transconductance: The relationship of a change in ID to the
corresponding change in VGS is called transconductance,
Transconductance is denoted gm and given by:
ΔI D
gm 
ΔV GS

Input impedance: Z i  

1
Output Impedance: Z o  rd 
y os
VDS
where: rd  VGS  constant
I D 37
FET AC Equivalent Circuit

38
 JFET Biasing
For the proper operation of n-channel JFET, gate must be negative w.r.t.
source. This can be achieved either by inserting a battery in the gate circuit
or by a circuit known as biasing circuit.
1. Bias battery. In this method, JFET is biased by a bias battery VGG. This
battery ensures that gate is always negative w.r.t. source during all parts of
the signal.
2. Biasing circuit. The biasing circuit uses supply voltage VDD to provide
the necessary bias. Two most commonly used methods are
(i) self-bias
(ii) (ii) potential divider method.

12/26/2024 Dessie Fentaw 39

 JFET Biasing by Bias Battery
Figure shows the biasing of a n-channel JFET by a bias
battery – VGG.
This method is also called gate bias. The battery voltage
– VGG ensures that gate – source junction remains reverse
biased. Since there is no gate current, there will be no
voltage drop across RG.
 VGS = VGG
We can find the value of drain current ID from the
following relation

12/26/2024 Dessie Fentaw 40

 Self-Bias for JFET
Figure shows the self-bias method for n-channel
JFET. The resistor RS is the bias resistor. The d.c.
component of drain current
flowing through RS produces the desired bias
voltage. Voltage across RS, VS = ID RS
Since gate current is negligibly small, the gate
terminal is at d.c. ground i.e., VG = 0.
VGS = VG − VS = 0 − ID RS
or VGS = − ID RS
Thus bias voltage VGS keeps gate negative w.r.t.
source

VGS = VG – VS = Negative. This means that VG is negative w.r.t. VS. Thus if VG = 2V and VS
= 4V, then VGS = 2 – 4 = – 2V i.e. gate is less positive than the source.

12/26/2024 Dessie Fentaw 41

12/26/2024 Dessie Fentaw 42
Example 5. Find VDS and VGS in Figure, given that ID = 5 mA.

12/26/2024 Dessie Fentaw 43

Example 6. In a self-bias n-channel JFET, the operating point is to be set at ID = 1.5 mA
and VDS =10 V. The JFET parameters are IDSS = 5 mA and VGS (off) = − 2 V. Find the
values of RS and RD. Given that VDD = 20 V.
Solution.

12/26/2024 Dessie Fentaw 44

 JFET with Voltage-Divider Bias

Figure shows potential divider method of biasing a

JFET. This circuit is identical to that used for a
transistor. The resistors R1 and R2 form a voltage
divider across drain supply VDD. The voltage V2 (=
VG)across R2 provides the necessary bias.

The circuit is so designed that ID RS is larger than V2 so

that VGS is negative. This provides correct bias voltage. We
can find the operating point as under :

12/26/2024 Dessie Fentaw 45

Example 7. Determine ID and VGS for the JFET with voltage-divider bias in Figure
given that VD = 7V.

12/26/2024 Dessie Fentaw 46

EX. In an n-channel JFET biased by potential divider method, it is desired to set the
operating point at ID = 2.5 mA and VDS = 8V. If VDD = 30 V, R1 = 1 MΩ and R2 =
500 kΩ, find the value of RS. The parameters of JFET are IDSS = 10 mA and VGS
(off) = – 5 V. For the figure below

12/26/2024 Dessie Fentaw 47

 D.C. and A.C. Equivalent Circuits of JFET

 Like in a transistor amplifier, both d.c. and a.c. conditions prevail in a JFET
amplifier. The d.c. sources set up d.c. currents and voltages whereas the a.c.
source (i.e. signal) produces fluctuations in the JFET currents and voltages
 . Therefore, a simple way to analyse the action of a JFET amplifier is to split
the circuit into two parts viz.
 d.c. equivalent circuit and a.c. equivalent circuit.
 The d.c. equivalent circuit will determine the operating point (d.c. bias
levels) for the circuit while a.c. equivalent circuit determines the output
voltage and hence voltage gain of the circuit.

12/26/2024 Dessie Fentaw 48

 We shall split the JFET amplifier shown in Figure below

12/26/2024 Dessie Fentaw 49

 1. D. C. equivalent circuit.
In the d.c. equivalent circuit of a JFET amplifier, only d.c. conditions are considered

 Reduce all a.c. sources to zero.

 Open all the capacitors.
Applying these two steps to the JFET
amplifier circuit shown above , we get the
d.c. equivalent circuit
shown here. We can easily calculate the
d.c. currents and voltages from this
circuit

The d.c. equivalent circuit of a JFET amplifier

using voltage-divider bias . It is clear that :
VDD = VDS + ID (RD + RS)
or VDS = VDD – ID (RD + RS)

12/26/2024 Dessie Fentaw 50

2. A. C. equivalent circuit.
In the a.c. equivalent circuit of a JFET amplifier, only a.c. conditions are to be considered.
The capacitors are generally used to couple or bypass the a.c. signal. The designer
intentionally selects capacitors that are large enough to appear as short circuits to the a.c.
signal. It follows, therefore, that in order to draw the a.c. equivalent circuit, the following
two steps are applied to the JFET amplifier circuit :
(i) Reduce all d.c. sources to zero (i.e. VDD = 0).
(ii) Short all the capacitors.

12/26/2024 Dessie Fentaw 51

 Calculations
Input impedance:
Zi  RG

Output impedance:

Z o  rd || R D

Zo  R D
rd  10R D

Voltage gain:

A v   g m (rd || R D )

A v  g m R D
rd  10R D

52
 Voltage Gain of JFET Amplifier
(i) for facility of reference. Note that R1 || R2 and can be replaced by a single
resistance RT. Similarly, RD || RL and can be replaced by a single resistance RAC (=
total a.c. drain resistance). The a.c. equivalent circuit can be of

We now find the expression for voltage gain of this amplifier. Referring to Fig. 19.36
(ii), output voltage (vout) is given by ;
vout = id RAC

12/26/2024 Dessie Fentaw 53

 But vout /vin is the voltage gain (Av) of the amplifier.
∴ Voltage gain, Av = gm RAC for loaded amplifier
= gm RD for unloaded amplifier
12/26/2024 Dessie Fentaw 54
 Calculations
Input impedance:

Z i  R1 || R 2

Output impedance:

Z o  rd || R D

Zo  R D
rd  10R D

Voltage gain:
A v   g m (rd || R D )

A v  g m R D
rd  10R D

55
 Example 8. The JFET in the amplifier of Figure given has a transconductance
gm = 1 mA/V. If the source resistance RS is very small as compared to RG,
find the voltage gain of the amplifier.

Transconductance of JFET, gm= 1

mA/V =

The total ac load (i.e. RAC) in the drain circuit consists of the parallel combination of RD
and RL i.e.
Total a.c. load, RAC = RD || RL
= 12 kΩ || 8 kΩ = 4.8 kΩ

12/26/2024 Dessie Fentaw 56

 Islamic University of Gaza
Chapter 6:
Field-Effect Transistors Dr. Talal Skaik
 FETs vs. BJTs

Similarities:
• Amplifiers
• Switching devices
• Impedance matching circuits

Differences:
• FETs are voltage controlled devices. BJTs are current controlled
devices.
• FETs have a higher input impedance. BJTs have higher gains.
• FETs are less sensitive to temperature variations and are more
easily integrated on ICs.

Electronic Devices and Circuit Theory, 10/e 2 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
 FET Types

•JFET: Junction FET

•MOSFET: Metal–Oxide–Semiconductor FET

D-MOSFET: Depletion MOSFET

E-MOSFET: Enhancement MOSFET

Electronic Devices and Circuit Theory, 10/e 3 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
 JFET Construction
There are two types of JFETs
•n-channel
•p-channel
The n-channel is more widely
used.

There are three terminals:

•Drain (D) and Source (S) are

connected to the n-channel
•Gate (G) is connected to the p-
type material

Water analogy for the

JFET control mechanism.
Electronic Devices and Circuit Theory, 10/e 4 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
 JFET Operating Characteristics:
VGS = 0 V , VDS some positive value
When VGS = 0 and VDS is increased from 0 to a more positive voltage:

• The depletion region between p-

gate and n-channel increases.
• Increasing the depletion region,
decreases the size of the n-
channel which increases the
resistance of the n-channel.
• Even though the n-channel
resistance is increasing, the
current (ID) from source to drain
through the n-channel is
increasing. This is because VDS is
increasing.
Electronic Devices and Circuit Theory, 10/e 5 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
 JFET Operating Characteristics:
VGS = 0 V , VDS some positive value

ID versus VDS for VGS = 0 V.

Electronic Devices and Circuit Theory, 10/e 6 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
 JFET Operating Characteristics: Pinch Off
If VGS = 0 and VDS is further increased to
a more positive voltage, then the
depletion zone gets so large that it pinches
off the n-channel.

As VDS is increased beyond |VP|, the level

of ID remains the same (ID=IDSS).

IDSS is the maximum drain current

for a JFET and is defined by the
conditions VGS=0 and VDS > |VP|.
Electronic Devices and Circuit Theory, 10/e 7 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
 JFET Operating Characteristics , VGS<0
•As VGS becomes more negative,
the depletion region increases.
•The more negative VGS, the
resulting level for ID is reduced.
•Eventually, when VGS=VP (-ve)
[VP=VGS(off)], ID is 0 mA. (the device
is “turned off”.

•The level of VGS that results in

ID=0 mA is defined by VGS=VP,
with VP being a negative voltage for
n-channel devices and a positive
voltage for p-channel JFETs. Application of a negative
voltage to the gate of a JFET.

Electronic Devices and Circuit Theory, 10/e 8 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
 JFET Operating Characteristics

n-Channel JFET characteristics with IDSS = 8 mA and VP = -4 V.

Electronic Devices and Circuit Theory, 10/e 9 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
 JFET Operating Characteristics:
Voltage-Controlled Resistor
•The region to the left of
the pinch-off point is called
the ohmic region.

•The JFET can be used as a

variable resistor, where VGS
controls the drain-source
resistance (rd). As VGS
becomes more negative, the
resistance (rd) increases.
ro
rd  where ro is the resistance with
2
 VGS  VGS=0 and rd is the resistance at a
 1  
 VP  particular level of VGS.

Electronic Devices and Circuit Theory, 10/e 10 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
 p-Channel JFETS

The p-channel JFET behaves

the same as the n-channel JFET,
except the voltage polarities and
current directions are reversed.

Electronic Devices and Circuit Theory, 10/e 11 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
 p-Channel JFET Characteristics

As VGS increases more positively

• The depletion zone

increases
• ID decreases (ID < IDSS)
• Eventually ID = 0 A

Also note that at high levels of VDS the JFET reaches a breakdown situation:
ID increases uncontrollably if VDS > VDSmax.

Electronic Devices and Circuit Theory, 10/e 12 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
 JFET Symbols

JFET symbols: (a) n-channel; (b) p-channel.

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(a) VGS = 0 V, ID = IDSS; (b) cutoff (ID = 0 A) VGS less than (more negative than) the
pinch-off level; (c) ID is between 0 A and IDSS for VGS ≤ 0 V and greater than the
pinch-off level.

Electronic Devices and Circuit Theory, 10/e 14 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
 JFET Transfer Characteristics
In a BJT,  indicates the relationship between IB (input)
and IC (output).

In a JFET, the relationship of VGS (input) and ID (output)

is a little more complicated (Shockley’s equation):

2
 V 
I D  I DSS  1  GS 
 V 
 P 

William Bradford Shockley

(1910–1989)
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 JFET Transfer Curve

This graph shows the value of ID for a given value of VGS.

Electronic Devices and Circuit Theory, 10/e 16 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
 Plotting the JFET Transfer Curve
Using IDSS and Vp (VGS(off)) values found in a specification sheet, the
transfer curve can be plotted according to these three steps:
Step 1
2
 V 
I D  I DSS  1  GS 
 VP 
Solving for VGS = 0V ID = IDSS
Conversely , for a given
Step 2
 V 
2 ID, VGS can be obtained:
I D  I DSS  1  GS 
 VP 
 ID 
Solving for VGS = Vp (VGS(off)) ID = 0A VGS  VP 1  
 IDSS 
Step 3
2
 V 
Solving for VGS = 0V to Vp I D  I DSS  1  GS 
 VP 

 1 
2

i.e. For VGS = -1 V I D  8mA 1    4.5mA

 4 

Electronic Devices and Circuit Theory, 10/e 17 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.
Example 6.1
Sketch the transfer curve defined by IDSS=12 mA and VP=-6V.

2
 V 
I D  I DSS  1  GS 
 VP 

 ID 
VGS  VP 1  
 IDSS 

Electronic Devices and Circuit Theory, 10/e 18 Copyright ©2009 by Pearson Education, Inc.
Robert L. Boylestad and Louis Nashelsky Dr. Talal Skaik 2014 Upper Saddle River, New Jersey 07458 • All rights reserved.