Session 6

Extraction
Physical verification
Prepared by:
On-chip variation
ICpedia PnR Team
Extraction

2
What is Required for Extraction?
Layout
Process Info

Extractor

Parasitic Netlist

3
Star-RCXT Flow
Process Modeling Cell-Level Transistor-Level

ITF Milkyway or LEF/DEF GDSII

grdgenxo
Hercules or
Calibre
models StarXtract Command File

Layer Mapping xTractor

Field Solver

Netlist Reports Reports

4
Example: Layer Mapping File
conducting_layers Design to

• metal1 M1 Process (GRD)

• metal2 M2 Layer mapping

• metal3 M3
via_layers
• via1 VIA1
• via2 VIA2
marker_layers
remove_layers
• TEXT

5
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 Example: Command File
* This is a Comment
BLOCK : TOP
MILKYWAY_DATABASE : xtdesign
TCAD_GRD_FILE : Tech.nxtgrd
MAPPING_FILE : xt.mapping
NETLIST_FORMAT : SPEF
COUPLE_TO_GROUND : NO * default is YES

Command Value

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38
FAQ (Frequently Asked
Questions)

7
41
Star RCXT flows
• What are all the possible flows with Star-RCXT?
• What types of I/P database are supported?
• MW DB:
• Cell level Xtraction
• Lef Def:
• Cell level Xtraction
• GDS:
• Cell or Txr level Xtraction
• CCI :
• Cell or Txr level Xtraction

8
42
Post Star RCXT flow
• What is the post-STAR-RCXT flow? In other words, the SPF/SPEF is i/p for which tools?
• Simulation:
• The parasitic netlist is given to simulation tools (hspice,nanosim) for simulation purposes
• STA:
• The parasitic netlist is given to STA tools (Primetime) for STA analysis .
• IR drop:
• The power n/w in Parasitic netlist is given to IR drop analysis tools (Astro Rail).
• Xtalk:
• The Coupling cap in parasitic netlist is given to Xtalk tools(PrimetimeSI)
• NOTE: It’s not limited to the above tools only.

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43
STA review

10
Basics of Static Timing analysis
• Static Timing Analysis (STA) is a method for determining if a circuit
meets timing constraints without having to simulate.
Derates and
Constraints .SPEF Gatelevel netlist (.v) SC .libs Uncertainites

Static Timing Analysis (PT)

Timing reports SDF files

11
 Timing paths
- Three main steps are followed by STA tools (ex.
PT):
1. Circuit is broken down into sets of timing
paths.
2. Delay of each path is calculated.
3. Path delays are checked to see if timing
constraints have been met.

A timing path is a point-to-point path in a design

which can propagate data from one flip-flop to
another

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Timing Path Types
There are 4 types of paths in any synchronous circuit

register-to- register-to-output
input-to-register (in2reg)
register(reg2reg) (reg2out)

D Q D Q
DFF DFF

CLK CLK

Clock

Input-to-output
(in2out)
Combinational
Logic

13
Timing paths
- A path is a route from a Startpoint to an Endpoint
• A startpoint can be:
1. clock pin of a FF,
2. An input port.
• An endpoint can be:
1. Input data pin of a FF
2. An output port.

Remember that STA is exhaustive, therefore:

- Many paths can be going to any one endpoint.
- Many paths can exist for each startpoint to endpoint combination.

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Components of Circuit Timing
• Delay components
FF
• Cells, Interconnects
• Constrained components
• Clocked registers require setup/hold, recovery/removal
constraints.

For circuit to operate without failure it is required that delay components at no point violate
constraints of other components.

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Physical
Verification

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Physical verification
- PVR checks are done on design gds to assure that the design is clean.
- We use a standalone setup to run each PVR check on the GDS and Spice.

Design GDS Design Verilog netlist SC library spice Ruleset files

V2Spi

Design CDL

DRC/LVS/Antenna

Reports .vue files (Hercules, ICV)

.db files (Calibre)
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DRC → Checks for certain layout rules, to ensure design will be manufactured reliably.
LVS → checks functional correctness of the design.

Layout vs Schematic (LVS) compares the design layout with the design schematic/netlist
to tell if the design is functionally equivalent to schematic.
For this, the connections are extracted from layout of the design by using a set of rules to
convert the layout to connections. These connections are, then compared if they match with
the connections of the netlist. If the connections match, the LVS is said to be clean.

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LVS steps

1. Extraction: The tool takes GDSII file containing all the

layers and uses polygon based approach to determine
the components like transistors, diodes, capacitors and
resistors and also connectivity information between
devices presented in the layout by their layers of
construction. All the device layers, terminals of the
devices, size of devices, nets, vias and the locations of
pins are defined and given an unique identification.
2. Reduction: All the defined information is extracted in
the form of netlist.
3. Comparison: The extracted layout netlist is then
compared to the netlist of the same stage using the
LVS rule deck. In this stage the number of instances,
nets and ports are compared. All the mismatches such
as shorts and opens, pin mismatch etc.. are reported.
The tools also checks topology and size mismatch.

http://www.signoffsemi.com/sign-off-checks/ 19
Issues that can be detected by LVS

1. Shorts: Shorts are formed, if two or more wires which should not be
connected together are connected.
2. Opens: Opens are formed, if the wires or components which should
be connected together are left floating or partially connected.
3. Component mismatch: Component mismatch can happen, if
components of different types are used (e.g, LVT cells instead of HVT
cells).
4. Missing components: Component missing can happen, if an
expected component is left out from the layout.
5. Parameter mismatch: All components has it’s own properties, LVS
tool is configured to compare these properties with some tolerance. If
this tolerance is not met, then it will give parameter mismatch.

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On-Chip
Variation

21
On-Chip Variation
• Used to model random variations occurs due to fabrication
process either die-to-die , or within the same die.
• We should model it as it can lead to chip failure, as it can make
path delay faster or slower.
• We will add extra pessimism to model this random variation.
Types of variations
 On-Chip Variation
These OCV variations can affect the wire delays and cell delays in different portions of the chip.

→ The result is that all the cells of the entire chip no longer can be modelled using the fast or slow process corner alone.
→ Some cells will run fast, others slower than expected, depending on the changes in process condition and the impact of
design-dependent effects.
Failure to account for these issues can lead to setup and hold violations in designs that are, nominally at least,
error-free.

As a result, the design’s timing needs to be analyzed in a way that takes into account the potential for timing to
change within a given process or temperature corner.

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Types of Variations
Systematic Variations Random variations
Deterministic in nature, and can be Totally random, and therefore non-
attributed to a particular manufacturing deterministic in nature.
process parameter, then can be
experimentally modelled. Very difficult to gauge and predict.

They also exhibit spatial correlation. [2 They have a cancelling effect owing to
transitiors close to each other exhibit their own random nature.
similar variations]

Example: inter-chip variations.

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Types of Variations
Global Variations Local variations

Handled by different process corners (ss, Handled by:

ff, tt…etc.) OCV
SSTA (ideal approach, non-practical
runtime and memory requirements)
AOCV (used since 16/14nm tech. nodes)
POCV (widely used <10nm)
SOCV

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Type of derates

On-chip variation Advanced OCV Parametric OCV

Instead of applying a
Derate factor depends on certain derate ,it models
Used Fixed derates
path depth and distance delay as a function of a
90nm and above
65nm and below random variable(σ/μ)
16nm and below.

Pessimism decrease
 1. Global OCV [Fixed derates]
In order to model this, we add timing derate in the timing path.
--> The delay values of cells and nets are multiplied by the timing derate
percentage, which adds more pessimism to account for these variations.

For setup check, to increase pessimism:

(Tcomb|max,Tskew|min)
Data is multiplied by setup_data_late derate. (greater than 1)
Launch clock is multiplied by setup_clock_late derate. (greater than 1)
Capture clock is multiplied by setup_clock_early derate. (less than 1)

For hold check, to increase pessimism:

(Tcomb|min,Tskew|max)
Data is multiplied by hold_data_early derate. (less than 1)
Launch clock is multiplied by hold_clock_early derate. (less than 1)
Capture clock is multiplied by hold_clock_late derate. (greater than 1)

http://vlsi-soc.blogspot.com/2017/03/ocv-vs-aocv.html
28
 Clock Reconvergence Pessimism Removal (CRPR)
- For the common clock path, present in both launch and capture clock paths, it is derated twice with two different
values!
- This is extra pessimism due to the fact that same cells cannot have different delays, in the same conditions and same
point of time.
Therefore, extra pessimism is removed.

CRPR Adjustment = 0.4 ns.

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 Issues in OCV:

• Fixed timing derate used for all the cells in the

OCV is over pessimistic.
• Here in OCV as number of stages increases the
pessimism increases.
• In reality, All the cells in a particular path could
not be delayed all or early all. There is a mixed
type of effect always and this causes cancellation
of effect in total.
 The need for AOCV/POCV/SSTA
OCV models systematic variations and random variations, with
a global margin value for all cells in the design.
This can be very pessimistic!

This is why OCV derating is considered very pessimistic, which

leads to long timing closure cycle non-optimal area and power
results.
→ As we shrink technology, a need arise for more efficient
methodology for variation-aware timing analysis.

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 1. Advanced OCV (AOCV)
AOCV models the random and systematic variations across an IC that affect timing by using variable derating factors.
It consider the cell type, location and the logic depth of each path being analyzed.

PrimeTime uses derating tables to specify the AOCV information. It calculates and applies variable derating factors
that consider the location and the depth of each path being analyzed.

Cell Variation is calculated for each individual cell.

Type
Distance As the distance increase, the systematic variations
would increase, we use a higher derate value to
reflect the increased uncertainty in timing analysis.
Path As the path depth increases, in the same distance,
Depth random variations tend to cancel each other,
therefore AOCV derate tends to decrease.

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 1. Advanced OCV (AOCV)
How PT determines the AOCV derate for each cell in a timing path?
1. Cell locations is annotated from .spef file.
2. While performing reg2reg timing analysis, bounding box containing sequential cells and all clock and data cells is
calculated.
3. As the depth increase within same unit distance, AOCv derate decrease as path depth increases due to cancelling of random
variations.
4. If distance increases, AOCV derates increases due to increase in systematic variations.

33
 Variation according to type
• When derate_type is early:
The table entries are expected to increase with depth and decrease with distance.
object_type: design
rf_type : rise
delay_type : net
derate_type: early
object_spec:
depth :0123456789
distance : 2500000 1973000
table: 0.8248 0.8248 0.8666 0.8849 0.8958 0.9032 0.9086 0.9128 0.9162 0.9189 \
0.8256 0.8256 0.8677 0.8863 0.8974 0.9050 0.9105 0.9149 0.9183 0.9212

•When derate_type is late:

The table entries are expected to decrease with depth and increase with distance.

object_type: design
rf_type : rise
delay_type : net
derate_type: late
object_spec:
depth :0123456789
distance : 2500000 1973000
table: 1.1842 1.1842 1.1398 1.1203 1.1088 1.1010 1.0952 1.0908 1.0872 1.0843 \
1.1832 1.1832 1.1383 1.1184 1.1065 1.0985 1.0925 1.0879 1.0842 1.0811
Parametric On-Chip Variation
 In POCV, Instead of applying a specific derating factor to a cell, it models
delay as a function of a random variable which is specific to that instance.
 POCV it is assumed that the normal delay value of a cell follows the
normal distribution curve.
delay = nominal delay + delay variation *N
A. Delay variation (σ) using POCV Side File
 It is an external file contains the coefficient for delay variation
 It is usually obtained using HSPICE simulations
 It applies a single coefficient value for each library cell
 The coefficient C is the value of the variation at 1 σ , is independent of input
transition and output load
The Delay variation (σ) = C * Nominal delay (µ)
Delay of a cell = Nominal delay (µ) ± (C * Nominal delay) * N
 Parameteric On-Chip Variation

# of cells
μ = mean value
= nominal delay

corner value
Standard
deviation

µ σ µ+3σ cell delay

The Further from the mean to the left tor right the more changes to this particular cell is expected
B. Delay variation (σ) using LVF [most commonly used]
 LVF stands for library Variation Format
 The information of POCV variation is directly provided into the library itself in
LVF format.
• The cell delay variation is modeled as a function of input transition and output
load per timing arc
• Accuracy increased a lot for nodes <16nm
Delay of a cell = Nominal delay (µ) ± σ * N

ocv_sigma_cell_rise ("delay_template_7x7") {
sigma_type : "late";
index_1("0.0088, 0.0264, 0.0608, 0.1296, 0.2672, 0.5424, 1.0936");
index_2("0.001, 0.0024, 0.0052, 0.0108, 0.0221, 0.0445, 0.0895");
values("0.000476, 0.000677, 0.001075, 0.001870, 0.003438, 0.006626, 0.012922", \
"0.000651, 0.000901, 0.001303, 0.002081, 0.003678, 0.006818, 0.013144", \
"0.000840, 0.001166, 0.001714, 0.002558, 0.004112, 0.007249, 0.013529", \
"0.001115, 0.001520, 0.002193, 0.003317, 0.005087, 0.008153, 0.014445", \
"0.001521, 0.002033, 0.002883, 0.004242, 0.006522, 0.010072, 0.016258", \
"0.002155, 0.002793, 0.003853, 0.005563, 0.008424, 0.012955, 0.020171", \
"0.003204, 0.003977, 0.005321, 0.007515, 0.010960, 0.016582, 0.025786");
}
POCV delay calculation:
 Sensitivity (σ) = Mean * Coeff.
 Corner = Mean ± N σ
 Mean (Path) = µ1 + µ2 + µ3 +….
 Sigma (path) = sqrt (σ1^2 + σ2^2 + σ3^2+….)
 Total delay (path) = Mean (path) ± Sigma (path) * N

Cell 1 Cell2

Nominal delay 60ps Nominal delay 80ps

Sigma = 0.05*60= 3ps Sigma = 0.05*80= 4ps

Path arrival: 60 + 80 = 140ps

Path arrival sigma: = 5ps
POCV timing report
Report_timing –variation
POCV Guardband

 Guard-banding allows you to model non-process related effects

(Voltage ,Temperature) in an POCV flow.
 It applies to both nominal delay & sigma

𝑀𝑒𝑎𝑛 = 𝑑𝑒𝑙𝑎𝑦_𝑛𝑜𝑚𝑖𝑛𝑎𝑙 ∗ (𝑃𝑂𝐶𝑉 𝑔𝑢𝑎𝑟𝑑𝑏𝑎𝑛𝑑 ∗ 𝑃𝑂𝐶𝑉 𝑑𝑖𝑠𝑡𝑎𝑛𝑐𝑒 𝑑𝑒𝑟𝑎𝑡𝑒 + 𝐼𝑛𝑐r. 𝑑𝑒𝑟𝑎𝑡𝑒)

𝑆𝑖𝑔𝑚𝑎 = 𝑑𝑒𝑙𝑎𝑦_𝑛𝑜𝑚𝑖𝑛𝑎𝑙 ∗ (𝑃𝑂𝐶𝑉 𝑔𝑢𝑎𝑟𝑑𝑏𝑎𝑛𝑑 ∗ 𝑃𝑂𝐶𝑉 𝑐𝑜𝑒𝑓𝑓 ∗ 𝑃𝑂𝐶𝑉 𝑐𝑜𝑒𝑓 𝑠𝑐𝑎𝑙𝑒 𝑓𝑎𝑐𝑡𝑜𝑟)
Liberty Variation Format (LVF)
• The cell delay variation is modeled as a function of input transition and output load per timing arc
 Liberty syntax, variation in time units
 POCV table indexes are recommended (not required) to be the same as NLDM 2-D table lookup
• The distance-based derating can be applied using side file

ocv_sigma_cell_rise ("delay_template_7x7") {
sigma_type : "late";
index_1("0.0088, 0.0264, 0.0608, 0.1296, 0.2672, 0.5424, 1.0936");
index_2("0.001, 0.0024, 0.0052, 0.0108, 0.0221, 0.0445, 0.0895");
values("0.000476, 0.000677, 0.001075, 0.001870, 0.003438, 0.006626, 0.012922", \
"0.000651, 0.000901, 0.001303, 0.002081, 0.003678, 0.006818, 0.013144", \
"0.000840, 0.001166, 0.001714, 0.002558, 0.004112, 0.007249, 0.013529", \
"0.001115, 0.001520, 0.002193, 0.003317, 0.005087, 0.008153, 0.014445", \
"0.001521, 0.002033, 0.002883, 0.004242, 0.006522, 0.010072, 0.016258", \
"0.002155, 0.002793, 0.003853, 0.005563, 0.008424, 0.012955, 0.020171", \
"0.003204, 0.003977, 0.005321, 0.007515, 0.010960, 0.016582, 0.025786");
}
 PrimeTime Moment-Based LVF
• At 7nm technology node and ultra low
voltage ( < 0.45V), strong non-Gaussian
timing variation due to near Vth voltages
 Large skewness, long tails
• POCV extended with 3 statistical
moments
 Mean shift, standard deviation, skewness
• Corner values are computed by
integrating the non-Gaussian
distributions
 Mean+/-3*Sensit can no longer be used for corner
value computation
Transition/Constraints LVF