14 August 2023 1445 ‫ محرم‬28

ً ‫َو َما أُوتِيت ُ ْم مِ نَ ْالع ِْل ِم إِ اَّل قَل‬

‫ِيل‬
Dr. Hesham Omran
Ain Shams University – Master Micro LLC

Analog IC Design – Cadence and Master Micro Tools

Lab 05
Simple vs Wide Swing (Low Compliance) Cascode Current Mirror

Intended Learning Objectives

In this lab you will:
• Explore current mirror sizing trade-offs using Sizing Assistant (SA).
• Bias a cascode device using a series resistance.
• Design and simulate simple and wide swing (low-voltage) current mirrors.
• Compare simple and wide swing current mirrors.
• Investigate the effect of mismatch on a wide swing current mirror.

NOTE: To get access to the Sizing Assistant (SA) please register at https://adt.master-micro.com/ and
create a support ticket from your dashboard. Verified instructors may also request access to an editable
MS Word version of the labs and the model answers.

NOTE: The values and charts used in the lab document assume the provided 180 nm educational device
models and 1.8 V supply. Other models/technologies can be used by applying reasonable adjustments to
the lab values.

Part 1: Exploring Sizing Tradeoffs Using SA

1) We want to design a simple current mirror with the following specs.

Parameter

Current direction (source/sink) Sink

Input Current 10𝜇𝐴

Output Current 20𝜇𝐴

% Change in Current for 𝚫𝑽𝒐𝒖𝒕 = 𝟏𝑽 < 10%

Percent mismatch: 𝝈(𝑰𝒐𝒖𝒕 )/𝑰𝒐𝒖𝒕 ≤ 2%

Compliance voltage ≤ 150𝑚𝑉

Area Minimize

2) Sinking current means which device type? NMOS or PMOS?

 3) The % Change in current translates to a spec on the 𝜆 = 1/𝑉𝐴 of the device. How much is the
required 𝜆?
4) The current mirror design trade-offs are summarized in the table below.

Parameter Higher gm/ID (lower 𝑽∗) Lower gm/ID (higher 𝑽∗)

Area

Dependence on 𝑽𝑫𝑺 (output resistance,

𝝀 = 𝟏/𝑽𝑨)
Random mismatch

Systematic mismatch

Compliance voltage (headroom)

5) Examine these trade-offs using SA. Use SA to plot the sizing at a constant 𝝈(𝑰𝒐𝒖𝒕 )/𝐼𝑜𝑢𝑡 .

𝑨
√𝟏 + 𝟏 × 𝑽𝑻 × 𝒎𝒈𝒎
𝝈(𝑰𝒐𝒖𝒕 ) 𝒎 √𝑊𝐿
= × 𝟏𝟎𝟎
𝑰𝒐𝒖𝒕 𝒎𝐼𝐷
1
Where 𝑚 is the mirroring ratio, 𝑨𝑽𝑻 = 𝟑. 𝟓𝒎𝑽 ⋅ 𝝁𝒎 is Pelgrom’s coefficient, and the √1 + factor
𝑚
is due to taking the difference between two random variables (𝑉𝑇𝐻 of the two current mirror
transistors).

➔ ADT Hint: If the LUT contains mismatch data, we can directly use the parameter idmis in SA to
get the standard deviation of the current random variations ‘idmis_% = sqrt(1.5)*idmis/ID*100’.
The mismatch data can be added to any LUT using ADT by using an appropriate Monte Carlo
mismatch model file.

Page 2 of 7
1) Can we do the previous design trade-offs exploration sweeps using a standard SPICE simulator, i.e.,
sweep Vstar at a constant 𝝈(𝑰𝒐𝒖𝒕 )/𝐼𝑜𝑢𝑡 ? Why?
2) The above results mean that the highest 𝑉 ∗ is desirable from the perspective of mismatch, area, and
𝜆. Thus, 𝑉 ∗ will be limited by the required compliance voltage.
NOTE: We assume that the compliance voltage ≈ 𝑉𝐷𝑆𝑠𝑎𝑡 ≈ 𝑉 ∗.
3) Report the above plot with a cursor added at the required 𝑉 ∗. Does this point satisfy the mismatch
and 𝜆 constraints?
4) If the 𝜆 constraint is not satisfied at 𝝈(𝑰𝒐𝒖𝒕 )/𝐼𝑜𝑢𝑡 = 2%, i.e., it needs a longer 𝐿, we can use SA to
find the required design point as shown below.

Page 3 of 7
 5) Report the device sizing and 𝝈(𝑰𝒐𝒖𝒕 )/𝐼𝑜𝑢𝑡 at the selected design point.

Part 2: Current Mirror Simulation

1) Create a new schematic. Construct the circuit shown below.

2) The current mirror takes input current IB and generates output current = 2*IB (note the multiplier
setting in the output branch).
3) Instead of using a wide-swing bias transistor (a magic battery) to generate VB, we use a resistor RB in
series with the input branch.
4) Unless otherwise stated, set VOUT = VDD/2 and VMIS1 = VMIS2 = 0.

1. Design and OP (Operating Point) Analysis

1) Assume we want to set a 50𝑚𝑉 saturation margin for M2 and M3, i.e., 𝑉𝐷𝑆2 ≈ 𝑉𝐷𝑆3 ≈ 𝑉 ∗ + 50𝑚𝑉.
Ignore the body effect and calculate a rough value for RB.

Page 4 of 7
 𝑉𝐺𝑆4 +𝑉𝐷𝑆2 −𝑉𝐺𝑆2 𝑉𝐷𝑆2
Hint: 𝑅𝐵 = ≈
𝐼𝐵 𝐼𝐵
Hint: The purpose of doing rough analysis is not to reach a final design point, but to calculate a value
that makes sense and can be used to determine a reasonable range for a simulator sweep.
2) Perform DC sweep (not parametric sweep) for RB. Choose a reasonable sweep range given the rough
value computed in the previous step. Report 𝑉𝐷𝑆3 vs 𝑅𝐵 . Choose 𝑅𝐵 to satisfy the 50𝑚𝑉 saturation
margin requirement. Is the selected 𝑅𝐵 value larger or smaller than the rough analytical value?
Why?
➔ Cadence Hint: The DC sweep is performed in a simulator inner loop, so it is very fast and takes
small disk space. The parametric sweep is an outer loop repetitive calling of the simulator, so it is
much slower and takes much larger disk space.
3) Simulate the OP point. Report a snapshot clearly showing the following parameters.
➔ Cadence Hint: You can use Info Balloons (View -> Info Balloons) to show the device parameters.
Use (View -> Annotations -> Setup) to customize the Info Balloons.
➔ Cadence Hint: You can add expressions to the Info Balloons, e.g., Vstar = 2/(gm/ID).

ID
VGS
VDS
VTH
VDSAT
Vstar = 2/(gm/ID)
gm/ID
GM
GDS
GMB
Region

4) Do all transistors operate in saturation?

2. DC Sweep (𝐼𝑜𝑢𝑡 vs VOUT)

1) Perform DC sweep (not parametric sweep) using VOUT = 0:10m:VDD. Report 𝐼𝑜𝑢𝑡 vs VOUT for the
two CMs overlaid in the same plot.
o Comment on the difference between the two circuits.
o From the plot, find an estimate for the compliance voltage of each current mirror.
o 𝐼𝑜𝑢𝑡 of the simple CM is exactly equal to IB*2 at a specific value of VOUT. Why?
2) For the simple current mirror, calculate the percent change in 𝐼𝑜𝑢𝑡 when VOUT changes from 0.5V to
1.5V (i.e., 1V change). Compare the result to the value expected from Part 1.
3) Report the percent of error in 𝐼𝑜𝑢𝑡 vs VOUT (ideal 𝐼𝑜𝑢𝑡 should be IB*2) for the two CMs in the current
mirror operating region (VOUT ≈ 𝑉 ∗to VDD) overlaid in the same plot.
Hint: Calculate percent of error as (simulated – ideal)/ideal * 100
o Comment on the difference between the two circuits.
4) Report Rout vs VOUT (take the inverse of the derivative of 𝐼𝑜𝑢𝑡 plot) for the two CMs in the current
mirror operating region (VOUT ≈ 𝑉 ∗to VDD) overlaid in the same plot. Use log scale on the y-axis.
Add a cursor at VOUT = VDD/2.
o Comment on the difference between the two circuits.
o Does Rout change with VOUT? Why?
➔ Cadence Hint: Rout can also be simulated using AC analysis. The value we used here should be
similar to the AC analysis result at low frequencies.

Page 5 of 7
 5) Analytically calculate Rout of both circuits at VOUT = VDD/2. Compare with simulation results in a
table.

3. Mismatch
NOTE: Practically, we study the mismatch using Monte Carlo simulation as will be shown in the next
section. However, in this section, we will manually add mismatch in the circuit.
1) Perform DC sweep for VMIS1 from 0 to sqrt(1.5)*3.5m/sqrt(W*L*1e12) and set VMIS2 = 0. This
models the standard deviation of the mismatch in 𝑉𝑇𝐻 for the current mirror devices. Find the
percent change in 𝐼𝑜𝑢𝑡 .
2) Analytically calculate the percent change in 𝐼𝑜𝑢𝑡 and compare it to the simulation result.
Hint: The voltage change at the gate can be considered as a small signal. Thus, the change in the
current can be calculated using the 𝐺𝑚 of the circuit. In this case, the circuit can be considered as a
cascode amplifier.
3) Set VMIS1 = 0 and perform DC sweep for VMIS2 from 0 to sqrt(1.5)*3.5m/sqrt(W*L*1e12). This
models the standard deviation of the mismatch in 𝑉𝑇𝐻 for the cascode devices. Find the percent
change in 𝐼𝑜𝑢𝑡 .
4) Analytically calculate the percent change in 𝐼𝑜𝑢𝑡 and compare it to the simulation result.
Hint: The voltage change at the gate can be considered as a small signal. Thus, the change in the
current can be calculated using the 𝐺𝑚 of the circuit. In this case, the circuit can be considered as a
degenerated common source amplifier.
5) Which mismatch contribution is more pronounced? Why?
6) Which design decision is better: setting the same W and L for the mirror and cascode devices? Or
using larger W and L for the current mirror devices? Why?

4. Monte Carlo (MC) Simulation

NOTE: Use the model file ee214b_mis.sp which includes the mismatch models of the devices.
NOTE: Using the multiplier parameter can give wrong mismatch results because the errors from the
parallel devices will be correlated. Thus, set m = 1, and name the device as an array of two devices
‘Mx<1:0>’ as shown in the schematic below.
NOTE: In this section we will set both VMIS1 and VMIS2 to zero.

Page 6 of 7
 1) Change the model name of the mirror devices to be ‘nch_mis’ to include their mismatch effect. Keep
the model of the cascode devices as ‘nch’.
Hint: Open the model file and see how the mismatch is modeled in the nch_mis subcircuit.
2) Run Monte Carlo (MC) simulation for mismatch only as shown below.

3) Report a plot for the histogram of 𝐼𝑜𝑢𝑡 .

Hint: You can measure the OP current of the voltage source connected to the output node.
Ex: abs(pv("V1" "i" ?result "dcOpInfo"))
4) Calculate the standard deviation percentage 𝝈(𝑰𝒐𝒖𝒕 )/𝐼𝑜𝑢𝑡 .
5) Compare the MC simulation result to the expected analytical result.
6) Set the mirror devices model to ‘nch’ and the cascode devices model to to ‘nch_mis’. Repeat all the
above steps.

Lab Summary
In Part 1 you learned:
• How to use SA to examine current mirror design trade-offs.
• How to design a simple current mirror.

In Part 2 you learned:

• How to design a wide swing (low-voltage) current mirror.
• How the behavior of a simple current mirror changes with the output voltage.
• How the behavior of a wide swing current mirror changes with the output voltage.
• The effect of mismatch on a wide swing current mirror.
• How to perform Monte Carlo simulations for a current mirror circuit.

Acknowledgements
Thanks to all who contributed to these labs. Special thanks to Dr. Sameh A. Ibrahim for reviewing and editing
the labs. If you find any errors or have suggestions concerning these labs, please contact
[email protected].

Page 7 of 7