a Software Programmable

Gain Amplifier
AD526
FEATURES PIN CONFIGURATION
Digitally Programmable Binary Gains from 1 to 16
Two-Chip Cascade Mode Achieves Binary Gain from
1 to 256 DIG GND 1 16 A1
Gain Error: NULL 2 15 A0
0.01% Max, Gain = 1, 2, 4 (C Grade) VIN 3 14 CS
0.02% Max, Gain = 8, 16 (C Grade) NULL 4 AD526 CLK
13
0.5 ppm/ⴗC Drift Over Temperature TOP VIEW
ANALOG GND 2 5 (Not to Scale) 12 A2
Fast Settling Time
ANALOG GND 1 6 11 B
10 V Signal Change:
–VS 7 10 +VS
0.01% in 4.5 ␮s (Gain = 16)
VOUT SENSE 8 9 VOUT FORCE
Gain Change:
0.01% in 5.6 ␮s (Gain = 16)
Low Nonlinearity: ⴞ0.005% FSR Max (J Grade)
Excellent DC Accuracy:
Offset Voltage: 0.5 mV Max (C Grade)
Offset Voltage Drift: 3 ␮V/ⴗC (C Grade)
TTL-Compatible Digital Inputs

PRODUCT DESCRIPTION
The AD526 is a single-ended, monolithic software program- APPLICATION HIGHLIGHTS
mable gain amplifier (SPGA) that provides gains of 1, 2, 4, 8 1. Dynamic Range Extension for ADC Systems: A single
and 16. It is complete, including amplifier, resistor network AD526 in conjunction with a 12-bit ADC can provide
and TTL-compatible latched inputs, and requires no external 96 dB of dynamic range for ADC systems.
components. 2. Gain Ranging Preamps: The AD526 offers complete digital
Low gain error and low nonlinearity make the AD526 ideal for gain control with precise gains in binary steps from 1 to 16.
precision instrumentation applications requiring programmable Additional gains of 32, 64, 128 and 256 are possible by cas-
gain. The small signal bandwidth is 350 kHz at a gain of 16. In cading two AD526s.
addition, the AD526 provides excellent dc precision. The FET-
input stage results in a low bias current of 50 pA. A guaranteed ORDERING GUIDE
maximum input offset voltage of 0.5 mV max (C grade) and low
gain error (0.01%, G = 1, 2, 4, C grade) are accomplished using Temperature Package Package
Analog Devices’ laser trimming technology. Model Range Descriptions Options
To provide flexibility to the system designer, the AD526 can be AD526JN Commercial 16-Lead Plastic DIP N-16
operated in either latched or transparent mode. The force/sense AD526AD Industrial 16-Lead Cerdip D-16
configuration preserves accuracy when the output is connected AD526BD Industrial 16-Lead Cerdip D-16
to remote or low impedance loads. AD526CD Industrial 16-Lead Cerdip D-16
AD526SD Military 16-Lead Cerdip D-16
The AD526 is offered in one commercial (0°C to +70°C) grade, AD526SD/883B Military 16-Lead Cerdip D-16
J, and three industrial grades, A, B and C, which are specified 5962-9089401MEA* Military 16-Lead Cerdip D-16
from –40°C to +85°C. The S grade is specified from –55°C to
*Refer to official DESC drawing for tested specifications.
+125°C. The military version is available processed to MIL-
STD 883B, Rev C. The J grade is supplied in a 16-lead plastic
DIP, and the other grades are offered in a 16-lead hermetic
side-brazed ceramic DIP.

REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 1999
AD526–SPECIFICATIONS (@ V = ⴞ15 V, R = 2 k⍀ and T = +25ⴗC unless otherwise noted)
S L A

AD526J AD526A AD526B/S AD526C

Model Min Typ Max Min Typ Max Min Typ Max Min Typ Max Units
GAIN
Gain Range
(Digitally Programmable) 1, 2, 4, 8, 16 1, 2, 4, 8, 16 1, 2, 4, 8, 16 1, 2, 4, 8, 16
Gain Error
Gain = 1 0.05 0.02 0.01 0.01 %
Gain = 2 0.05 0.03 0.02 0.01 %
Gain = 4 0.10 0.03 0.02 0.01 %
Gain = 8 0.15 0.07 0.04 0.02 %
Gain = 16 0.15 0.07 0.04 0.02 %
Gain Error Drift
Over Temperature
G=1 0.5 2.0 0.5 2.0 0.5 2.0 0.5 2.0 ppm/°C
G=2 0.5 2.0 0.5 2.0 0.5 2.0 0.5 2.0 ppm/°C
G=4 0.5 3.0 0.5 3.0 0.5 3.0 0.5 3.0 ppm/°C
G=8 0.5 5.0 0.5 5.0 0.5 5.0 0.5 5.0 ppm/°C
G = 16 1.0 5.0 1.0 5.0 1.0 5.0 1.0 5.0 ppm/°C
Gain Error (TMIN to TMAX)
Gain = 1 0.06 0.03 0.02 0.015 %
Gain = 2 0.06 0.04 0.03 0.015 %
Gain = 4 0.12 0.04 0.03 0.015 %
Gain = 8 0.17 0.08 0.05 0.03 %
Gain = 16 0.17 0.08 0.05 0.03 %
Nonlinearity
Gain = 1 0.005 0.005 0.005 0.0035 % FSR
Gain = 2 0.001 0.001 0.001 0.001 % FSR
Gain = 4 0.001 0.001 0.001 0.001 % FSR
Gain = 8 0.001 0.001 0.001 0.001 % FSR
Gain = 16 0.001 0.001 0.001 0.001 % FSR
Nonlinearity (TMIN to TMAX)
Gain = 1 0.01 0.01 0.01 0.007 % FSR
Gain = 2 0.001 0.001 0.001 0.001 % FSR
Gain = 4 0.001 0.001 0.001 0.001 % FSR
Gain = 8 0.001 0.001 0.001 0.001 % FSR
Gain = 16 0.001 0.001 0.001 0.001 % FSR
VOLTAGE OFFSET, ALL GAINS
Input Offset Voltage 0.4 1.5 0.25 0.7 0.25 0.5 0.25 0.5 mV
Input Offset Voltage Drift Over
Temperature 5 20 3 10 3 10 3 10 µV/°C
Input Offset Voltage
TMIN to TMAX 2.0 1.0 0.8 0.8 mV
Input Offset Voltage vs. Supply
(VS ± 10%) 80 80 84 90 dB
INPUT BIAS CURRENT
Over Input Voltage Range ± 10 V 50 150 50 150 50 150 50 150 pA
ANALOG INPUT
CHARACTERISTICS
Voltage Range
(Linear Operation) ⴞ10 ± 12 ⴞ10 ± 12 ⴞ10 ± 12 ⴞ10 ± 12 V
Capacitance 5 5 5 5 pF
RATED OUTPUT
Voltage ⴞ10 ± 12 ⴞ10 ± 12 ⴞ10 ± 12 ⴞ10 ± 12 V
Current (VOUT = ± 10 V) ± 10 ⴞ5 ± 10 ⴞ5 ± 10 ⴞ5 ± 10 mA
Short-Circuit Current 15 30 15 30 15 30 15 30 mA
DC Output Resistance 0.002 0.002 0.002 0.002 Ω
Load Capacitance
(For Stable Operation) 700 700 700 700 pF

–2– REV. D
 AD526
AD526J AD526A AD526B/S AD526C
Model Min Typ Max Min Typ Max Min Typ Max Min Typ Max Units
NOISE, ALL GAINS
Voltage Noise, RTI
0.1 Hz to 10 Hz 3 3 3 3 µV p-p
Voltage Noise Density, RTI
f = 10 Hz 70 70 70 70 nV√Hz
f = 100 Hz 60 60 60 60 nV√Hz
f = 1 kHz 30 30 30 30 nV√Hz
f = 10 kHz 25 25 25 35 nV√Hz
DYNAMIC RESPONSE
–3 dB Bandwidth (Small Signal)
G=1 4.0 4.0 4.0 4.0 MHz
G=2 2.0 2.0 2.0 2.0 MHz
G=4 1.5 1.5 1.5 1.5 MHz
G=8 0.65 0.65 0.65 0.65 MHz
G = 16 0.35 0.35 0.35 0.35 MHz
Signal Settling Time to 0.01%
(∆VOUT = ± 10 V)
G=1 2.1 4 2.1 4 2.1 4 2.1 4 µs
G=2 2.5 5 2.5 5 2.5 5 2.5 5 µs
G=4 2.7 5 2.7 5 2.7 5 2.7 5 µs
G=8 3.6 7 3.6 7 3.6 7 3.6 7 µs
G = 16 4.1 7 4.1 7 4.1 7 4.1 7 µs
Full Power Bandwidth
G = 1, 2, 4 0.10 0.10 0.10 0.10 MHz
G = 8, 16 0.35 0.35 0.35 0.35 MHz
Slew Rate
G = 1, 2, 4 4 6 4 6 4 6 4 6 V/µs
G = 8, 16 18 24 18 24 18 24 18 24 V/µs
DIGITAL INPUTS
(TMIN to TMAX)
Input Current (VH = 5 V) 60 100 140 60 100 140 60 100 140 60 100 140 µA
Logic “1” 2 6 2 6 2 6 2 6 V
Logic “0” 0 0.8 0 0.8 0 0.8 0 0.8 V
TIMING1
(VL = 0.2 V, VH = 3.7 V)
A0, A1, A2
TC 50 50 50 50 ns
TS 30 30 30 30 ns
TH 30 30 30 30 ns
B
TC 50 50 50 50 ns
TS 40 40 40 40 ns
TH 10 10 10 30 ns
TEMPERATURE RANGE
Specified Performance 0 +70 –40 +85 –40/–55 +85/+125 –40 +85 °C
Storage –65 +125 –65 +150 –65 +150 –65 +150 °C
POWER SUPPLY
Operating Range ⴞ4.5 ⴞ16.5 ⴞ4.5 ⴞ16.5 ⴞ4.5 ⴞ16.5 ⴞ4.5 ⴞ16.5 V
Positive Supply Current 10 14 10 14 10 14 10 14 mA
Negative Supply Current 10 13 10 13 10 13 10 13 mA
PACKAGE OPTIONS
Plastic (N-16) AD526JN
Ceramic DIP (D-16) AD526AD AD526BD AD526SD AD526CD
AD526SD/883B
NOTES
1
Refer to Figure 25 for definitions. FSR = Full Scale Range = 20 V. RTI = Referred to Input.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all production units at final electrical test. All min and max specifications are guaranteed, although only those shown in
boldface are tested on all production units.

REV. D –3–
AD526–Typical Performance Characteristics
20 30 20
OUTPUT VOLTAGE SWING – 6V

OUTPUT VOLTAGE SWING – 6V

INPUT BIAS CURRENT – pA

15 15
+258C
RL = 2kV 20
@ VS = 615V VIN = 0

10 10

10
5 5

0 0 0
0 5 10 15 20 100 1k 10k 0 5 10 15 20
SUPPLY VOLTAGE – 6V LOAD RESISTANCE – V SUPPLY VOLTAGE – 6V

Figure 1. Output Voltage Swing vs. Figure 2. Output Voltage Swing vs. Figure 3. Input Bias Current vs.
Supply Voltage, G = 16 Load Resistance Supply Voltage

100nA 75 20
16
10
8
VS = 615V
INPUT BIAS CURRENT – pA

10nA
INPUT BIAS CURRENT

50 4
1nA

GAIN
2
1
100pA
25 1

10pA

1pA 0
–60 –20 20 60 100 140 –10 –5 0 5 10 10 100 1k 10k 100k 1M 10M
TEMPERATURE – 8C INPUT VOLTAGE – V FREQUENCY – Hz

Figure 4. Input Bias Current vs. Figure 5. Input Bias Current vs. Input Figure 6. Gain vs. Frequency
Temperature Voltage

25 100 1.0002
615V WITH 1V p-p
SINE WAVE
FULL POWER RESPONSE – V p-p

POWER SUPPLY REJECTION – dB

20 GAIN = 8, 16 80
1.0001
NORMALIZED GAIN

+SUPPLY
15 60
GAIN = 1, 2, 4
1.0000

10 40

–SUPPLY
0.9999
5 20

0 10 0.9998
1k 10k 100k 1M 10M 1 10 100 1k 10k 100k 1M –60 –20 20 60 100 140
FREQUENCY – Hz FREQUENCY – Hz TEMPERATURE – 8C

Figure 7. Large Signal Frequency Figure 8. PSRR vs. Frequency Figure 9. Normalized Gain vs.
Response Temperature, Gain = 1

–4– REV. D
 AD526
1000 0.006
INPUT NOISE VOLTAGE – nV/ Hz

0.004

NONLINEARITY – %FSR
0.002

100
0.000

–0.002

10 –0.004
10 100 1k 10k 100k –60 –20 20 60 100 140
FREQUENCY – Hz TEMPERATURE – 8C

Figure 10. Noise Spectral Density Figure 11. Nonlinearity vs. Figure 12. Wideband Output Noise,
Temperature, Gain = 1 G = 16 (Amplified by 10)

Figure 13. Large Signal Pulse Figure 14. Small Signal Pulse Figure 15. Large Signal Pulse
Response and Settling Time,* Response, G = 1 Response and Settling Time,*
G=1 G=2

Figure 16. Small Signal Pulse Figure 17. Large Signal Pulse Figure 18. Small Signal Pulse
Response, G = 2 Response and Settling Time,* Response, G = 4
G=4

*For Settling Time Traces, 0.01% = 1/2 Vertical Division

REV. D –5–
AD526

Figure 19. Large Signal Pulse Figure 20. Small Signal Pulse Figure 21. Large Signal Pulse
Response and Settling Time,* G = 8 Response, G = 8 Response and Settling Time,* G = 16

–60 10
TOTAL HARMONIC DISTORTION – dB

PHASE DISTORTION – Dedrees

–70 5

–80 0

–90 –5

–100 –10
10 100 1k 10k 100k 10 100 1k 10k 100k
FREQUENCY – Hz FREQUENCY – Hz

Figure 22. Small Signal Pulse Figure 23. Total Harmonic Distortion Figure 24. Phase Distortion vs.
Response, Gain = 16 vs. Frequency Gain = 16 Frequency, Gain = 16

100
OUTPUT IMPEDANCE – V

G = 2, 8
G = 4, 16

G=1
10

1
10k 100k 1M 10M
FREQUENCY – Hz

Figure 25. Output Impedance vs. Figure 26. Gain Change Settling Figure 27. Gain Change Settling
Frequency Time,** Gain Change: 1 to 2 Time,** Gain Change 1 to 4

*For Settling Time Traces, 0.01% = 1/2 Vertical Division

**Scope Traces are: Top: Output Transition; Middle: Output Settling; Bottom: Digital Input.

–6– REV. D
 AD526

Figure 28. Gain Change Settling Figure 29. Gain Change Settling
Time,* Gain Change 1 to 8 Time,* Gain Change 1 to 16

+15V –15V
10mF 10mF +15V –15V
+ + 10mF 10mF
+ + TEKTRONIX
7000 SERIES
SCOPE
7A13
PREAMP
AD526 5MHz BW
G = 16
OP37

900V
G = 10

100V Vo = 160 3 e p-p

+ 10mF

+5V
SHIELD
NOTE: COAX CABLE 1 FT. OR LESS

Figure 30. Wideband Noise Test Circuit

+15V –15V
10mF 10mF
+ +
DATA
DYNAMICS
5109 +15V –15V
(OR EQUIVALENT 10mF 10mF
FLAT-TOP PULSE 5kV + +
GENERATOR) AD526
TEKTRONIX
1pF 7000 SERIES
VERROR SCOPE
2kV +
POT. VERROR 3 5 7A13
AD711 – PREAMP
5kV 5MHz BW
– AD3554
1pF
+
G RIN 5kV
5.6kV
1 5.6kV IN6263
2 2.8kV
4 1.4kV RIN 10mF 10mF TSET = TMEAS2 – TX2
– 5pF + +
8 715V 5kV IN6263 1.25kV
16 348V AD3554 G TX
50V –15V +15V
+ 1 1.2ms
2 1.2ms
4 1.2ms
10mF 10mF 8 1.4ms
+ + 16 1.8ms

–15V +15V

Figure 31. Settling Time Test Circuit

*Scope Traces are:

Top: Output Transition
Middle: Output Settling
Bottom: Digital Input

REV. D –7–
AD526
THEORY OF OPERATION TRANSPARENT MODE OF OPERATION
The AD526 is a complete software programmable gain amplifier In the transparent mode of operation, the AD526 will respond
(SPGA) implemented monolithically with a drift-trimmed directly to level changes at the gain code inputs (A0, A1, A2) if
BiFET amplifier, a laser wafer trimmed resistor network, JFET B is tied high and both CS and CLK are allowed to float low.
analog switches and TTL compatible gain code latches. After the gain codes are changed, the AD526’s output voltage
A particular gain is selected by applying the appropriate gain typically requires 5.5 µs to settle to within 0.01% of the final
code (see Table I) to the control logic. The control logic turns value. Figures 26 to 29 show the performance of the AD526 for
on the JFET switch that connects the correct tap on the gain positive gain code changes.
network to the inverting input of the amplifier; all unselected
JFET gain switches are off (open). The “on” resistance of the A2
A1
gain switches causes negligible gain error since only the
A0
amplifier’s input bias current, which is less than 150 pA, actu- +VS
ally flows through these switches.
+5V 0.1mF
The AD526 is capable of storing the gain code, (latched mode),
B, A0, A1, A2, under the direction of control inputs CLK and OUT
16 15 14 13 12 11 10 9 FORCE
CS. Alternatively, the AD526 can respond directly to gain code
A1 A0 CS CLK A2 B
changes if the control inputs are tied low (transparent mode). LOGIC AND LATCHES
For gains of 8 and 16, a fraction of the frequency compensation 16 8 4 2 1
capacitance (C1 in Figure 32) is automatically switched out of VOUT
the circuit. This increases the amplifier’s bandwidth and im- GAIN NETWORK

proves its signal settling time and slew rate. –

AD526 +

1 2 3 4 5 6 7 8 OUT
AMPLIFIER
SENSE
+VS
C1 VIN 0.1mF

–VS
C2
VIN OUT
FORCE Figure 33. Transparent Mode

N1 N2 LATCHED MODE OF OPERATION

–VS OUT The latched mode of operation is shown in Figure 34. When
SENSE either CS or CLK go to a Logic “1,” the gain code (A0, A1, A2,
B) signals are latched into the registers and held until both CS
A0
C
and CLK return to “0.” Unused CS or CLK inputs should be tied
O 14kV to ground . The CS and CLK inputs are functionally and electri-
A1 N
L T G=8
cally equivalent.
A R
A2 T O 3.4kV
C L RESISTOR TIMING SIGNAL
H NETWORK
B G=2 A2
E L
S O 1kV A1
CLK G
I A0
C G = 16 +VS
CS 1.7kV
+5V 0.1mF
G=4
DIGITAL OUT
GND 1kV 1.7kV
ANALOG ANALOG 16 15 14 13 12 11 10 9 FORCE
GND2 GND1
A1 A0 CS CLK A2 B
LOGIC AND LATCHES
Figure 32. Simplified Schematic of the AD526
16 8 4 2 1
VOUT
GAIN NETWORK
–
AD526 +

1 2 3 4 5 6 7 8 OUT
SENSE

VIN 0.1mF

–VS

Figure 34. Latched Mode

–8– REV. D
 AD526
TIMING AND CONTROL DIGITAL FEEDTHROUGH
With either CS or CLK or both held high, the AD526 gain state
Table I. Logic Input Truth Table will remain constant regardless of the transitions at the A0, A1,
A2 or B inputs. However, high speed logic transitions will un-
Gain Code Control Condition avoidably feed through to the analog circuitry within the AD526
A2 A1 A0 B CLK (CS = 0) Gain Condition causing spikes to occur at the signal output.
X X X X 1 Previous State Latched This feedthrough effect can be completely eliminated by operat-
0 0 0 1 0 1 Transparent ing the AD526 in the transparent mode and latching the gain
0 0 1 1 0 2 Transparent code in an external bank of latches (Figure 36).
0 1 0 1 0 4 Transparent
To operate the AD526 using serial inputs, the configuration
0 1 1 1 0 8 Transparent
shown in Figure 36 can be used with the 74LS174 replaced by a
1 X X 1 0 16 Transparent
serial-in/parallel-out latch, such as the 54LS594.
X X X 0 0 1 Transparent
X X X 0 1 1 Latched A1 A0 A2 B +5V
0 0 0 1 1 1 Latched
0 0 1 1 1 2 Latched 1mF
0 1 0 1 1 4 Latched TIMING
SIGNAL
74LS174
0 1 1 1 1 8 Latched
1 X X 1 1 16 Latched +VS
NOTE: X = Don’t Care.
0.1mF
The specifications on page 3, in combination with Figure 35,
give the timing requirements for loading new gain codes. OUT
16 15 14 13 12 11 10 9 FORCE

A1 A0 CS CLK A2 B
GAIN CODE LOGIC AND LATCHES
VALID DATA
INPUTS
16 8 4 2 1
TC VOUT
GAIN NETWORK
CLK OR CS
–
TS TH AD526 +
TC = MINIMUM CLOCK CYCLE NOTE: THRESHOLD LEVEL FOR
1 2 3 4 5 6 7 8 OUT
TS = DATA SETUP TIME GAIN CODE, CS, AND CLK IS 1.4V.
SENSE
TH = DATA HOLD TIME
VIN 0.1mF
Figure 35. AD526 Timing
–VS

Figure 36. Using an External Latch to Minimize Digital

Feedthrough

REV. D –9–
AD526
GROUNDING AND BYPASSING Utilizing the force and sense outputs of the AD526, as shown in
Proper signal and grounding techniques must be applied in Figure 38, avoids signal drops along etch runs to low impedance
board layout so that specified performance levels of precision loads.
data acquisition components, such as the AD526, are not
Table II. Logic Table for Figure 38
degraded.
As is shown in Figure 37, logic and signal grounds should be VOUT/VIN A2 A1 A0
separate. By connecting the signal source ground locally to the
1 0 0 0
AD526 analog ground Pins 5 and 6, gain accuracy of the
2 0 0 1
AD526 is maintained. This ground connection should not be
4 0 1 0
corrupted by currents associated with other elements within the
8 0 1 1
system.
16 1 0 0
32 1 0 1
+15V –15V
64 1 1 0
0.1mF 128 1 1 1
0.1mF

AD574
VIN 12-BIT
0.1mF 0.1mF A/D
CONVERTER
ANALOG ANALOG +VS –VS
GROUND 1 GROUND 2
VOUT
FORCE
AMP
AD526
VOUT
GAIN SENSE
NETWORK
DIGITAL 1mF
GROUND
LATCHES AND LOGIC
+5V

Figure 37. Grounding and Bypassing

CLK
A2
A1
A0
+VS +VS

+5V 0.1mF +5V 0.1mF

OUT OUT
16 15 14 13 12 11 10 9 FORCE 16 15 14 13 12 11 10 9 FORCE

A1 A0 CS CLK A2 B A1 A0 CS CLK A2 B
LOGIC AND LATCHES LOGIC AND LATCHES

16 8 4 2 1 16 8 4 2 1
VOUT
GAIN NETWORK GAIN NETWORK
– –
AD526 + AD526 +

1 2 3 4 5 6 7 8 OUT 1 2 3 4 5 6 7 8 OUT
SENSE SENSE

VIN 0.1mF
0.1mF
–VS
–VS

Figure 38. Cascaded Operation

–10– REV. D
 AD526
OFFSET NULLING CASCADED OPERATION
Input voltage offset nulling of the AD526 is best accomplished A cascade of two AD526s can be used to achieve binarily
at a gain of 16, since the referred-to-input (RTI) offset is ampli- weighted gains from 1 to 256. If gains from 1 to 128 are needed,
fied the most at this gain and therefore is most easily trimmed. no additional components are required. This is accomplished by
The resulting trimmed value of RTI voltage offset typically using the B pin as shown in Figure 38. When the B pin is low,
varies less than 3 µV across all gain ranges. the AD526 is held in a unity gain stage independent of the other
Note that the low input current of the AD526 minimizes RTI gain code values.
voltage offsets due to source resistance.
OFFSET NULLING WITH A D/A CONVERTER
+VS Figure 41 shows the AD526 with offset nulling accomplished
with an 8-bit D/A converter (AD7524) circuit instead of the
0.1mF potentiometer shown in Figure 39. The calibration procedure is
the same as before except that instead of adjusting the potenti-
OUT
16 15 14 13 12 11 10 9 FORCE ometer, the D/A converter corrects for the offset error. This
A1 A0 CS CLK A2 B
calibration circuit has a number of benefits in addition to elimi-
LOGIC AND LATCHES nating the trimpot. The most significant benefit is that calibra-
16 8 4 2 1 tion can be under the control of a microprocessor and therefore
VOUT can be implemented as part of an autocalibration scheme. Sec-
GAIN NETWORK ondly, dip switches or RAM can be used to hold the 8-bit word
– after its value has been determined. In Figure 42 the offset null
AD526 +
sensitivity, at a gain of 16, is 80 µV per LSB of adjustment,
1 2 3 4 5 6 7 8 OUT which guarantees dc accuracy to the 16-bit performance level.
SENSE
VIN
20kV 0.1mF +VS

–VS 0.1mF

Figure 39. Offset Voltage Null Circuit OUT

16 15 14 13 12 11 10 9 FORCE

OUTPUT CURRENT BOOSTER A1 A0 CS CLK A2 B

LOGIC AND LATCHES
The AD526 is rated for a full ± 10 V output voltage swing into
16 8 4 2 1
2 kΩ. In some applications, the need exists to drive more cur- VOUT
rent into heavier loads. As shown in Figure 40, a high current GAIN NETWORK
booster may be connected “inside the loop” of the SPGA to –
provide the required current boost without significantly degrad- AD526 +

ing overall performance. Nonlinearities, offset and gain inaccu- 1 2 3 4 5 6 7 8 OUT

SENSE
racies of the buffer are minimized by the loop gain of the
VIN
AD526 output amplifier. +VS
AD581 OR
0.1mF

AD587 3.3MV
7.5MV –VS
+10V
+VS VREF
ALL BYPASS CAPACITORS ARE 0.1mF
0.1mF +VS
1kV 0.01mF
MSB
10mF
OUT LSB OUT 1
AD7524 –
16 15 14 13 12 11 10 9 FORCE 0.01mF CS AD548
OUT 2
WR +
A1 A0 CS CLK A2 B
LOGIC AND LATCHES 0.01mF

16 8 4 2 1
HOS-100 GND –VS
GAIN NETWORK
0.01mF
Figure 41. Offset Nulling Using a DAC
–
AD526 +

1 2 3 4 5 6 7 8 OUT
SENSE
0.1mF
VIN
RL

–VS

Figure 40. Current Output Boosting

REV. D –11–
AD526
FLOATING-POINT CONVERSION the input falls within, relative to full scale. Once the AD526 has
High resolution converters are used in systems to obtain high settled to the appropriate level, then the second sample/hold
accuracy, improve system resolution or increase dynamic range. amplifier can be put into hold which holds the amplified signal
There are a number of high resolution converters available with while the AD7572 perform its conversion routine. The acquisi-
throughput rates of 66.6 kHz that can be purchased as a single tion time for the AD585 is 3 µs, and the conversion time for the
component solution; however in order to achieve higher through- AD7572 is 5 µs for a total of 8 µs, or 125 kHz. This performance
put rates, alternative conversion techniques must be employed. relies on the fast settling characteristics of the AD526 after the
A floating point A/D converter can improve both throughput flash autoranging (comparator) circuit quantizes the input sig-
rate and dynamic range of a system. nal. A 16-bit register holds the 3-bit output from the flash autor-
In a floating point A/D converter (Figure 42), the output data is anger and the 12-bit output of the AD7572.
presented as a 16-bit word, the lower 12 bits from the A/D The A/D converter in Figure 42 has a dynamic range of 96 dB.
converter form the mantissa and the upper 4 bits from the digi- The dynamic range of a converter is the ratio of the full-scale
tal signal used to set the gain form the exponent. The AD526 input range to the LSB value. With a floating-point A/D con-
programmable gain amplifier in conjunction with the compara- verter the smallest value LSB corresponds to the LSB of the
tor circuit scales the input signal to a range between half scale monolithic converter divided by the maximum gain of the PGA.
and full scale for the maximum usable resolution. The floating point A/D converter has a full-scale range of 5 V, a
The A/D converter diagrammed in Figure 42 consists of a pair maximum gain of 16 V/V from the AD526 and a 12-bit A/D
of AD585 sample/hold amplifiers, a flash converter, a five-range converter; this produces:
programmable gain amplifier (the AD526) and a fast 12-bit A/D LSB = ([FSR/2N]/Gain) = ([5 V/4096]/16) = 76 µV. The
converter (the AD7572). The floating-point A/D converter dynamic range in dBs is based on the log of the ratio of the
achieves its high throughput rate of 125 kHz by overlapping the full-scale input range to the LSB; dynamic range = 20 log
acquisition time of the first sample/hold amplifier and the set- (5 V/76 µV) = 96 dB.
tling time of the AD526 with the conversion time of the A/D
converter. The first sample/hold amplifier holds the signal for
the flash autoranger, which determines which binary quantum

–15V +15V

+
+5V –15V +15V 10mF 10mF +5V
+
+ 5 6
+5V 1/6
10mF 10mF
+ BUSY
30pF D12
50kV MSB
+5V
74-
D11
123
CLOCK 1 3 1/2 VIN 74– D10
125MHz 1/6 1/6 1ms S/H
2 4 68pF LS174 D9
–15V +15V AD585
D8
+ 2.5MHz AD7572
–15V +15V 10mF 10mF D7
+

+
10mF 10mF 68pF
+ 10kV
F
S D6
AD526 47mF
VIN D5
+5V B D4
S/H 74–
AD585 LSB LS174 D3
VIN A0 A1 A2
D2
D1

10kV

–15V +15V +5V

10mF + A0
+ 10mF E1
10kV 74ALS86 A1
74– E2
+5VREF 1 3 12 A2 LS174
2 1/4 11 E3
13 1/4
10kV
5kV 10kV
4
AD588 6 NOTE: ALL BYPASS CAPACITORS ARE 0.1mF
5 1/4
2.5kV 10kV
1 3
9 8 2 1/4
10 1/4

1.25kV 10kV
1mF 11 10
1/6

1.25kV LM339A

Figure 42. Floating-Point A/D Converter

–12– REV. D
 AD526
HIGH ACCURACY A/D CONVERTERS hunting during the calibration process, the reference offset and
Very high accuracy and high resolution floating-point A/D con- gain codes should be different from the endpoint codes. A cali-
verters can be achieved by the incorporation of offset and gain bration cycle consists of selecting whether gain or offset is to be
calibration routines. There are two techniques commonly used calibrated then selecting the appropriate multiplexer channel to
for calibration, a hardware circuit as shown in Figure 43 and/or apply the reference voltage to the signal channel. Once the op-
a software routine. In this application the microprocessor is eration has been initiated, the counter, a 74ALS869, drives the
functioning as the autoranging circuit, requiring software over- D/A converter in a linear fashion providing a small correction
head; therefore, a hardware calibration technique was applied voltage to either the gain or offset trim point of the AD574. The
which reduces the software burden. The software is used to set output of the A/D converter is then compared to the value pre-
the gain of the AD526. In operation the signal is converted, and set in the 74ALS528 to determine a match. Once a match is
if the MSB of the AD574 is not equal to a Logical 1, the gain is detected, the 74ALS528 produces a low going pulse which stops
increased by binary steps, up to the maximum gain. This maxi- the counter. The code at the D/A converter is latched until the
mizes the full-scale range of the conversion process and insures next calibration cycle. Calibration cycles are under the control
a wide dynamic range. of the microprocessor in this application and should be imple-
The calibration technique uses two point correction, offset and mented only during periods of converter inactivity.
gain. The hardware is simplified by the use of programmable
magnitude comparators, the 74ALS528s, which can be “burned”
for a particular code. In order to prevent under or over range

+5V +15V –15V

200pF 10mF
+
10mF
+

–15V +15V MSB

NOISE
AD585
REDUCTION 7404
1mF 2 1
+15V
+5V F AD574 DATA
A3 BUS
R8 S
AD588 10kV –15V +15V
A1 AD7501 AD526
R1 R4 VIN1 VREF OP27
A4 –5V VIN2 1kV
R2 R5
VIN3 WR
+VS +15V LSB
50kV
R3 R6 0.1mF VIN4
A2 –VS SYS –15V
0.1mF GND DE- +5V
–15V DECODED DECODED CODED
WR WR
ADDRESS ADDRESS ADD

ADDRESS BUS
12 12
+5V

CALIBRATION
PRESET +5V +5V PIN 15 R5
MSB
VALUE AD588 20kV
PIN 28 5kV VREF R62
74ALS AD574 20kV
528 R72 A2
RFB A R21 10kV R11 GAIN
P=Q MSB AD7628 AD712
1 5kV
3 C12
7475 2 7400 INPUT
GAIN LATCH DAC A OUT A A1
1/2 BUFFER AGND
74ALS AD712
ADG221 869
RFB B R41
LSB 7475
WR C22
CONTROL
4 LSB LATCH DAC B OUT B A3
MSB 6 LOGIC
5 7400 R8
7475
AD712 20kV
74ALS
1/2 R92
AGND 10kV
528 +5V WR A/B
R102 A2
P=Q VREF OFFSET
20kV R12
PIN 15 AD712
5kV
OFFSET AD588
+5V
AGND
NOTE: ALL BYPASS CAPACITORS ARE 0.1mF

LSB

+5V

Figure 43. High Accuracy A/D Converter

REV. D –13–
AD526
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Plastic 16-Lead Sided-Brazed
DIP Package (N-16) Ceramic Package (D-16)

0.87 (22.1) MAX

0.430
(10.922)

C1103d–0–8/99
16 9 0.25 0.31
1 8
(6.25) (7.87) 0.040R 16 9
0.310 ⴞ0.01 0.265 0.290 ⴞ0.010
0.3 (7.62) (6.73) (7.37 ⴞ0.254)
PIN 1 0.035 (7.874 ⴞ0.254)
(0.89) 0.18 1 8
(4.57)
MAX PIN 1
0.18
0.125 (3.18)
(4.57) 0.011 0.800 ⴞ0.010
MIN (0.28) (20.32 ⴞ0.254) 0.300
0.018 0.100 0.033 SEATING 0.035 ⴞ0.01 (7.62)
(0.46) (2.54) (0.84) PLANE (0.889 ⴞ0.254) REF
0.095 (2.41) 0.085 (2.159)
0.125
0.180 ⴞ0.03
(3.175)
(4.57 ⴞ0.762) MIN
0.047 ⴞ0.007 0.100 0.010 ⴞ0.002
(1.19 ⴞ0.18) (2.54) SEATING (0.254 ⴞ0.05)
0.017 +0.003
–0.002 BSC PLANE
(0.43 +0.076
–0.05 )
0.700 (17.78) BSC

PRINTED IN U.S.A.

–14– REV. D