1

Intelligent and Miniaturized Neural Interfaces: An may present practical challenges in real-world deployments due to
Emerging Era in Neurotechnology the difficulty of gathering adequate neural activity relevant to
pathological brain states. Moreover, accurate decoding of complex
Mahsa Shoaran1, Uisub Shin1,2, MohammadAli Shaeri1 BMI tasks requires high-resolution intracortical or ECoG datasets.
1EPFL, Lausanne, Switzerland, 2Cornell University, Ithaca, NY For instance, restoring dexterous (i.e., with a high degree of freedom)
[23] or fine movements (i.e., with a high number of classes) like
Introduction handwriting [16] or speech ability [17, 18, 24] necessitates the
Over the past decade, there has been a growing interest in the recording of data from hundreds of electrodes or even more.
development of intelligent neural interface systems-on-chip (SoCs) Efficiency: The primary challenge in realizing a high-channel-count
for a range of neurological disorders and emerging brain-machine neural interface SoC lies in the increasing area and energy
interface (BMI) applications. The shift toward creating intelligent consumption of the hardware. The demand for compact, low-power
systems featuring on-implant signal processing, neural biomarker chips becomes even more critical in the context of brain implants due
extraction, and AI has replaced prior efforts that primarily focused on to their invasive nature, physical placement, and the potential risk of
raw neural signal acquisition and data compression for off-body heat generation, which could lead to tissue damage. Thus, ensuring
processing [1-4]. Integrating complex functions into miniaturized that the employed AI algorithms are scalable is essential to process
neural devices presents significant opportunities for various high-density neural data efficiently.
applications, including therapeutic devices for central nervous
system (CNS) disorders, peripheral nerve prostheses, spinal cord Flexibility and adaptability: Given the constrained area and power
interfaces, and beyond. In this paper, we review the latest budget, current SoCs often rely on low-complexity AI models and
advancements in the development of CMOS-based integrated small feature sets designed specifically for seizure detection.
circuits (ICs) for three categories of intelligent neural prostheses, all Embedding a flexible AI model along with an extensive set of
featuring embedded signal processing on the implantable or features could enable the identification of more intricate patterns in
wearable device. These categories include: 1) Neural interfaces for brain activity and extend adaptability to various disorders beyond
closed-loop symptom tracking and responsive stimulation; 2) Neural epilepsy. In addition, the characteristics of neural signals vary over
interfaces for emerging network-related conditions, such as time due to factors such as electrode movement, noise, and the
psychiatric and memory disorders; and 3) Intelligent BMI SoCs for dynamic nature of neural activity. In the context of epilepsy, there is
movement and communication recovery following paralysis. These also a need for algorithms capable of generalizing effectively across
developments mark the beginning of a dynamic field, and we patients with limited seizure data, diverse seizure types, and
anticipate the emergence of an even wider array of smart neural datasets with high variability among patients. Consequently, the field
prostheses in the years ahead. has witnessed the emergence of novel techniques, including few-
shot [25], one-shot [7], and zero-shot learning [26], as well as online
Challenges toward future intelligent neural interfaces learning algorithms and hardware [7, 10].
Integration of advanced signal processing and machine learning 1. Closed-loop stimulation with real-time symptom tracking
(ML) algorithms on neural interface systems can significantly
enhance the therapeutic potential of these devices in the future. For The most prevalent application of AI in neural SoCs pertains to
instance, AI-embedded neural interface technology has closed-loop stimulation systems, wherein stimulation parameters
demonstrated its potential in enabling accurate, personalized adapt in response to dynamic changes in the state of brain networks.
symptom detection for patients with brain disorders, particularly In this context, the closed-loop NeuralTree SoC [8, 27] presented
epilepsy. More than a decade of active innovation in the development potential solutions to address several of the aforementioned
of ICs and AI algorithms has led to the creation of advanced systems, challenges. A modular 256-ch front-end is implemented in the mixed-
achieving greater than 95% sensitivity and specificity in epileptic signal domain to enable area-efficient high-density neural sensing for
seizure detection using hardware-efficient invasive or non-invasive effective AI model training, as shown in Fig. 1(a). Furthermore, as
SoCs [5-10]. Similarly, embedded neural biomarkers can guide the depicted in Fig. 1(b), a dynamic channel-selective inference scheme
delivery of stimulation in a variety of neurological indications as they is implemented, in which only informative channels and features
can represent the dynamic state of neuronal activity over time [11- pertinent to specific disease states (identified via full-array high-
14]. Furthermore, software-based AI algorithms have enabled density training) undergo selective processing. This approach helps
increasingly complex BMI systems for rapid movement and to reduce hardware resource utilization during inference while
communication recovery [15-18], with miniaturized hardware preserving high accuracy. To enhance the SoC’s versatility across
implementations recently emerging [8, 19]. While this progress is multiple applications, a diverse set of biomarkers was integrated
promising, there are still several challenges that must be addressed using hardware-friendly feature approximations and extracted in a
for the next generation of intelligent neural interface SoCs. disease-specific manner. A tree-structured neural network classifier,
NeuralTree, employs hardware-efficient techniques such as network
Scalability: Remarkable seizure detection performance has been pruning and weight quantization. It is also trained with an energy-
achieved with hardware systems utilizing a limited number of sensing aware learning algorithm that penalizes power-demanding features,
channels (8-24) from well-established EEG datasets, such as the thereby further enhancing energy efficiency during inference.
pediatric CHB-MIT dataset [20]. A number of recent works expanded System-level co-design and optimization of circuits and algorithms
this to larger, intracranial EEG (iEEG)-based datasets with higher resulted in significant improvements in channel count, compactness,
number of channels (≤128) and more difficult seizure patterns from and energy efficiency. The SoC also integrates a 16-ch, area-
adults with intractable epilepsy [21, 22]. The limited spatial resolution efficient high-voltage-compliant stimulator. In addition to seizure
of electrodes in seizure detection or other symptom tracking systems detection, the SoC demonstrated on-chip detection of tremors in

Fig. 1. The NeuralTree SoC [8]: (a) A modular 256-ch front-end enables high-density sensing for AI training. (b) Brain-state inference is
executed along a single path of the tree, wherein the neural network in each node utilizes up to 64 dynamically selected features.
 2

Fine-tuning of model parameters was subsequently performed online

to account for inter-patient variability in seizure patterns.
2. New paradigms for closing the loop
Deep brain stimulation (DBS) stands as a well-established
therapeutic approach for movement disorders. Continuous high-
frequency DBS (e.g., 130Hz) has proven effective in suppressing
motor symptoms associated with PD and essential tremor.
Furthermore, DBS has exhibited potential in a growing range of
applications in recent years, spanning from movement disorders to
epilepsy, stroke, psychiatric and memory-related conditions [30].
However, open-loop DBS may result in various side effects,
excessive energy consumption and battery usage, and reduced
effectiveness over time [31, 32]. Recent evidence suggests that a
novel approach utilizing closed-loop, phase-locked DBS [33, 34] can
be as effective in addressing movement disorders [35] and holds
Fig. 2. Illustration of phase-locked DBS for regulating cross-region potential for treating psychiatric conditions like major depression
neural connectivity [43], and a potential advancement with on-chip [36]. While the biomarker-driven closed-loop approach (e.g.,
AI for emerging applications such as mental disorders. NeuralTree) is an effective solution for disorders with well-
Parkinson’s disease (PD) for the first time (Fig. 3, bottom-left), while established biomarkers such as epilepsy and PD, it may not be
the multi-class nature of the probabilistic NeuralTree [22] enables the equally suitable for psychiatric and memory disorders with more
potential deployment of this technology in prosthetic BMIs. intricate underlying mechanisms. Alternatively, phase-locked DBS
delivers bursts of stimulation precisely locked to specific phases of
Area-efficient SoC design neuronal oscillations, as illustrated in Fig. 2 (left). This approach
Scaling the channel count up to several thousands requires a holds the potential to enhance therapeutic efficacy while minimizing
substantial reduction in the die area occupied by neural recording side effects and enabling prolonged effectiveness, thanks to
amplifiers. To address this challenge, traditional AC-coupled neural enhanced plasticity [37].
amplifiers [28] have given way to mixed-signal or digitally intensive Furthermore, brain connectivity, whether within- or cross-region,
designs, which scale more gracefully with advanced CMOS plays a pivotal role in detecting pathological brain states across
technology nodes. The 0.025mm2/ch front-end in [4] introduced a various neurological and psychiatric disorders, particularly those that
mixed-signal electrode DC offset cancellation method, effectively impact distributed brain networks. For instance, it was shown that
replacing an area-consuming analog integrator. The adoption of an epileptic seizures manifest spatial and temporal changes in cross-
open-loop architecture for signal amplification facilitated a significant channel phase synchronization [38]. Also, excessive phase-
reduction in the input capacitors, at the expense of increased gain amplitude coupling (PAC) has been observed in patients with PD
mismatch. Recently, hardware sharing through time-division [39]. Moreover, conditions like depression [40], post-traumatic stress
multiplexing (TDM) has become a popular design choice for high- disorder (PTSD) [41], and Alzheimer's disease [42] have shown
density area-efficient neural recording. For instance, the NeuralTree disruptions in network connectivity, emphasizing the significance of
SoC’s 256-ch 0.004mm2/ch front-end utilized four 64-ch TDM connectivity analysis in understanding and diagnosing these
modules to perform high-density neural sensing for AI training. A two- complex disorders.
step fast-settling DC servo loop (DSL) rapidly canceled DC offsets
from multiplexed inputs, which were dynamically reconfigured for Inspired by these neuroscientific findings, a recent closed-loop
each 1s window of channel-selective inference. Another 256-ch neuromodulation SoC [14, 43] introduced novel stimulation
ECoG recording front-end adopted multiplexing and reported a paradigms, wherein neural connectivity within or across regions is
compact area of 0.001mm2/ch (with an off-chip multiplexed switch monitored continuously and regulated through phase-locked DBS.
matrix) [29]. A hardware-efficient DSL coarsely canceled electrode While earlier seizure detection SoCs [44, 45] demonstrated on-chip
DC offsets, while neural signals with residual offsets were digitized computation of connectivity metrics such as PAC and phase-locking
by incremental delta-sigma ADCs. In time-shared architectures, the value (PLV) using iterative vector processing with CORDICs, their
requirement for a wider bandwidth amplifier introduces elevated high accuracy comes at the cost of excessive power consumption
noise folding from electrodes. Therefore, the choice of an optimal (>200μW). In [14, 43], the complex nonlinear functions for phase and
degree of multiplexing is a critical decision that requires careful amplitude computation were efficiently approximated using a last-bit
consideration of various factors. These include electrode impedance, accurate linear arctangent algorithm and the ℓ ∞-norm, resulting in
available silicon area, desired signal modality and fidelity, along with >60% power savings for PAC/PLV extraction without compromising
the noise resilience inherent in AI models. accuracy. This SoC demonstrated the first-in-literature phase-locked
neurostimulator and was validated in-vivo in rats within regions
Other algorithm and hardware considerations associated with fear and anxiety (Fig. 3, bottom-right). In addition, a
As the channel count increases, the associated overhead for AI multi-mode stimulation control is supported through various
training can become prohibitively high. For instance, training the combinations of phase-locking events and thresholded connectivity
classifier on large neural data offline could demand a significant measures, which may be useful for treating different neurological
amount of energy consumption for raw data transmission. This may conditions in the future.
require the reemergence of lightweight compression techniques Further advancements in this technology can be achieved by
(e.g., compressive sensing [3]) or replacing raw data with feature integrating an AI model and utilizing its decision to guide phase-
transmission to lower the telemetry power during initial model locked DBS control, as envisioned for the treatment of mental
training. The integration of advanced security measures such as data disorders in Fig. 2 (right). Depending on the target application, it may
encryption will become imperative for such devices to protect be necessary to explore new types of biomarkers and connectivity
sensitive data and preserve privacy. Moreover, the classification measures to improve detection accuracy and therapeutic efficacy. In
performance may degrade over time as the pattern of pathological addition to traditional classifiers with handcrafted features, deep
brain activity changes. Recent SoCs have introduced several learning models that automatically mine features from raw neural
approaches to reduce retraining overhead and maintain long-term activity may offer promising alternatives. System-level innovation
accuracy. The seizure detector in [10] employed unsupervised across ICs and learning algorithms would be critical to efficiently
learning to retrain a logistic regression classifier online. While this integrate such complex models into resource-constrained brain
approach performed well on the CHB-MIT dataset, the basic linear implants. Lastly, there has been a continued demand and ongoing
model employed may not be optimal for handling more complex efforts to realize concurrent brain sensing and stimulation
seizure patterns. Another interesting concept was introduced in [26], capabilities for uninterrupted brain-state detection in closed-loop
where the SoC achieved patient-independent seizure detection by settings. This poses numerous circuit/algorithm design challenges,
training a convolutional neural network on pre-existing datasets.
3

Spike detection and sorting SoCs

As an initial step, the detection of spiking activity is crucial to analyze
intracortical data at the level of individual neurons. A common
approach is to detect threshold-crossing events either in the time or
nonlinear energy operator (NEO) transform domains as spikes [49-
52, 55, 59, 60, 64]. NEO emphasizes sharp, high-energy signal
changes, leading to superior detection accuracy and reduced
sensitivity to thresholds, making it a popular choice for spike
detection chips. While the threshold level can be computed during
off-chip training [60], there is a growing interest in on-chip
unsupervised approaches that adaptively compute the threshold [50,
52, 55, 59]. Traditionally, the threshold level can be adjusted online
using statistical measures such as the mean, median, or standard
deviation of the averaged signal over a sliding time window [51, 59,
64, 65]. To improve detection accuracy, a hardware-efficient
unsupervised dual detector was introduced in [50]. Utilizing two
detection pathways to discern signals in both high- and low-noise
scenarios, this approach achieved a record spike detection accuracy
of 97.4% on the standard Wave_Clus (Quiroga) dataset. Assuming
a known spiking rate for each specific brain region, a threshold was
efficiently calculated in [52], leading to reduced hardware costs albeit
with a trade-off in accuracy. While most spike detection SoCs have
been evaluated on the single-channel, synthetic Wave_Clus dataset,
validating their performance on emerging high-density datasets (e.g.,
those recorded by Utah arrays or Neuropixels probes) is crucial to
demonstrate their robustness and reliability for future clinical and
prosthetic applications.
Fig. 3. Chip micrographs and experimental results of the Standard AI tools play a significant role in spike sorting, the process
NeuralTree and phase-locked DBS SoCs [8, 43]. of assigning individual spikes into distinct clusters based on
waveform similarities. To achieve this, various features are extracted
including high-dynamic-range neural recording, fast artifact recovery, from the detected spikes and subsequently classified into separate
and stimulation artifact cancellation—all of which must be achieved neuronal classes. For instance, static time-domain features of spike
without consuming excessive area and power. waveforms such as spike peaks and their derivatives can be
extracted to reduce data dimensionality and the hardware complexity
3. Neural signal processing SoCs for BMI applications of classifiers [64, 66]. A salient feature selection method was
In another context, intelligent neural interfaces have the potential to proposed in [56] to dynamically select a minimal subset of spike
significantly improve prosthetic BMIs, with the goal of restoring lost features based on the highest class discrimination. Alternatively, an
motor or communication abilities for paralyzed patients. As efficiency ℓ2-normalized convolutional autoencoder with a fully connected layer
and miniaturization continue to improve, these interfaces can play a aimed to identify informative features for the clustering process [57].
pivotal role in facilitating the translation of BMIs into daily lives of The extraction of informative features not only enhances hardware
patients beyond clinical settings. Moreover, recent advancements in efficiency but also improves accuracy and robustness in the spike
ultra-high-density microelectrode arrays, dense cortical grids, and sorting process.
flexible polymer threads (e.g., Neuropixels probe and Neuralink To classify spike waveforms, several hardware-efficient methods
systems) are enabling unprecedented levels of sensing resolution in such as oblique decision trees [66] and window discrimination [56]
neural interfaces [27, 46-48]. While this has the potential to have been employed in literature. While these designs are not self-
revolutionize the functionality of BMIs, transmitting such a large sufficient and require off-chip training, a current technology direction
amount of data for offline processing and analysis comes with is to employ unsupervised spike sorters to eliminate the need for off-
significant power consumption and security risks. In realizing fully chip training. K-means and its variants are widely used for this
implantable, energy-efficient BMIs, it is crucial to implement on-chip purpose owing to the simplicity of the model. These methods assign
signal processing and/or data compression algorithms with minimal each data point to a cluster by evaluating the minimum distance,
power and area overhead, while preserving essential information. To utilizing various metrics such as ℓ1-norm [55] and ℓ2-norm distance
this end, a variety of on-chip signal processing approaches have [59], cosine similarity [57], or correlation coefficient [58].
been introduced for BMIs, ranging from spike detection [49-52] and Subsequently, the spike sorter updates the spike cluster using the
sorting [53-60] to feature extraction [8, 49, 56, 57] and movement newly acquired data. A recent spike sorter was developed
decoding [8, 19, 61-63]. specifically for the 384-ch Neuropixels probe with closely-spaced
Importantly, next-generation intelligent BMIs must incorporate on- electrodes [59]. Given that each neuronal spike may potentially be
chip decoding capabilities to support a variety of applications. Yet, recorded by multiple neighboring channels, this sorter selects the
the challenge arises from the fact that current software-based BMIs channel with the highest amplitude while discarding redundant
often utilize complex models like recurrent neural networks (RNNs) spikes captured by other channels. This approach has shown
with extensive parameter counts. Efficient integration of such models outstanding accuracy of 97.7% on a pre-recorded Neuropixels
in resource-limited implantable or wearable platforms presents a dataset. Recent spike sorting SoCs have achieved power levels in
significant challenge. This model complexity stems from the the order of 1-3μW/ch and 0.001-0.02mm2/ch silicon area [59, 60].
distributed nature of neural activity associated with motor functions, In the absence of ground truth datasets in spike sorting, current
resulting in significantly higher data dimensionality compared to evaluations rely on synthetic datasets or real recordings with
more typical problems like spike sorting. In addition, the complexity manually created labels, which hinders reliable accuracy
of BMI tasks (as indicated by factors such as the number of classes comparisons across systems. Additionally, challenges such as the
or degree of freedom) demands the use of advanced AI models separation of temporally overlapping spikes sensed by a single
rather than relying solely on basic signal processing and data electrode and low performance in high-noise scenarios are areas
clustering techniques. Thus, a primary hurdle in achieving fully- that must be addressed in the future.
implantable, miniaturized, and low-power BMIs is the development
of neural decoders capable of effectively learning from intricate high- Although many interesting spike detection and sorting approaches
dimensional neural data and seamlessly integrating them with brain have been proposed and implemented at the chip level, a significant
implants. hurdle is on-chip decoding of neural activity. While spike sorting
deals with relatively simple tasks, involving low-dimensional data and
 4

Fig. 5. The hardware architecture of the MiBMI chipset and related

timing diagram [19]. The integrated 192-ch front-end chip performs
area-efficient neural recording. Upon smoothing, detecting activity
onset, and alignment, the decoder extracts DNCs and classifies
the attempted character.
Fig. 4. The concept of distinctive neural codes (DNCs) and the
DNC-based decoding results on the 31-class handwriting task [19]. neural recording unit alongside the on-chip decoder can substantially
reduce power consumption and device form factor.
a limited number of classes, neural decoding necessitates the A miniaturized brain-to-text BMI
analysis of ultra-high-dimensional data with significantly greater task
complexity—a challenge yet to be fully addressed. A new generation of BMIs [16-18, 24] strives to greatly improve the
restoration of lost communication abilities such as writing and
Neural SoCs with embedded movement decoding speech for paralyzed patients. Thanks to the fine motor skills
Recent innovations in BMI technology have shown a remarkable required for tasks like handwriting, decoding such complex
potential for transforming the lives of individuals with paralysis, movements can be achieved at considerably higher speeds
particularly those who have lost the ability to move or communicate. compared to conventional BMIs that primarily predict simple point-
Empowered by advanced AI algorithms, recent BMIs have to-point movements. However, these tasks often demand
demonstrated the decoding of brain activity associated with various sophisticated AI models to decode neural activities linked to
movements and actions, including gait, reach-and-grasp, cursor dexterous motor skills, which poses challenges for efficient
control, typing, handwriting, and speech [15-18, 23, 24, 67-70]. integration within brain implants. To address this challenge, a recent
Moreover, notable breakthroughs have showcased the potential of miniaturized BMI chipset (MiBMI) [19] employed the new concept of
BMIs in studying cognitive processes such as decision-making and Distinctive Neural Code (DNC) as a promising solution to decode
neural plasticity [69, 70], providing insights into the complexities of attempted handwriting. Figure 4 illustrates the concept of a decoder
cognitive functions. However, these BMIs depend on powerful yet utilizing DNCs in the context of a conceptual 31-character
bulky computers with limited mobility, making them impractical for handwriting task [16]. Inspired by the brain’s saliency model of
everyday use and daily life settings of patients. attention, the most distinctive features of neural activity (i.e., DNCs)
Only a handful of papers have reported on-chip decoding for BMI are selected, effectively transforming a high-dimensional state space
applications. In [61], a neuromorphic SoC was developed to decode to a lower-dimensional subspace. This allows for the accurate
four-class neural activity evoked by cortical stimulation to control a differentiation of various classes in complex BMI tasks, while
robotic arm, consuming a substantial chip area and power. eliminating the need for resource-intensive pre-processing steps like
Alternatively, [62] demonstrated a 128-ch extreme learning machine time warping [16]. Another significant advantage is that, due to the
(ELM) for decoding finger movements. The hidden layer (i.e., a rich information content of DNCs, complex multi-class decoding
random projection layer) was implemented on chip, while the tasks can be achieved using simple classifiers (e.g., linear
processing of the output layer to generate decisions was conducted discriminant analysis or LDA) with 1750× fewer parameters
off-chip. The 93-ch intracortical BMI system in [63] decoded finger compared to the RNN used in [16].
movement intentions using spiking band power (SBP) features within Figure 5 shows the block diagram of the brain-to-text decoder
the 0.3–1kHz frequency range and a predictor based on a steady- exploiting DNCs. It receives a 512-ch neural input (i.e., spike counts),
state Kalman filter (SSKF). While this system achieved high accuracy which is then smoothed to mitigate the decoder's sensitivity to
in closed-loop finger movements, it exhibited a notable latency of up misalignments and noise (Fig. 5, right). A subset of neural activities
to 2.4s and utilized a commercial recording system (Intan). The high- is selected following a movement attempt, and their mean class
density NeuralTree SoC [8] enables ECoG-based finger movement activity is computed for onset detection and alignment. This is
classification, but it lacks high-bandwidth spike recording capability, followed by real-time extraction of DNCs for each class. This method
which is crucial for more complex motor decoding tasks. reduces data dimensionality by 51200× at the decoder's output,
Although the mentioned BMIs have shown high accuracy in decoding while also lowering the training time of the decoder. Moreover,
basic movements, there is an increasing need for the development through DNC extraction and memory sharing, this approach can
of advanced on-chip decoders, possibly using interpretable models, drastically reduce computational requirements, performing 320×
to handle more intricate BMI tasks like handwriting and speech. fewer MAC computations and utilizing 100× less memory compared
Utilizing interpretable models is beneficial not only for gaining to a traditional LDA model. The fabricated decoder occupied a
insights into brain functions but also for advancing prosthetics compact area of 0.75mm2, consumed 223μW, and achieved a
development by establishing solid scientific foundations. Moreover, notable accuracy of 90.8% in the 31-class motor decoding task.
these models often yield meaningful results, facilitating thorough To demonstrate the feasibility of a complete BMI chipset, a compact
validation of decoder predictions. Additionally, in the development of 192-ch neural recording chip was additionally integrated, as
implantable BMIs, the integration of a low-power, custom-designed illustrated in Fig. 5 (top-left). Each of the 24 multiplexed modules
5

Table I. Design specifications and performance summary of the state-of-the-art spike sorting and BMI SoCs.
Front. TBioCAS’19 J. Neurosci. TBioCAS’22
Parameter TBioCAS’16 [62] JSSC’22 [8] TBioCAS’22 [63] JSSC’23 [59] ISSCC’24 [19]
Neurosci.’16 [61] [55] Methods’19 [54] [60]

Process (nm) 180 350 130 40 22 65 180 22 65

Supply Voltage (V) 1.8 0.6/1.2 1.09 1.1 0.5-0.8 1.2 0.625 0.59 1.2

# of Channels 15 128 10 16 16 256† 93 384 192/512

Symmlet-2 Adaptive Spectral Spike peak and

Features - - - SBP DNC
Wavelet filtering powers, LMP derivatives

Decoding Model SNN ELM K-means BOTM K-means NeuralTree SSKF K-means LDA

Prosthetic Finger Finger

Decoding Task Spike Sorting Spike Sorting Spike Sorting Finger Movement Spike Sorting Handwriting
Control Movement Movement

Input Signal Spike Train Spike Train Intracortical Intracortical Intracortical ECoG Intracortical Intracortical Spiking Rate

# of Classes 4 12 5‡ 4‡ 8‡ 6 Continuous 2‡ 31

Accuracy (%) 50−70 99.3 N/A 93.4* 94.12* 73.3 100(1D), 96(2D) 89.5*, 97.7+ 90.8A, 91.3B

AI Area/ch (mm2) 2.86$ 0.133$^ 0.08 0.0175 0.014 0.02$ 0.097 0.0013 0.0015

#
AI Power/ch (µW) 267 0.01^ 56.9 19 2.79 4.24 6.2(1D), 6.3(2D) 1.78 0.44

† Selective 64-ch processing ‡ Maximum number of clusters/ch * Wave_Clus dataset + Neuropixels dataset $ Estimated active area
# A B
^ Excluding the off-chip output layer Power measured with 40 input channels Measured on 620s data Simulated on 10.7-hr data

records 8-ch broadband (10kHz) neural activity containing both neurological applications, hardware realization of AI models, among
action potentials (APs) and local field potentials (LFPs). Through others. We also discussed various IC and SoC design examples that
binary search in the feedback, the DC offsets from multiplexed inputs aim to address these challenges either individually or collectively, in
are suppressed to a linear range of the amplifiers. In this time-shared addition to providing an outlook on other important problems that
architecture, inter-channel crosstalk is effectively reduced by remain to be tackled. Continued research and development efforts
periodically resetting the capacitors, while the resulting kT/C as well led by circuit designers and AI experts are anticipated to further
as flicker noise are up-modulated by chopping and subsequently advance this new era in neurotechnology, ultimately enhancing the
filtered out. The 192-ch recording chip occupied an active area of quality of life for a diverse population of patients around the world.
1.7mm2 (0.009mm2/ch) and consumed 660μW (3.44μW/ch). This References:
demonstrates the potential for replacing power-demanding and bulky
off-the-shelf recording units, enabling the realization of fully [1] R.R. Harrison et al., “A Low-Power Integrated Circuit for a
implantable and miniaturized BMIs. Wireless 100-Electrode Neural Recording System,” JSSC, Jan.
2007.
Table I summarizes the state-of-the-art BMI SoCs with embedded
AI. For spike sorters, the maximum number of spike clusters per [2] D.A. Borton et al., “An implantable wireless neural interface for
channel is reported as a measure of task complexity. As the recording cortical circuit dynamics in moving primates,” J.
technology matures, there has been a clear shift toward the Neuroeng., Feb. 2013.
development of high-channel-count, low-power, and miniaturized [3] M. Shoaran et al., “Compact Low-Power Cortical Recording
BMIs. With advances in feature engineering, efficient data Architecture for Compressive Multichannel Data Acquisition,”
representation, and on-chip AI, the complexity of decoding tasks has TBioCAS, Dec. 2014.
also evolved—from single-digit-class spike sorting and finger [4] R. Muller et al., “A Minimally Invasive 64-Channel Wireless
movement to more intricate 31-class character decoding. μECoG Implant,” JSSC, Jan. 2015.
New opportunities in AI-enhanced BMIs [5] M.A.B. Altaf and J. Yoo, “A 1.83 μJ/Classification, 8-Channel,
Current BMIs primarily rely on powerful external computers (e.g., Patient-Specific Epileptic Seizure Classification SoC Using a Non-
CPUs or GPUs) for neural signal processing. On the other hand, the Linear Support Vector Machine,” TBioCAS, Feb. 2016.
next-generation BMIs aim to become unintrusive, low-power [6] M.A.B. Altaf, C. Zhang and J. Yoo, “A 16-Channel Patient-Specific
implantable devices, ideal for daily-life applications in patients with Seizure Onset and Termination Detection SoC With Impedance-
disabilities. These devices will seamlessly incorporate efficient AI Adaptive Transcranial Electrical Stimulator,” JSSC, Nov. 2015.
models to learn and decode complex neural data, while enhancing
[7] M. Zhang et al., “A Patient-Specific Closed-Loop Epilepsy
patient privacy and reducing reliance on data telemetry.
Management SoC With One-Shot Learning and Online Tuning,”
To serve as practical neuroprostheses for patients, decoding models JSSC, Apr. 2022.
must offer both low latency and high accuracy. Closed-loop BMIs can
[8] U. Shin et al., “NeuralTree: A 256-Channel 0.227-μJ/Class
further enable bidirectional communication between the neural
Versatile Neural Activity Classification and Closed-Loop
interface and the user, allowing real-time adjustments and enhancing
Neuromodulation SoC,” JSSC, Nov. 2022.
prosthetic device functionality. For instance, incorporating tactile and
sensory feedback mechanisms can provide patients with a more [9] Y. Wang et al., “A Closed-Loop Neuromodulation Chipset With 2-
natural and dexterous control experience over the BMI. Furthermore, Level Classification Achieving 1.5-Vpp CM Interference Tolerance,
hybrid BMIs capable of decoding multiple neural signal modalities 35-dB Stimulation Artifact Rejection in 0.5ms and 97.8%-Sensitivity
hold the potential to enhance the robustness and decoding accuracy Seizure Detection,” TBioCAS, Aug. 2021.
of these interfaces in the future. [10] A. Chua, M.I. Jordan and R. Muller, “SOUL: An Energy-Efficient
Conclusion Unsupervised Online Learning Seizure Detection Classifier,” JSSC,
Aug. 2022.
This paper reviewed the major challenges in advancing intelligent
neural interface technology, including closed-loop neuromodulation [11] F.T. Sun and M.J. Morrell, “The RNS System: responsive cortical
and prosthetic BMIs, with a special focus on integrated circuits and stimulation for the treatment of refractory partial epilepsy,” Expert
on-chip AI. We delved into various aspects such as the development Review of Medical Devices, Nov. 2014.
of high-resolution neural recording ICs, exploration of new
biomarkers and closed-loop stimulation methods for emerging
 6

[12] M. Shoaran et al., “A 16-channel 1.1mm2 implantable seizure [38] F. Mormann et al., “Mean phase coherence as a measure for
control SoC with sub-μW/channel consumption and closed-loop phase synchronization and its application to the EEG of epilepsy
stimulation in 0.18µm CMOS,” VLSI, Jun. 2016. patients,” Phys. D: Nonlinear Phenomena, Oct. 2000.
[13] M. Shoaran et al., “A Fully Integrated IC With 0.85-μW/Channel [39] C. De Hemptinne et al., “Exaggerated phase–amplitude coupling
Consumption for Epileptic iEEG Detection,” TCAS II, Feb. 2015. in the primary motor cortex in Parkinson disease,” Proc. Nat. Acad.
[14] U. Shin et al., “A 16-Channel 60μW Neural Synchrony Processor Sci., Mar. 2013.
for Multi-Mode Phase-Locked Neurostimulation,” CICC, Apr. 2022. [40] A.T. Drysdale et al., “Resting-state connectivity biomarkers
[15] T. Aflalo et al., “Decoding motor imagery from the posterior define neurophysiological subtypes of depression,” Nat. Med., Jan.
parietal cortex of a tetraplegic human,” Science, May 2015. 2017.
[16] F.R. Willett et al., “High-performance brain-to-text [41] C. Imperatori et al., “Aberrant EG functional connectivity and
communication via handwriting,” Nature, May 2021. EEG power spectra in resting state post-traumatic stress disorder: A
sLORETA study,” Biol. Psychol., Oct. 2014.
[17] F.R. Willett et al., “A high-performance speech neuroprosthesis,”
Nature, Aug. 2023. [42] C.S. Musaeus et al., “Electroencephalographic cross-frequency
coupling as a sign of disease progression in patients with mild
[18] S.L. Metzger et al., “A high-performance neuroprosthesis for cognitive impairment: a pilot study,” Front. in Neurosci., Aug. 2020.
speech decoding and avatar control,” Nature, Aug. 2023.
[43] U. Shin et al., “A 16-Channel Low-Power Neural Connectivity
[19] M. Shaeri et al., “MiBMI: A 192/512-Channel 2.46mm2 Extraction and Phase-Locked Deep Brain Stimulation SoC,” SSC-L,
Miniaturized Brain-Machine Interface Chipset Enabling 31-Class Jan. 2023.
Brain-to-Text Conversion Through Distinctive Neural Codes,”
ISSCC, Feb. 2024 (accepted for presentation). [44] K. Abdelhalim et al., “64-Channel UWB Wireless Neural Vector
Analyzer SoC With a Closed-Loop Phase Synchrony-Triggered
[20] A.L. Goldberger et al., “PhysioBank, PhysioToolkit, and Neurostimulator,” JSSC, Jul. 2013.
PhysioNet: components of a new research resource for complex
physiologic signals,” Circulation, Jun. 2000. [45] G. O’Leary et al., “NURIP: Neural Interface Processor for Brain-
State Classification and Programmable-Waveform
[21] M. Shoaran et al., “Energy-Efficient Classification for Resource- Neurostimulation,” JSSC, Nov. 2018.
Constrained Biomedical Applications,” JETCAS, Dec. 2018.
[46] N.A. Steinmetz et al., “Neuropixels 2.0: A miniaturized high-
[22] B. Zhu, M. Farivar and M. Shoaran, “ResOT: Resource-Efficient density probe for stable long-term brain recordings,” Science, Apr.
Oblique Trees for Neural Signal Classification,” TBioCAS, Aug. 2021.
2020.
[47] K. Sahasrabuddhe et al., “The Argo: a high channel count
[23] S.N. Flesher et al., “A brain-computer interface that evokes recording system for neural recording in vivo,” J. Neur. Eng., Feb.
tactile sensations improves robotic arm control,” Science, May 2021. 2021.
[24] S. Duraivel et al., “High-resolution neural recordings improve the [48] D.-Y. Yoon et al., “A 1024-channel simultaneous recording
accuracy of speech decoding,” Nat. Commun., Nov. 2023. neural SoC with stimulation and real-time spike detection,” VLSI,
[25] B. Zhu and M. Shoaran, “Unsupervised Domain Adaptation for Jun. 2021.
Cross-Subject Few-Shot Neurological Symptom Detection,” NER, [49] M. Shaeri and A.M. Sodagar, “Data transformation in the
May 2021 processing of neuronal signals: A powerful tool to illuminate
[26] C.-W. Tsai et al., “SciCNN: A 0-Shot-Retraining Patient- informative contents,” RBME, Feb. 2022.
Independent Epilepsy-Tracking SoC,” ISSCC, Feb. 2023. [50] X. Guo, M. Shaeri and M. Shoaran, “An accurate and hardware-
[27] U. Shin et al., “A 256-Channel 0.227μJ/class Versatile Brain efficient dual spike detector for implantable neural interfaces,”
Activity Classification and Closed-Loop Neuromodulation SoC with BioCAS, Oct. 2022.
0.004mm2-1.51μW/channel Fast-Settling Highly Multiplexed Mixed- [51] Z. Zhang and T.G. Constandinou, “Adaptive spike detection and
Signal Front-End,” ISSCC, Feb. 2022. hardware optimization towards autonomous, high-channel-count
[28] R.R. Harrison and C. Charles, “A low-power low-noise CMOS BMIs,” J. Neurosci. Meth., Apr. 2021.
amplifier for neural recording applications,” JSSC, Jun. 2003. [52] Z. Zhang et al., “Calibration-Free and Hardware-Efficient Neural
[29] X. Huang et al., “Actively Multiplexed μECoG Brain Implant Spike Detection for Brain Machine Interfaces,” TBioCAS, Aug. 2023.
System With Incremental-ΔΣ ADCs Employing Bulk-DACs,” JSSC, [53] M. Shaeri, A. Afzal and M. Shoaran, “Challenges and
Nov. 2022. opportunities of edge AI for next-generation implantable BMIs,”
[30] A.M. Lozano et al., “Deep brain stimulation: current challenges AICAS, Jun. 2022.
and future directions,“ Nat. Rev. Neurol., Mar. 2019. [54] H. Xu et al., “Unsupervised and real-time spike sorting chip for
[31] L. Yao, P. Brown and M. Shoaran, “Resting Tremor Detection in neural signal processing in hippocampal prosthesis,” J. Neurosci.
Parkinson's Disease with Machine Learning and Kalman Filtering,” Meth., Jan. 2019.
BioCAS, Oct. 2018. [55] G. Gagnon-Turcotte et al., “A wireless electro-optic headstage
[32] L. Yao, P. Brown and M. Shoaran, “Improved detection of with a 0.13-μm CMOS custom integrated DWT neural signal decoder
Parkinsonian resting tremor with feature engineering and Kalman for closed-loop optogenetics,” TBioCAS, Oct. 2019.
filtering,” Clin. Neurophysiol., Jan. 2020. [56] M. Shaeri and A.M. Sodagar “A framework for on-implant spike
[33] L.S. Kumari and A.Z. Kouzani, “Phase-Dependent Deep Brain sorting based on salient feature selection,” Nature Commun., Jun.
Stimulation: A Review”, Brain Sci., Mar. 2021. 2020.
[34] S.R. Schreglmann et al., “Non-invasive suppression of essential [57] C. Seong, W. Lee and D. Jeon, “A Multi-Channel Spike Sorting
tremor via phase-locked disruption of its temporal coherence,” Nat. Processor With Accurate Clustering Algorithm Using Convolutional
Commun., Jan. 2021. Autoencoder,” TBioCAS, Dec. 2021,
[35] H. Cagnan et al., “Stimulating at the right time: phase-specific [58] F. Kalantari, H. Hosseini-Nejad and A.M. Sodagar, “Hardware-
deep brain stimulation,” Brain, Jan. 2017. Efficient, On-the-Fly, On-Implant Spike Sorter Dedicated to Brain-
[36] C.R.P. Sullivan, S. Olsen and A.S. Widge, “Deep brain Implantable Microsystems,” TVLSI, Aug. 2022.
stimulation for psychiatric disorders: From focal brain targets to [59] Y. Chen et al., “An Online-Spike-Sorting IC Using Unsupervised
cognitive networks,” NeuroImage, Jan. 2021. Geometry-Aware OSort Clustering for Efficient Embedded Neural-
[37] S. Zanos et al., “Phase-Locked Stimulation during Cortical Beta Signal Processing,” JSSC, Nov. 2023.
Oscillations Produces Bidirectional Synaptic Plasticity in Awake [60] S.M.A. Zeinolabedin et al., “A 16-channel fully configurable
Monkeys,” Curr. Biol., Aug. 2018. neural SoC with 1.52 μW/ch signal acquisition 2.79 μW/ch real-time
7

spike classifier, and 1.79 TOPS/W deep neural network accelerator

in 22 nm FDSOI,” TBioCAS, Feb. 2022.
[61] F. Boi et al., “A bidirectional brain-machine interface featuring a
neuromorphic hardware decoder,” Front. Neurosci., Dec. 2016.
[62] Y. Chen, E. Yao and A. Basu, “A 128-channel extreme learning
machine-based neural decoder for brain machine interfaces,”
TBioCAS, Jun. 2016.
[63] H. An et al., “A power-efficient brain-machine interface system
with a sub-mW feature extraction and decoding ASIC demonstrated
in nonhuman primates,” TBioCAS, Jun. 2022.
[64] V. Karkare, S. Gibson and D. Marković, “A 130-μW, 64-Channel
Neural Spike-Sorting DSP Chip,” JSSC, May 2011.
[65] R.R. Harrison, “The Design of Integrated Circuits to Observe
Brain Activity,” Proc. IEEE, Jul. 2008.
[66] Y. Yang, S. Boling and A.J. Mason, “A hardware-efficient
scalable spike sorting neural signal processor module for
implantable high-channel-count brain machine interfaces,”
TBioCAS, Aug. 2017.
[67] A. Ajiboye et al., “Restoration of reaching and grasping
movements through brain-controlled muscle stimulation in a person
with tetraplegia: a proof-of-concept demonstration,” The Lancet, May
2017.
[68] H. Lorach et al., “Walking naturally after spinal cord injury using
a brain–spine interface,” Nature, Jun. 2023.
[69] R.A. Andersen et al., “Exploring Cognition with Brain–Machine
Interfaces,” Ann. Rev. Psych., Jan. 2022.
[70] M.C. Dadarlat, R.A. Canfield and A.L. Orsborn, “Neural Plasticity
in Sensorimotor Brain–Machine Interfaces,” Ann. Rev. Biomed. Eng.,
Jun. 2023.