STM32F401xD STM32F401xE

ARM Cortex-M4 32b MCU+FPU, 105 DMIPS,

512KB Flash/96KB RAM, 11 TIMs, 1 ADC, 11 comm. interfaces
Datasheet - preliminary data

Features
• Includes ST state-of-the-art patented
UFBGA

technology
® ®
• Core: Arm 32-bit Cortex -M4 CPU with FPU,
adaptive real-time accelerator (ART UFQFPN48 UFBGA100
WLCSP49 LQFP100 (14 × 14 mm) (7 × 7 mm)
Accelerator) allowing 0-wait state execution (3.029 x 3.029 mm)LQFP64 (10 × 10 mm)
(7 × 7 mm)
from flash memory, frequency up to 84 MHz,
memory protection unit, • Debug mode
105 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), – Serial wire debug (SWD) & JTAG
and DSP instructions interfaces
• Memories – Cortex®-M4 Embedded Trace Macrocell™
– Up to 512 Kbytes of flash memory • Up to 81 I/O ports with interrupt capability
– up to 96 Kbytes of SRAM – Up to 78 fast I/Os up to 42 MHz
– 512 bytes of OTP memory – All I/O ports are 5 V-tolerant
• Clock, reset, and supply management • Up to 12 communication interfaces
– 1.7 V to 3.6 V application supply and I/Os – Up to 3 x I2C interfaces (SMBus/PMBus)
– POR, PDR, PVD, and BOR – Up to 3 USARTs (2 x 10.5 Mbit/s,
– 4-to-26 MHz crystal oscillator 1 x 5.25 Mbit/s), ISO 7816 interface, LIN,
– Internal 16 MHz factory-trimmed RC IrDA, modem control)
– 32 kHz oscillator for RTC with calibration – Up to 4 SPIs (up to 42Mbit/s at
– Internal 32 kHz RC with calibration fCPU = 84 MHz), SPI2 and SPI3 with muxed
full-duplex I2S to achieve audio class
• Power consumption accuracy via internal audio PLL or external
– Run: 146 µA/MHz (peripheral off) clock
– Stop (Flash in Stop mode, fast wake-up – SDIO interface
time): 42 µA typical at 25 °C; 65 µA max at – Advanced connectivity: USB 2.0 full-speed
25 °C device/host/OTG controller with on-chip
– Stop (Flash in Deep power down mode, PHY
fast wake-up time): down to 10 µA at 25 °C; • CRC calculation unit
30 µA max at 25 °C
– Standby: 2.4 µA at 25 °C / 1.7 V without • 96-bit unique ID
RTC; 12 µA at 85 °C at 1.7 V • RTC: subsecond accuracy, hardware calendar
– VBAT supply for RTC: 1 µA at 25 °C • All packages are ECOPACK2 compliant
• 1×12-bit, 2.4 MSPS A/D converter: up to 16
channels Table 1. Device summary
• General-purpose DMA: 16-stream DMA Reference Part number
controllers with FIFOs and burst support
STM32F401CD,
• Up to 11 timers: up to six 16-bit, two 32-bit STM32F401xD
STM32F401RD, STM32F401VD
timers up to 84 MHz, each with up to four
IC/OC/PWM or pulse counter and quadrature STM32F401CE,
(incremental) encoder input, two watchdog STM32F401xE
STM32F401RE, STM32F401VE
timers (independent and window) and a
SysTick timer

January 2025 DS10086 Rev 4 1/138

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to www.st.com
change without notice.
Contents STM32F401xD STM32F401xE

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 Compatibility with STM32F4 series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1 Arm® Cortex®-M4 with FPU core with embedded
flash memory and SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2 Adaptive real-time memory accelerator (ART Accelerator) . . . . . . . . . . . 15
3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4 Embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 16
3.6 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.7 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.8 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.9 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 18
3.10 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.11 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.12 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.13 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.14 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.14.1 Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.14.2 Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.15 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.15.1 Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.15.2 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.15.3 Regulator ON/OFF and internal power supply supervisor availability . . 25
3.16 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 25
3.17 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.18 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.19 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.19.1 Advanced-control timers (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

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3.19.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.19.3 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.19.4 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.19.5 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.20 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.21 Universal synchronous/asynchronous receiver transmitters (USART) . . 29
3.22 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.23 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.24 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.25 Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . . . . 30
3.26 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 31
3.27 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.28 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.29 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.30 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.31 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.3.2 VCAP_1/VCAP_2 external capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.3.3 Operating conditions at power-up / power-down (regulator ON) . . . . . . 62
6.3.4 Operating conditions at power-up / power-down (regulator OFF) . . . . . 62

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6.3.5 Embedded reset and power control block characteristics . . . . . . . . . . . 63

6.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.3.7 Wake-up time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.3.8 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.3.9 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.3.11 PLL spread spectrum clock generation (SSCG) characteristics . . . . . . 84
6.3.12 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.3.13 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.3.14 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 89
6.3.15 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.3.16 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.3.17 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.3.18 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.3.19 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
6.3.20 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
6.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.3.22 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
6.3.23 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
6.3.24 SD/SDIO MMC card host interface (SDIO) characteristics . . . . . . . . . 113
6.3.25 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

7.1 Device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
7.2 WLCSP49 package information (A0ZV) . . . . . . . . . . . . . . . . . . . . . . . . . .117
7.3 UFQFPN48 package information (A0B9) . . . . . . . . . . . . . . . . . . . . . . . . 120
7.4 LQFP64 package information (5W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
7.5 LQFP100 package information (1L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
7.6 UFBGA100 package information (A0C2) . . . . . . . . . . . . . . . . . . . . . . . . 129
7.7 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
7.7.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

9 Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

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List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. STM32F401xD/xE features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. Regulator ON/OFF and internal power supply supervisor availability. . . . . . . . . . . . . . . . . 25
Table 4. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 5. Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 6. USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 7. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 8. STM32F401xD/xE pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 9. Alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 10. STM32F401xD/xE
register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 11. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 12. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 13. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 14. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 15. Features depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 16. VCAP_1/VCAP_2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 17. Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 62
Table 18. Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 63
Table 19. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 20. Typical and maximum current consumption, code with data processing (ART
accelerator disabled) running from SRAM - VDD = 1.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 21. Typical and maximum current consumption, code with data processing (ART
accelerator disabled) running from SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 22. Typical and maximum current consumption in run mode, code with data processing
(ART accelerator enabled except prefetch) running from Flash memory- VDD = 1.7 V . . . 66
Table 23. Typical and maximum current consumption in run mode, code with data processing
(ART accelerator enabled except prefetch) running from Flash memory - VDD = 3.3 V . . 67
Table 24. Typical and maximum current consumption in run mode, code with data processing
(ART accelerator disabled) running from Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 25. Typical and maximum current consumption in run mode, code with data processing
(ART accelerator enabled with prefetch) running from Flash memory . . . . . . . . . . . . . . . . 68
Table 26. Typical and maximum current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 27. Typical and maximum current consumptions in Stop mode - VDD=1.8 V . . . . . . . . . . . . . . 69
Table 28. Typical and maximum current consumption in Stop mode - VDD=3.3 V. . . . . . . . . . . . . . . 69
Table 29. Typical and maximum current consumption in Standby mode - VDD=1.8 V . . . . . . . . . . . . 70
Table 30. Typical and maximum current consumption in Standby mode - VDD=3.3 V . . . . . . . . . . . . 70
Table 31. Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . . 70
Table 32. Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 33. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 34. Low-power mode wake-up timings(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 35. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 36. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 37. HSE 4-26 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 38. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 39. HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 40. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 41. Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

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Table 42. PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 43. SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 44. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 45. Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 46. Flash memory programming with VPP voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 47. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 48. EMS characteristics for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 49. EMI characteristics for WLCSP49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 50. EMI characteristics for LQFP100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 51. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 52. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 53. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 54. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 55. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 56. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 57. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 58. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 59. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 60. SCL frequency (fPCLK1= 42 MHz, VDD = VDD_I2C = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 61. SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 62. I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 63. USB OTG FS startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 64. USB OTG FS DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 65. USB OTG FS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 66. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 67. ADC accuracy at fADC = 18 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 68. ADC accuracy at fADC = 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 69. ADC accuracy at fADC = 36 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 70. ADC dynamic accuracy at fADC = 18 MHz - limited test conditions . . . . . . . . . . . . . . . . . 109
Table 71. ADC dynamic accuracy at fADC = 36 MHz - limited test conditions . . . . . . . . . . . . . . . . . 109
Table 72. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 73. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 74. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 75. Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 76. Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 77. Dynamic characteristics: SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 78. RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 79. WLCSP49 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 80. WLCSP49 - Example of PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 81. UFQFPN48 – Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 82. LQFP64 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 83. LQFP100 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 84. UFBGA100 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 85. UFBGA100 - Example of PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . . 131
Table 86. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 87. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 88. Device order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 89. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

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STM32F401xD STM32F401xE List of figures

List of figures

Figure 1. Compatible board design for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 2. Compatible board design for LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 3. STM32F401xD/xE block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 4. Multi-AHB matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 5. Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 20
Figure 6. PDR_ON control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 7. Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 8. Startup in regulator OFF: slow VDD slope -
power-down reset risen after VCAP_1/VCAP_2 stabilization. . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 9. Startup in regulator OFF mode: fast VDD slope -
power-down reset risen before VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 10. STM32F401xD/xE WLCSP49 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 11. STM32F401xD/xE UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 12. STM32F401xD/xE LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 13. STM32F401xD/xE LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 14. STM32F401xD/xE UFBGA100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 15. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 16. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 17. Input voltage measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 18. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 19. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 20. External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 21. Typical VBAT current consumption (LSE and RTC ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 22. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 23. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 24. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 25. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 26. ACCHSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 27. ACCLSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 28. PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 29. PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 30. FT I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 31. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 32. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 33. I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 34. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 35. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 36. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 37. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 38. I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 39. USB OTG FS timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . 106
Figure 40. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 41. Typical connection diagram when using the ADC with FT/TT pins featuring analog switch
function 110
Figure 42. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 111
Figure 43. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 112
Figure 44. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 45. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

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8
List of figures STM32F401xD STM32F401xE

Figure 46. WLCSP49 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 47. WLCSP49 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 48. WLCSP49 marking(package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 49. UFQFPN48 – Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 50. UFQFPN48 – Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 51. UFQFPN48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 52. LQFP64 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 53. LQFP64 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 54. LQFP100 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 55. LQFP100 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 56. UFBGA100 - Outline(13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 57. UFBGA100 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

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STM32F401xD STM32F401xE Introduction

1 Introduction

This document provides the ordering information and mechanical device characteristics of
the STM32F401xD/xE microcontrollers.
This document has to be read with RM0368 reference manual, which is available from the
STMicroelectronics website www.st.com. It includes all information concerning flash
memory programming.
For information on the Arm®(a) Cortex®-M4 core,refer to the Cortex®-M4 programming
manual (PM0214) available from www.st.com.
For information on the device errata with respect to the datasheet and reference manual,
refer to the STM32F401xD and STM32F401xE errata sheet (ES0299), available from
www.st.com.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

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54
Description STM32F401xD STM32F401xE

2 Description

The STM32F401XD/XE devices are based on the high-performance Arm® Cortex® -M4 32-
bit RISC core operating at a frequency of up to 84 MHz.
The Cortex®-M4 core features a floating-point unit (FPU) single precision, which supports all
Arm single-precision data-processing instructions and data types. It also implements a full
set of DSP instructions and a memory protection unit (MPU), which enhances application
security.
The STM32F401xD/xE incorporate high-speed embedded memories (512 Kbytes of flash
memory, 96 Kbytes of SRAM), and an extensive range of enhanced I/Os and peripherals
connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix.
All devices offer one 12-bit ADC, a low-power RTC, six general-purpose 16-bit timers
including one PWM timer for motor control, two general-purpose 32-bit timers. They also
feature standard and advanced communication interfaces.
• Up to three I2Cs
• Up to four SPIs
• Two full duplex I2Ss. To achieve audio class accuracy, the I2S peripherals can be
clocked via a dedicated internal audio PLL or via an external clock to allow
synchronization.
• Three USARTs
• SDIO interface
• USB 2.0 OTG full speed interface
The STM32F401xD/xE operate in the - 40 to + 105 °C temperature range from a 1.7 (PDR
OFF) to 3.6 V power supply. A comprehensive set of power-saving mode allows the design
of low-power applications.
These features make the STM32F401xD/xE microcontrollers suitable for a wide range of
applications:
• Motor drive and application control
• Medical equipment
• Industrial applications: PLC, inverters, circuit breakers
• Printers, and scanners
• Alarm systems, video intercom, and HVAC
• Home audio appliances
• Mobile phone sensor hub

Table 2. STM32F401xD/xE features and peripheral counts

Peripherals STM32F401xD STM32F401xE

Flash memory in Kbytes 384 512

SRAM in Kbytes System 96
General-
7
purpose
Timers
Advanced-
1
control

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STM32F401xD STM32F401xE Description

Table 2. STM32F401xD/xE features and peripheral counts (continued)

Peripherals STM32F401xD STM32F401xE

4/2 (full 4/2 (full

SPI/ I2S 3/2 (full duplex) 3/2 (full duplex)
duplex) duplex)
Communication I2C 3
interfaces
USART 3
SDIO - 1 - 1
USB OTG FS 1
GPIOs 36 50 81 36 50 81

12-bit ADC 1
Number of channels 10 16 10 16
Maximum CPU frequency 84 MHz
Operating voltage 1.7 to 3.6 V
Ambient temperatures: –40 to +85 °C/–40 to +105 °C
Operating temperatures
Junction temperature: –40 to + 125 °C
WLCSP49 UFBGA100 WLCSP49 UFBGA100
Package LQFP64 LQFP64
UFQFPN48 LQFP100 UFQFPN48 LQFP100

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54
Description STM32F401xD STM32F401xE

2.1 Compatibility with STM32F4 series

The STM32F401xD/xE are fully software and feature compatible with the STM32F4 series
(STM32F42x, STM32F43x, STM32F41x, STM32F405 and STM32F407)
The STM32F401xD/xE can be used as a drop-in replacement of the other STM32F4
products but some slight changes have to be done on the PCB board.

Figure 1. Compatible board design for LQFP100 package

STM32F4x1
STM32F405/STM32F415 line
STM32F407/STM32F417 line 58 PD11 58 PD11
57 PD10 57 PD10
STM32F427/STM32F437 line 56 PD9 56 PD9
STM32F429/STM32F439 line 55 PD8 PB11 not available anymore 55 PD8
54 PB15 Replaced by V CAP1 54 PB15
53 PB14 53 PB14
52 PB13 52 PB13
51 PB12 51 PB12
41
42
43
44
45
46
47
48
49
50

48
49
41
42
43
44
45
46
47

50
VDD
PE10

PE12
PE13
PE14
PE15
PB10
PE11

VCAP1
PB11

VCAP1

VDD
PE10

PE12
PE13
PE14
PE15
PB10
PE11

VSS
VSS VDD
VSS VDD

MS31467V2

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STM32F401xD STM32F401xE Description

Figure 2. Compatible board design for LQFP64 package

^dDϯϮ&ϰϬϱͬ^dDϯϮ&ϰϭϱůŝŶĞ
PC12
PC11
STM32F4x1
PC10
PA15
PA14

PC12
PC11
PC10
PA15
PA14
53 52 51 50 49
53 52 51 50 49
48 VDD VDD 48 VDD VDD
47 VCAP2
47 VSS
46 PA13
46 PA13
45 PA12
45 PA12
44 PA11
44 PA11
43 PA10
43 PA10
42 PA9
41 PA8
VSS 42 PA9
VSS
41 PA8
40 PC9
40 PC9
39 PC8
39 PC8
38 PC7
38 PC7
37 PC6
37 PC6
36 PB15 WϭϭŶŽƚĂǀĂŝůĂďůĞĂŶLJŵŽƌĞ 36 PB15
35 PB14 ZĞƉůĂĐĞĚďLJs CAP1 35 PB14
34 PB13
34 PB13
33 PB12
28 29 30 31 32 33 PB12
28 29 30 31 32
VDD
PB2

PB11
PB10

VCAP1

VDD
PB2
PB10
VCAP1
VSS
V CAP increased to 4.7 μf
^ZϭёŽƌďĞůŽǁϭ

VSS VDD
V S S V DD

MS31468V2

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54
Description STM32F401xD STM32F401xE

Figure 3. STM32F401xD/xE block diagram

NJTRST, JTDI,
JTCK/SWCLK JTAG & SW MPU
JTDO/SWD, JTDO ETM NVIC
TRACECLK
TRACED[3:0] D-BUS
ARM Cortex-M4
84 MHz I-BUS

AHB bus-matrix 7S4M

FPU

ACCEL/
CACHE
S-BUS 512 KB
Flash

96 KB SRAM

DP

FIFO
PHY
DMA2 8 Streams AHB2 84 MHz
USB DM
FIFO
OTG FS ID, VBUS, SOF
8 Streams AHB1 84 MHz
DMA1 FIFO VDD Power managmt
Voltage VDD = 1.7 to 3.6 V
regulator (PDR OFF)
3.3 to 1.2 V
1.8 to 3.6 V
@VDDA @VDD VSS (PDR ON)
POR Supply VCAP
PA[15:0] RC HS reset
GPIO PORT A supervision
RC LS Int POR/PDR
PB[15:0] BOR VDDA, VSSA
GPIO PORT B
PLL1&2 NRST
PVD
PC[15:0] GPIO PORT C
@VDDA @VDD
PD[15:0] GPIO PORT D XTAL OSC OSC_IN
4- 16MHz OSC_OUT
PE[15:0] Reset &
GPIO PORT E WDG 32K
clock
MANAGT
control
PWR VBAT = 1.65 to 3.6 V
PH[1:0] GPIO PORT H interface
@VBAT
APB2CLK
AHB2PCLK
HCLK
APB1CLK
AHB1PCLK

OSC32_IN
XTAL 32 kHz OSC32_OUT
LS
RTC
AWU ALARM_OUT
Backup register
LS

STAMP1

CRC
TIM2 32b 4 channels, ETR as AF

TIM3 16b 4 channels, ETR as AF

DMA2 DMA1
up to 81 AF EXT IT. WKUP TIM4 16b 4 channels, ETR as AF
FIFO

D[7:0] AHB/APB2 AHB/APB1 TIM5 32b 4 channels

CMD, CK as AF
SDIO / MMC

4 compl. channels TIM1_CH1[1:4]N,

4 channels TIM1_CH1[1:4]ETR, TIM1 / PWM 16b
BKIN as AF

smcard RX, TX as AF
16b USART2 irDA CTS, RTS as AF
2 channels as AF TIM9
MOSI/SD, MISO/SD_ext, SCK/CK
1 channel as AF TIM10 16b SP2/I2S2 NSS/WS, MCK as AF
WWDG
1 channel as AF SP3/I2S3 MOSI/SD, MISO/SD_ext, SCK/CK
TIM11 16b
NSS/WS, MCK as AF
APB2 84 MHz

RX, TX, CK, smcard I2C1/SMBUS SCL, SDA, SMBA as AF

USART1
CTS, RTS as AF irDA
(max)

I2C2/SMBUS SCL, SDA, SMBA as AF

30MHz

smcard
RX, TX, CK as AF USART6
irDA
MHz

I2C3/SMBUS SCL, SDA, SMBA as AF

MOSI, MISO,
APB1

SPI1
APB2 60MHz

SCK, NSS as AF
APB1 42

MOSI, MISO, SPI4

SCK, NSS as AF

VDDREF_ADC USART 2MBps

Temperature sensor
16 analog inputs
ADC1 IF
@VDDA

MS33717V1

1. The timers connected to APB2 are clocked from TIMxCLK up to 84 MHz, while the timers connected to APB1 are clocked
from TIMxCLK up to 42 MHz.

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3 Functional overview

3.1 Arm® Cortex®-M4 with FPU core with embedded

flash memory and SRAM
The Arm® Cortex®-M4 with FPU processor is the latest generation of Arm processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
MCU implementation, with a reduced pin count and low-power consumption, while
delivering outstanding computational performance and an advanced response to interrupts.
The Arm® Cortex®-M4 with FPU 32-bit RISC processor features exceptional code-
efficiency, delivering the high-performance expected from an Arm core in the memory size
usually associated with 8- and 16-bit devices. The processor supports a set of DSP
instructions, which allow efficient signal processing and complex algorithm execution. Its
single precision FPU (floating-point unit) speeds up software development by using
metalanguage development tools, while avoiding saturation.
The STM32F401xD/xE devices are compatible with all Arm tools and software.
Figure 3 shows the general block diagram of the STM32F401xD/xE.
Note: Cortex®-M4 with FPU is binary compatible with Cortex®-M3.

3.2 Adaptive real-time memory accelerator (ART Accelerator)

The ART Accelerator is a memory accelerator, which is optimized for STM32 industry-
standard Arm® Cortex®-M4 with FPU processors. It balances the inherent performance
advantage of the Arm® Cortex®-M4 with FPU over flash memory technologies, which
normally requires the processor to wait for the flash memory at higher frequencies.
To release the processor full 105 DMIPS performance at this frequency, the accelerator
implements an instruction prefetch queue and branch cache, which increases program
execution speed from the 128-bit flash memory. Based on CoreMark benchmark, the
performance achieved thanks to the ART Accelerator is equivalent to 0 wait state program
execution from flash memory at a CPU frequency up to 84 MHz.

3.3 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to eight protected areas that can in turn be
divided up into eight subareas. The protection area sizes are between 32 bytes and the
whole 4 gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-
time operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.

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3.4 Embedded flash memory

The devices embed 512 Kbytes of flash memory available for storing programs and data,
plus 512 bytes of OTP memory organized in 16 blocks which can be independently locked.

3.5 CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the flash memory integrity. The CRC calculation unit helps compute a software
signature during runtime, to be compared with a reference signature generated at link-time
and stored at a given memory location.

3.6 Embedded SRAM

All devices embed:
• 96 Kbytes of system SRAM, which can be accessed (read/write) at CPU clock speed
with 0 wait states

3.7 Multi-AHB bus matrix

The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs) and the slaves
(flash memory, RAM, AHB and APB peripherals) and ensures a seamless and efficient
operation even when several high-speed peripherals work simultaneously.

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Figure 4. Multi-AHB matrix

ARM GP GP
Cortex-M4 DMA1 DMA2

DMA_MEM1
DMA_PI

DMA_MEM2

DMA_P2
D-bus

S-bus
I-bus

S0 S1 S2 S3 S4 S5
M0 ICODE

ACCEL
Flash
512 kB
M1 DCODE

M2 SRAM1
96 Kbytes
M3 AHB APB1
periph1
M4 AHB
periph2 APB2

Bus matrix-S

MS31490V1

3.8 DMA controller (DMA)

The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8
streams each. They are able to manage memory-to-memory, peripheral-to-memory, and
memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals,
support burst transfer and are designed to provide the maximum peripheral bandwidth
(AHB/APB).
The two DMA controllers support circular buffer management, so that no specific code is
needed when the controller reaches the end of the buffer. The two DMA controllers also
have a double buffering feature, which automates the use and switching of two memory
buffers without requiring any special code.
Each stream is connected to dedicated hardware DMA requests, with support for software
trigger on each stream. Configuration is made by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals:
• SPI and I2S
• I2C
• USART
• General-purpose, basic and advanced-control timers TIMx
• SD/SDIO/MMC host interface
• ADC

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3.9 Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller able to manage 16 priority levels,
and handle up to 62 maskable interrupt channels plus the 16 interrupt lines of the Cortex®-
M4 with FPU.
• Closely coupled NVIC gives low-latency interrupt processing
• Interrupt entry vector table address passed directly to the core
• Allows early processing of interrupts
• Processing of late arriving, higher-priority interrupts
• Support tail chaining
• Processor state automatically saved
• Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.

3.10 External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 21 edge-detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 81 GPIOs can be connected
to the 16 external interrupt lines.

3.11 Clocks and startup

On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The
16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy at 25 °C. The
application can then select as system clock either the RC oscillator or an external 4-26 MHz
clock source. This clock can be monitored for failure. If a failure is detected, the system
automatically switches back to the internal RC oscillator and a software interrupt is
generated (if enabled). This clock source is input to a PLL thus allowing to increase the
frequency up to 84 MHz. Similarly, full interrupt management of the PLL clock entry is
available when necessary (for example if an indirectly used external oscillator fails).
Several prescalers allow the configuration of the two AHB buses, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB
buses is 84 MHz while the maximum frequency of the high-speed APB domains is 84 MHz.
The maximum allowed frequency of the low-speed APB domain is 42 MHz.
The devices embed a dedicated PLL (PLLI2S), which allows to achieve audio class
performance. In this case, the I2S master clock can generate all standard sampling
frequencies from 8 kHz to 192 kHz.

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3.12 Boot modes

At startup, boot pins are used to select one out of three boot options:
• Boot from user flash memory
• Boot from system memory
• Boot from embedded SRAM
The bootloader is located in system memory. It is used to reprogram the flash memory by
using either USART1(PA9/10), USART2(PD5/6), USB OTG FS in device mode (PA11/12)
through DFU (device firmware upgrade), I2C1(PB6/7), I2C2(PB10/3), I2C3(PA8/PB4),
SPI1(PA4/5/6/7), SPI2(PB12/13/14/15) or SPI3(PA15, PC10/11/12).
For more detailed information on the bootloader, refer to Application Note: AN2606, STM32
microcontroller system memory boot mode.

3.13 Power supply schemes

• VDD = 1.7 to 3.6 V: external power supply for I/Os with the internal supervisor
(POR/PDR) disabled, provided externally through VDD pins. Requires the use of an
external power supply supervisor connected to the VDD and PDR_ON pins.
• VDD = 1.8 to 3.6 V: external power supply for I/Os and the internal regulator (when
enabled), provided externally through VDD pins.
• VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, Reset blocks, RCs,
and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively, with
decoupling technique.
• VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
Refer to Figure 18: Power supply scheme for more details.

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3.14 Power supply supervisor

3.14.1 Internal reset ON

This feature is available for VDD operating voltage range 1.8 V to 3.6 V.
The internal power supply supervisor is enabled by holding PDR_ON high.
The devices have an integrated power-on reset (POR) / power-down reset (PDR) circuitry
coupled with a brownout reset (BOR) circuitry. At power-on, POR is always active, and
ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is
reached, the option byte loading process starts, either to confirm or modify default
thresholds, or to disable BOR permanently. Three BOR thresholds are available through
option bytes.
The devices remain in reset mode when VDD is below a specified threshold, VPOR/PDR, or
VBOR, without the need for an external reset circuit.
The devices also feature an embedded programmable voltage detector (PVD) that monitors
the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be
generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.

3.14.2 Internal reset OFF

This feature is available only on packages featuring the PDR_ON pin. The internal power-on
reset (POR) / power-down reset (PDR) circuitry is disabled by setting the PDR_ON pin to
low.
An external power supply supervisor has to monitor VDD and keep the device in reset mode
as long as VDD is below a specified threshold. Connect PDR_ON to this external power
supply supervisor. Refer to Figure 5.

Figure 5. Power supply supervisor interconnection with internal reset OFF(1)

VDD

External VDD power supply supervisor

Ext. reset controller active when

VDD < 1.7 V

PDR_ON
Application reset
NRST signal (optional)

VDD

MS31383V3

1. The PRD_ON pin is only available on the WLCSP49 and UFBGA100 packages.

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The VDD specified threshold, below which the device must be maintained under reset, is
1.7 V (see Figure 6).
A comprehensive set of power-saving mode allows to design low-power applications.
When the internal reset is OFF, the following integrated features are no longer supported:
• The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled.
• The brownout reset (BOR) circuitry must be disabled.
• The embedded programmable voltage detector (PVD) is disabled.
• VBAT functionality is no more available and the VBAT pin should be connected to VDD.

Figure 6. PDR_ON control with internal reset OFF

VDD

PDR = 1.7 V

time

Reset by a source different from

power supply supervisor

NRST

PDR_ON PDR_ON

time

MS19009V8

3.15 Voltage regulator

The regulator has four operating modes:
• Regulator ON
– Main regulator mode (MR)
– Low power regulator (LPR)
– Power-down
• Regulator OFF

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3.15.1 Regulator ON
On packages embedding the BYPASS_REG pin, the regulator is enabled by holding
BYPASS_REG low. On all other packages, the regulator is always enabled.
There are three power modes configured by software when the regulator is ON:
• MR is used in the nominal regulation mode (With different voltage scaling in Run)
In Main regulator mode (MR mode), different voltage scaling are provided to reach the
best compromise between maximum frequency and dynamic power consumption.
• LPR is used in the Stop modes
The LP regulator mode is configured by software when entering Stop mode.
• Power-down is used in Standby mode.
The Power-down mode is activated only when entering in Standby mode. The regulator
output is in high impedance and the kernel circuitry is powered down, inducing zero
consumption. The contents of the registers and SRAM are lost.
Depending on the package, one or two external ceramic capacitors should be connected on
the VCAP_1 and VCAP_2 pins. The VCAP_2 pin is only available for the LQFP100 and
UFBGA100 packages.
All packages have the regulator ON feature.

3.15.2 Regulator OFF

The Regulator OFF is available only on the UFBGA100, which features the BYPASS_REG
pin. The regulator is disabled by holding BYPASS_REG high. The regulator OFF mode
allows to supply externally a V12 voltage source through VCAP_1 and VCAP_2 pins.
Since the internal voltage scaling is not managed internally, the external voltage value must
be aligned with the targeted maximum frequency. Refer to Table 14: General operating
conditions.
The two 2.2 µF VCAP ceramic capacitors should be replaced by two 100 nF decoupling
capacitors. Refer to Figure 18: Power supply scheme.
When the regulator is OFF, there is no more internal monitoring on V12. An external power
supply supervisor should be used to monitor the V12 of the logic power domain. PA0 pin
should be used for this purpose, and act as a power-on reset on the V12 power domain.
In regulator OFF mode, the following features are no more supported:
• PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic power
domain, which is not reset by the NRST pin.
• As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As
a consequence, PA0 and NRST pins must be managed separately if the debug
connection under reset or prereset is required.

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Figure 7. Regulator OFF

V12
External VCAP_1/2 power
supply supervisor Application reset
Ext. reset controller active signal (optional)
when VCAP_1/2 < Min V12

VDD
PA0 NRST
VDD

BYPASS_REG
V12

VCAP_1

VCAP_2
ai18498V3

The following conditions must be respected:

• VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection
between power domains.
• If the time for VCAP_1 and VCAP_2 to reach V12 minimum value is faster than the time for
VDD to reach 1.7 V, then PA0 should be kept low to cover both conditions: until VCAP_1
and VCAP_2 reach V12 minimum value and until VDD reaches 1.7 V (see Figure 8).
• Otherwise, if the time for VCAP_1 and VCAP_2 to reach the V12 minimum value is slower
than the time for VDD to reach 1.7 V, then PA0 could be asserted low externally (see
Figure 9).
• If VCAP_1 and VCAP_2 go below V12 minimum value and VDD is higher than 1.7 V, then a
reset must be asserted on PA0 pin.
Note: The minimum value of V12 depends on the maximum frequency targeted in the application

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Figure 8. Startup in regulator OFF: slow VDD slope -

power-down reset risen after VCAP_1/VCAP_2 stabilization

VDD

PDR = 1.7 V VCAP_1/VCAP_2

V12
Min V12

time

NRST

time
MSv31179V1

1. This figure is valid whatever the internal reset mode (ON or OFF).

Figure 9. Startup in regulator OFF mode: fast VDD slope -

power-down reset risen before VCAP_1/VCAP_2 stabilization
VDD

PDR = 1.7 V

VCAP_1/VCAP_2
V12
Min V12

time
NRST
PA0 asserted externally

time MSv31180V1

1. This figure is valid whatever the internal reset mode (ON or OFF).

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3.15.3 Regulator ON/OFF and internal power supply supervisor availability

Table 3. Regulator ON/OFF and internal power supply supervisor availability

Power supply Power supply
Package Regulator ON Regulator OFF
supervisor ON supervisor OFF

UFQFPN48 Yes No Yes No

Yes
Yes
WLCSP49 Yes No PDR_ON external
PDR_ON set to VDD
control(1)
LQFP64 Yes No Yes No
LQFP100 Yes No Yes No
Yes Yes Yes
Yes
UFBGA100 BYPASS_REG set to BYPASS_REG set to PDR_ON external
PDR_ON set to VDD
VSS VDD control (1)
1. Refer to Section 3.14: Power supply supervisor

3.16 Real-time clock (RTC) and backup registers

The backup domain includes:
• The real-time clock (RTC)
• 20 backup registers
The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain
the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binary-
coded decimal) format. Correction for 28th, 29th (leap year), 30th, and 31st day of the month
are performed automatically. The RTC features a reference clock detection, a more precise
second source clock (50 or 60 Hz) can be used to enhance the calendar precision. The RTC
provides a programmable alarm and programmable periodic interrupts with wake-up from
Stop and Standby modes. The subseconds value is also available in binary format.
It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power
RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC
has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz
output to compensate for any natural quartz deviation.
Two alarm registers are used to generate an alarm at a specific time and calendar fields can
be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit
programmable binary autoreload downcounter with programmable resolution is available
and allows automatic wake-up and periodic alarms from every 120 µs to every 36 hours.
A 20-bit prescaler is used for the time base clock. It is by default configured to generate a
time base of 1 second from a clock at 32.768 kHz.
The backup registers are 32-bit registers used to store 80 bytes of user application data
when VDD power is not present. Backup registers are not reset by a system, a power reset,
or when the device wakes up from the Standby mode (see Section 3.17).
Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes,
hours, day, and date.
The RTC and backup registers are supplied through a switch that is powered either from the
VDD supply when present or from the VBAT pin.

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3.17 Low-power modes

The devices support three low-power modes to achieve the best compromise between low
power consumption, short startup time and available wake-up sources:
• Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
• Stop mode
The Stop mode achieves the lowest power consumption while retaining the contents of
SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low-power mode.
The devices can be woken up from the Stop mode by any of the EXTI lines (the EXTI
line source can be one of the 16 external lines, the PVD output, the RTC alarm/ wake-
up/ tamper/ time stamp events).
• Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.2 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, the SRAM and register contents are lost except for registers in the
backup domain when selected.
The devices exit the Standby mode when an external reset (NRST pin), an IWDG reset,
a rising edge on the WKUP pin, or an RTC alarm/ wake-up/ tamper/time stamp event
occurs.
Standby mode is not supported when the embedded voltage regulator is bypassed and
the 1.2 V domain is controlled by an external power.

3.18 VBAT operation

The VBAT pin allows to power the device VBAT domain from an external battery, an external
super-capacitor, or from VDD when no external battery and an external super-capacitor are
present.
VBAT operation is activated when VDD is not present.
The VBAT pin supplies the RTC and the backup registers.
Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events
do not exit it from VBAT operation. When PDR_ON pin is not connected to VDD (internal
Reset OFF), the VBAT functionality is no more available and VBAT pin should be connected
to VDD.

3.19 Timers and watchdogs

The devices embed one advanced-control timer, seven general-purpose timers, and two
watchdog timers.
All timer counters can be frozen in debug mode.
Table 4 compares the features of the advanced-control and general-purpose timers.

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Table 4. Timer feature comparison

Max. Max.
DMA Capture/
Timer Counter Counter Prescaler Complemen- interface timer
Timer request compare
type resolution type factor tary output clock clock
generation channels
(MHz) (MHz)

Any
Up, integer
Advanced
TIM1 16-bit Down, between 1 Yes 4 Yes 84 84
-control
Up/down and
65536
Any
Up, integer
TIM2,
32-bit Down, between 1 Yes 4 No 42 84
TIM5
Up/down and
65536
Any
Up, integer
TIM3,
16-bit Down, between 1 Yes 4 No 42 84
TIM4
Up/down and
General 65536
purpose Any
integer
TIM9 16-bit Up between 1 No 2 No 84 84
and
65536
Any
integer
TIM10,
16-bit Up between 1 No 1 No 84 84
TIM11
and
65536

3.19.1 Advanced-control timers (TIM1)

The advanced-control timer (TIM1) can be seen as three-phase PWM generators
multiplexed on four independent channels. It has complementary PWM outputs with
programmable inserted dead times. It can also be considered as a complete general-
purpose timer. Its four independent channels can be used for:
• Input capture
• Output compare
• PWM generation (edge- or center-aligned modes)
• One-pulse mode output
If configured as a standard 16-bit timers, it has the same features as the general-purpose
TIMx timers. If configured as a 16-bit PWM generator, it has full modulation capability
(0-100%).
The advanced-control timer can work together with the TIMx timers via the Timer Link
feature for synchronization or event chaining.
TIM1 supports independent DMA request generation.

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3.19.2 General-purpose timers (TIMx)

There are seven synchronizable general-purpose timers embedded in the
STM32F401xD/xE (see Table 4 for differences).
• TIM2, TIM3, TIM4, TIM5
The STM32F401xD/xE devices are 4 full-featured general-purpose timers: TIM2, TIM5,
TIM3, and TIM4.The TIM2 and TIM5 timers are based on a 32-bit autoreload
up/downcounter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16-
bit autoreload up/downcounter and a 16-bit prescaler. They all feature four independent
channels for input capture/output compare, PWM or one-pulse mode output. This gives
up to 15 input capture/output compare/PWMs.
The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the
other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the
timer Link feature for synchronization or event chaining.
Any of these general-purpose timers can be used to generate PWM outputs.
TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are
capable of handling quadrature (incremental) encoder signals and the digital outputs
from 1 to 4 hall-effect sensors.
• TIM9, TIM10, and TIM11
These timers are based on a 16-bit autoreload upcounter and a 16-bit prescaler. TIM10
and TIM11 feature one independent channel, whereas TIM9 has two independent
channels for input capture/output compare, PWM or one-pulse mode output. They can
be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers.
They can also be used as simple time bases.

3.19.3 Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes.

3.19.4 Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.

3.19.5 SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard
downcounter. It features:
• A 24-bit downcounter
• Auto reload capability
• Maskable system interrupt generation when the counter reaches 0
• Programmable clock source.

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3.20 Inter-integrated circuit interface (I2C)

Up to three I2C bus interfaces can operate in multicontroller and target modes. They can
support the standard (up to 100 kHz) and fast (up to 400 kHz) modes. The I2C bus
frequency can be increased up to 1 MHz. For more details about the complete solution,
please contact your local ST sales representative. They also support the 7/10-bit addressing
mode and the 7-bit dual addressing mode (as target). A hardware CRC
generation/verification is embedded.
They can be served by DMA and they support SMBus 2.0/PMBus.
The devices also include programmable analog and digital noise filters (see Table 5).

Table 5. Comparison of I2C analog and digital filters

- Analog filter Digital filter

Pulse width of
≥ 50 ns Programmable length from 1 to 15 I2C peripheral clocks
suppressed spikes

3.21 Universal synchronous/asynchronous receiver transmitters

(USART)
The devices embed three universal synchronous/asynchronous receiver transmitters
(USART1, USART2, and USART6).
These three interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN Master/Slave capability. The USART1 and USART6 interfaces are able to
communicate at speeds of up to 10.5 Mbit/s. The USART2 interface communicates at up to
5.25 bit/s.
USART1 and USART2 also provide hardware management of the CTS and RTS signals,
smartcard mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces
can be served by the DMA controller.

Table 6. USART feature comparison

Max. baud Max. baud
USART Standard Modem SPI Smartcard rate in Mbit/s rate in Mbit/s APB
LIN irDA
name features (RTS/CTS) master (ISO 7816) (oversampling (oversampling mapping
by 16) by 8)

APB2
USART1 X X X X X X 5.25 10.5 (max.
84 MHz)
APB1
USART2 X X X X X X 2.62 5.25 (max.
42 MHz)
APB2
USART6 X N.A X X X X 5.25 10.5 (max.
84 MHz)

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3.22 Serial peripheral interface (SPI)

The devices feature up to four SPIs in slave and master modes in full-duplex and simplex
communication modes. SPI1 and SPI4 can communicate at up to 42 Mbit/s, SPI2 and SPI3
can communicate at up to 21 Mbit/s. The 3-bit prescaler gives 8 master mode frequencies
and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification
supports basic SD Card/MMC modes. All SPIs can be served by the DMA controller.
The SPI interface can be configured to operate in TI mode for communications in master
mode and slave mode.

3.23 Inter-integrated sound (I2S)

can be operated in master or slave mode, in full duplex and simplex communication modes
and can be configured to operate with a 16-/32-bit resolution as an input or output channel.
Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of
the I2S interfaces is/are configured in master mode, the master clock can be output to the
external DAC/CODEC at 256 times the sampling frequency.
All I2Sx can be served by the DMA controller.

3.24 Audio PLL (PLLI2S)

The devices feature an additional dedicated PLL for audio I2S application, making it
possible to achieve error-free I2S sampling clock accuracy without compromising on the
CPU performance.
The PLLI2S configuration can be modified to manage an I2S sample rate change without
disabling the main PLL (PLL) used for the CPU.
The audio PLL can be programmed with very low error to obtain sampling rates ranging
from 8 kHz to 192 kHz.
In addition to the audio PLL, a master clock input pin can be used to synchronize the I2S
flow with an external PLL (or Codec output).

3.25 Secure digital input/output interface (SDIO)

An SD/SDIO/MMC host interface is available that supports MultiMediaCard System
Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.
The interface allows data transfer at up to 48 MHz, and is compliant with the SD memory
card specification version 2.0.
The SDIO Card Specification Version 2.0 is also supported with two different databus
modes: 1-bit (default) and 4-bit.
The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack
of MMC4.1 or previous.
In addition to SD/SDIO/MMC, this interface is fully compliant with the CE-ATA digital
protocol Rev1.1.

30/138 DS10086 Rev 4

STM32F401xD STM32F401xE Functional overview

3.26 Universal serial bus on-the-go full-speed (OTG_FS)

The devices embed a USB OTG full-speed device/host/OTG peripheral with integrated
transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and
with the OTG 1.0 specification. It has software-configurable endpoint setting and supports
suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock
that is generated by a PLL connected to the HSE oscillator. The major features are:
• Combined Rx and Tx FIFO size of 320 × 35 bits with dynamic FIFO sizing
• Supports the session request protocol (SRP) and host negotiation protocol (HNP)
• 4 bidirectional endpoints
• 8 host channels with periodic OUT support
• HNP/SNP/IP inside (no need for any external resistor)
• For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected

3.27 General-purpose input/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)
or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. All GPIOs are high-current-capable and have speed selection to better
manage internal noise, power consumption and electromagnetic emission.
The I/O configuration can be locked if needed by following a specific sequence to avoid
spurious writing to the I/Os registers.
Fast I/O handling allowing maximum I/O toggling up to 84 MHz.

3.28 Analog-to-digital converter (ADC)

One 12-bit analog-to-digital converter is embedded and shares up to 16 external channels,
performing conversions in the single-shot or scan mode. In scan mode, automatic
conversion is performed on a selected group of analog inputs.
The ADC can be served by the DMA controller. An analog watchdog feature allows very
precise monitoring of the converted voltage of one, some or all selected channels. An
interrupt is generated when the converted voltage is outside the programmed thresholds.
To synchronize A/D conversion and timers, the ADCs could be triggered by any of the TIM1,
TIM2, TIM3, TIM4, or TIM5 timer.

3.29 Temperature sensor

The temperature sensor has to generate a voltage that varies linearly with temperature. The
conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally
connected to the ADC_IN16 input channel, which is used to convert the sensor output
voltage into a digital value. Refer to the reference manual for additional information.

DS10086 Rev 4 31/138

54
Functional overview STM32F401xD STM32F401xE

As the offset of the temperature sensor varies from chip to chip due to process variation, the
internal temperature sensor is mainly suitable for applications that detect temperature
changes instead of absolute temperatures. If an accurate temperature reading is needed,
then an external temperature sensor part should be used.

3.30 Serial wire JTAG debug port (SWJ-DP)

The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using 2 pins only instead of the five reuse as GPIO with the alternate
function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively,
and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

3.31 Embedded Trace Macrocell™

The Arm Embedded Trace Macrocell provides a greater visibility of the instruction and data
flow inside the CPU core by streaming compressed data at a very high rate from the
STM32F401xD/xE through a small number of ETM pins to an external hardware trace port
analyzer (TPA) device. The TPA is connected to a host computer using any high-speed
channel available. Real-time instruction and data flow activity can be recorded and then
formatted for display on the host computer that runs the debugger software. TPA hardware
is commercially available from common development tool vendors.
The Embedded Trace Macrocell operates with third party debugger software tools.

32/138 DS10086 Rev 4

STM32F401xD STM32F401xE Pinouts and pin description

4 Pinouts and pin description

Figure 10. STM32F401xD/xE WLCSP49 pinout

      

$ 3$ 3$ 3% 3% %227 966 9''

3'5
% 966 9'' 3$ 3% 3% 9%$7
B21

3& 3&
& 3$ 3$ 3$ 3% 3%
26&B287 26&B,1

' 3+ 3+

3$ 3$ 966 3% 3&
26&B287 26&B,1

966$
( 3% 3% 3% 3$ 3$
95()
1567

) 3$ 3$ 3$ 9''$

3% 9'' 3$
95()

* 3% 9&$3 3% 3% 3% 3$ 3$

B

069

1. The above figure shows the package top view.

DS10086 Rev 4 33/138

54
Pinouts and pin description STM32F401xD STM32F401xE

Figure 11. STM32F401xD/xE UFQFPN48 pinout

BOOT0

PA15

PA14
VDD

VSS

PB7

PB6

PB5

PB4

PB3
PB9

PB8
48 47 46 45 44 43 42 41 40 39 38 37
VBAT 1 36 VDD

PC13 2 35 VSS

PC14-OSC32_IN 3 34 PA13

PC15-OSC32_OUT 4 33 PA12

PH0-OSC_IN 5 32 PA11

PH1-OSC_OUT 6 31 PA10
UFQFPN48
NRST 7 30 PA9

VSSA/VREF- 8 29 PA8

VDDA/VREF+ 9 28 PB15

PA0 10 27 PB14

PA1 11 26 PB13

PA2 12 25 PB12
13 14 15 16 17 18 19 20 21 22 23 24
PA3

PA4

PA5

PA6

PA7

VSS
PB0

PB1

PB2

PB10

VDD
VCAP_1
MS31150V5

1. The above figure shows the package top view.

34/138 DS10086 Rev 4

STM32F401xD STM32F401xE Pinouts and pin description

Figure 12. STM32F401xD/xE LQFP64 pinout

BOOT0

PC12

PC10
PC11

PA15
PA14
VDD
VSS

PD2
PB9
PB8

PB7
PB6
PB5
PB4
PB3
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VBAT 1 48 VDD
PC13 2 47 VSS
PC14-OSC32_IN 3 46 PA13
PC15-OSC32_OUT 4 45 PA12
PH0-OSC_IN 5 44 PA11
PH1-OSC_OUT 6 43 PA10
NRST 7 42 PA9
PC0 8 41 PA8
LQFP64
PC1 9 40 PC9
PC2 10 39 PC8
PC3 11 38 PC7
VSSA/VREF- 12 37 PC6
VDDA/VREF+ 13 36 PB15
PA0 14 35 PB14
PA1 15 34 PB13
PA2 16 33 PB12
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VSS
VDD

PC4
PC5
PB0
PB1
PB2
PB10
VCAP_1
VSS
VDD
PA3

PA4
PA5
PA6
PA7

MS31149V3

1. The above figure shows the package top view.

DS10086 Rev 4 35/138

54
Pinouts and pin description STM32F401xD STM32F401xE

Figure 13. STM32F401xD/xE LQFP100 pinout

BOOT0

PC12

PC10
PC11

PA15
PA14
VDD
VSS

PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PE1
PE0
PB9
PB8

PB7
PB6
PB5
PB4
PB3
100
99

97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
98
PE2 1 75 VDD
PE3 2 74 VSS
PE4 3 73 VCAP_2
PE5 4 72 PA13
PE6 5 71 PA12
VBAT 6 70 PA11
PC13 7 69 PA10
PC14-OSC32_IN 8 68 PA9
PC15-OSC32_OUT 9 67 PA8
VSS 10 66 PC9
VDD 11 65 PC8
PH0-OSC_IN 12 64 PC7
PH1-OSC_OUT 13 LQFP100 63 PC6
NRST 14 62 PD15
PC0 15 61 PD14
PC1 16 60 PD13
PC2 17 59 PD12
PC3 18 58 PD11
VDD 19 57 PD10
VSSA/VREF- 20 56 PD9
VREF+ 21 55 PD8
VDDA 22 54 PB15
PA0 23 53 PB14
PA1 24 52 PB13
PA2 25 51 PB12
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50 VDD
PA3

PA4
PA5
PA6
PA7
PC4
PC5

PE10

PE12
PE13
PE14
PE15
PB10
VCAP_1
PB0
PB1
PB2
PE7
PE8
PE9
VSS
VDD

PE11

VSS MS31151V4

1. The above figure shows the package top view.

36/138 DS10086 Rev 4

STM32F401xD STM32F401xE Pinouts and pin description

Figure 14. STM32F401xD/xE UFBGA100 pinout

           

3( 3( 3% %227 3' 3' 3% 3% 3$ 3$ 3$ 3$
$

% 3( 3( 3% 3% 3% 3' 3' 3' 3' 3& 3& 3$

& 9&$3
3& 3( 3( 9'' 3% 3' 3' 3& 3$
B
$17,B7$03

' 3&
3( 966 3$ 3$ 3&
26&B,1

( 3& 9%$7 %<3$66B5(* 3& 3& 3&

26&B287

) 3+ 966 966 966

26&B,1

* 3+ 9'' 9'' 9''

26&B287

+ 3& 1567 3'5B21 3' 3' 3'

- 966$ 3& 3& 3' 3' 3'

. 95() 3& 3$ 3$ 3& 3' 3% 3% 3% 3%

3$ 3% 9&$3 3%

/ 95() 3$ 3$ 3& 3( 3( 3( 3%
B
:.83

9''$ 3$ 3$ 3$ 3% 3% 3( 3( 3( 3( 3( 3(
0

069
1. This figure shows the package top view

DS10086 Rev 4 37/138

54
Pinouts and pin description STM32F401xD STM32F401xE

Table 7. Legend/abbreviations used in the pinout table

Name Abbreviation Definition

Unless otherwise specified in brackets below the pin name, the pin function during and after
Pin name
reset is the same as the actual pin name
S Supply pin
Pin type I Input only pin
I/O Input/ output pin
FT 5 V tolerant I/O
B Dedicated BOOT0 pin
I/O structure
NRST Bidirectional reset pin with embedded weak pull-up resistor

Notes Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset

Alternate
Functions selected through GPIOx_AFR registers
functions

Additional
Functions directly selected/enabled through peripheral registers
functions

Table 8. STM32F401xD/xE pin definitions

Pin Number
I/O structure
Pin type

Pin name
UFBGA100

Notes

Additional
WLCSP49

LQFP100
UQFN48

LQFP64

(function Alternate functions

functions
after reset)(1)

SPI4_SCK, TRACECLK,
- - - 1 B2 PE2 I/O FT - -
EVENTOUT

- - - 2 A1 PE3 I/O FT - TRACED0, EVENTOUT -

SPI4_NSS, TRACED1,
- - - 3 B1 PE4 I/O FT - -
EVENTOUT
SPI4_MISO, TIM9_CH1,
- - - 4 C2 PE5 I/O FT - -
TRACED2, EVENTOUT
SPI4_MOSI, TIM9_CH2,
- - - 5 D2 PE6 I/O FT - -
TRACED3, EVENTOUT

- - - - D3 VSS S - - - -

- - - - C4 VDD S - - - -

1 B7 1 6 E2 VBAT S - - - -

RTC_TAMP1,
2 D5 2 7 C1 PC13 I/O FT (2) (3) EVENTOUT,
RTC_OUT, RTC_TS

38/138 DS10086 Rev 4

STM32F401xD STM32F401xE Pinouts and pin description

Table 8. STM32F401xD/xE pin definitions (continued)

Pin Number

I/O structure
Pin type
Pin name

UFBGA100

Notes
Additional
WLCSP49

LQFP100
UQFN48

LQFP64

(function Alternate functions

functions
after reset)(1)

PC14- (2) (3)

3 C7 3 8 D1 OSC32_IN I/O FT (4) EVENTOUT OSC32_IN
(PC14)
PC15- (2) (3)
4 C6 4 9 E1 OSC32_OUT I/O FT (4) EVENTOUT OSC32_OUT
(PC15)

- - - 10 F2 VSS S - - - -

- - - 11 G2 VDD S - - - -

PH0-OSC_IN (4)
5 D7 5 12 F1 I/O FT EVENTOUT OSC_IN
(PH0)
PH1-
(4)
6 D6 6 13 G1 OSC_OUT I/O FT EVENTOUT OSC_OUT
(PH1)

7 E7 7 14 H2 NRST I/O FT - EVENTOUT -

- - 8 15 H1 PC0 I/O FT - EVENTOUT ADC1_IN10

- - 9 16 J2 PC1 I/O FT - EVENTOUT ADC1_IN11

SPI2_MISO, I2S2ext_SD,
- - 10 17 J3 PC2 I/O FT - ADC1_IN12
EVENTOUT
SPI2_MOSI/I2S2_SD,
- - 11 18 K2 PC3 I/O FT - ADC1_IN13
EVENTOUT

- - - 19 - VDD S - - - -

8 E6 12 20 - VSSA/VREF- S - - - -

- - - - J1 VSSA S - - - -

- - - - K1 VREF- S - - - -

9 - 13 - - VDDA/VREF+ S - - - -

- - - 21 L1 VREF+ S - - - -

- F7 - 22 M1 VDDA S - - - -

USART2_CTS,
(5)
10 F6 14 23 L2 PA0 I/O FT TIM2_CH1/TIM2_ETR, ADC1_IN0, WKUP
TIM5_CH1, EVENTOUT
USART2_RTS, TIM2_CH2,
11 G7 15 24 M2 PA1 I/O FT - ADC1_IN1
TIM5_CH2, EVENTOUT
USART2_TX, TIM2_CH3,
12 E5 16 25 K3 PA2 I/O FT - TIM5_CH3, TIM9_CH1, ADC1_IN2
EVENTOUT

DS10086 Rev 4 39/138

54
Pinouts and pin description STM32F401xD STM32F401xE

Table 8. STM32F401xD/xE pin definitions (continued)

Pin Number

I/O structure
Pin type
Pin name

UFBGA100

Notes
Additional
WLCSP49

LQFP100
UQFN48

LQFP64

(function Alternate functions

functions
after reset)(1)

USART2_RX, TIM2_CH4,
13 E4 17 26 L3 PA3 I/O FT - TIM5_CH4, TIM9_CH2, ADC1_IN3
EVENTOUT

- - 18 27 - VSS S - - - -

- - 19 28 - VDD S - - - -

BYPASS_
- - - - E3 I FT - - -
REG
SPI1_NSS,
14 G6 20 29 M3 PA4 I/O FT - SPI3_NSS/I2S3_WS, ADC1_IN4
USART2_CK, EVENTOUT
SPI1_SCK,
15 F5 21 30 K4 PA5 I/O FT - TIM2_CH1/TIM2_ETR, ADC1_IN5
EVENTOUT
SPI1_MISO, TIM1_BKIN,
16 F4 22 31 L4 PA6 I/O FT - ADC1_IN6
TIM3_CH1, EVENTOUT
SPI1_MOSI, TIM1_CH1N,
17 F3 23 32 M4 PA7 I/O FT - ADC1_IN7
TIM3_CH2, EVENTOUT

- - 24 33 K5 PC4 I/O FT - EVENTOUT ADC1_IN14

- - 25 34 L5 PC5 I/O FT - EVENTOUT ADC1_IN15

TIM1_CH2N, TIM3_CH3,
18 G5 26 35 M5 PB0 I/O FT - ADC1_IN8
EVENTOUT
TIM1_CH3N, TIM3_CH4,
19 G4 27 36 M6 PB1 I/O FT - ADC1_IN9
EVENTOUT

20 G3 28 37 L6 PB2 I/O FT - EVENTOUT BOOT1

- - - 38 M7 PE7 I/O FT - TIM1_ETR, EVENTOUT -

- - - 39 L7 PE8 I/O FT - TIM1_CH1N, EVENTOUT -

- - - 40 M8 PE9 I/O FT - TIM1_CH1, EVENTOUT -

- - - 41 L8 PE10 I/O FT - TIM1_CH2N, EVENTOUT -

SPI4_NSS, TIM1_CH2,
- - - 42 M9 PE11 I/O FT - -
EVENTOUT
SPI4_SCK, TIM1_CH3N,
- - - 43 L9 PE12 I/O FT - -
EVENTOUT
SPI4_MISO, TIM1_CH3,
- - - 44 M10 PE13 I/O FT - -
EVENTOUT

40/138 DS10086 Rev 4

STM32F401xD STM32F401xE Pinouts and pin description

Table 8. STM32F401xD/xE pin definitions (continued)

Pin Number

I/O structure
Pin type
Pin name

UFBGA100

Notes
Additional
WLCSP49

LQFP100
UQFN48

LQFP64

(function Alternate functions

functions
after reset)(1)

SPI4_MOSI, TIM1_CH4,
- - - 45 M11 PE14 I/O FT - -
EVENTOUT

- - - 46 M12 PE15 I/O FT - TIM1_BKIN, EVENTOUT -

SPI2_SCK/I2S2_CK,
21 E3 29 47 L10 PB10 I/O FT - I2C2_SCL, TIM2_CH3, -
EVENTOUT
TIM2_CH4, I2C2_SDA,
- - - - K9 PB11 I/O FT - -
EVENTOUT

22 G2 30 48 L11 VCAP_1 S - - - -

23 D3 31 49 F12 VSS S - - - -

24 F2 32 50 G12 VDD S - - - -

SPI2_NSS/I2S2_WS,
25 E2 33 51 L12 PB12 I/O FT - I2C2_SMBA, TIM1_BKIN, -
EVENTOUT
SPI2_SCK/I2S2_CK,
26 G1 34 52 K12 PB13 I/O FT - -
TIM1_CH1N, EVENTOUT
SPI2_MISO, I2S2ext_SD,
27 F1 35 53 K11 PB14 I/O FT - -
TIM1_CH2N, EVENTOUT
SPI2_MOSI/I2S2_SD,
28 E1 36 54 K10 PB15 I/O FT - RTC_REFIN
TIM1_CH3N, EVENTOUT

- - - 55 - PD8 I/O FT - EVENTOUT -

- - - 56 K8 PD9 I/O FT - EVENTOUT -

- - - 57 J12 PD10 I/O FT - EVENTOUT -

- - - 58 J11 PD11 I/O FT - EVENTOUT -

- - - 59 J10 PD12 I/O FT - TIM4_CH1, EVENTOUT -

- - - 60 H12 PD13 I/O FT - TIM4_CH2, EVENTOUT -

- - - 61 H11 PD14 I/O FT - TIM4_CH3, EVENTOUT -

- - - 62 H10 PD15 I/O FT - TIM4_CH4, EVENTOUT -

I2S2_MCK, USART6_TX,
- - 37 63 E12 PC6 I/O FT - TIM3_CH1, SDIO_D6, -
EVENTOUT
I2S3_MCK, USART6_RX,
- - 38 64 E11 PC7 I/O FT - TIM3_CH2, SDIO_D7, -
EVENTOUT

DS10086 Rev 4 41/138

54
Pinouts and pin description STM32F401xD STM32F401xE

Table 8. STM32F401xD/xE pin definitions (continued)

Pin Number

I/O structure
Pin type
Pin name

UFBGA100

Notes
Additional
WLCSP49

LQFP100
UQFN48

LQFP64

(function Alternate functions

functions
after reset)(1)

USART6_CK, TIM3_CH3,
- - 39 65 E10 PC8 I/O FT - -
SDIO_D0, EVENTOUT
I2S_CKIN, I2C3_SDA,
- - 40 66 D12 PC9 I/O FT - TIM3_CH4, SDIO_D1, -
MCO_2, EVENTOUT
I2C3_SCL, USART1_CK,
29 D1 41 67 D11 PA8 I/O FT - TIM1_CH1, OTG_FS_SOF, -
MCO_1, EVENTOUT
I2C3_SMBA, USART1_TX,
30 D2 42 68 D10 PA9 I/O FT - OTG_FS_VBUS
TIM1_CH2, EVENTOUT
USART1_RX, TIM1_CH3,
31 C2 43 69 C12 PA10 I/O FT - -
OTG_FS_ID, EVENTOUT
USART1_CTS, USART6_TX,
32 C1 44 70 B12 PA11 I/O FT - TIM1_CH4, OTG_FS_DM, -
EVENTOUT
USART1_RTS, USART6_RX,
33 C3 45 71 A12 PA12 I/O FT - TIM1_ETR, OTG_FS_DP, -
EVENTOUT
PA13 (JTMS-
34 B3 46 72 A11 I/O FT - JTMS-SWDIO, EVENTOUT -
SWDIO)

- - - 73 C11 VCAP_2 S - - - -

35 B1 47 74 F11 VSS S - - - -

36 - 48 75 G11 VDD S - - - -

- B2 - - - VDD S - - - -

PA14 (JTCK-
37 A1 49 76 A10 I/O FT - JTCK-SWCLK, EVENTOUT -
SWCLK)
JTDI, SPI1_NSS,
SPI3_NSS/I2S3_WS,
38 A2 50 77 A9 PA15 (JTDI) I/O FT - -
TIM2_CH1/TIM2_ETR, JTDI,
EVENTOUT
SPI3_SCK/I2S3_CK,
- - 51 78 B11 PC10 I/O FT - -
SDIO_D2, EVENTOUT
I2S3ext_SD, SPI3_MISO,
- - 52 79 C10 PC11 I/O FT - -
SDIO_D3, EVENTOUT
SPI3_MOSI/I2S3_SD,
- - 53 80 B10 PC12 I/O FT - -
SDIO_CK, EVENTOUT

- - - 81 C9 PD0 I/O FT - EVENTOUT -

42/138 DS10086 Rev 4

STM32F401xD STM32F401xE Pinouts and pin description

Table 8. STM32F401xD/xE pin definitions (continued)

Pin Number

I/O structure
Pin type
Pin name

UFBGA100

Notes
Additional
WLCSP49

LQFP100
UQFN48

LQFP64

(function Alternate functions

functions
after reset)(1)

- - - 82 B9 PD1 I/O FT - EVENTOUT -

TIM3_ETR, SDIO_CMD,
- - 54 83 C8 PD2 I/O FT - -
EVENTOUT
SPI2_SCK/I2S2_CK,
- - - 84 B8 PD3 I/O FT - -
USART2_CTS, EVENTOUT

- - - 85 B7 PD4 I/O FT - USART2_RTS, EVENTOUT -

- - - 86 A6 PD5 I/O FT - USART2_TX, EVENTOUT -

SPI3_MOSI/I2S3_SD,
- - - 87 B6 PD6 I/O FT - -
USART2_RX, EVENTOUT

- - - 88 A5 PD7 I/O FT - USART2_CK, EVENTOUT -

JTDO-SWO, SPI1_SCK,
PB3 SPI3_SCK/I2S3_CK,
39 A3 55 89 A8 I/O FT - -
(JTDO-SWO) I2C2_SDA, TIM2_CH2,
EVENTOUT
NJTRST, SPI1_MISO,
PB4 SPI3_MISO, I2S3ext_SD,
40 A4 56 90 A7 I/O FT - -
(NJTRST) I2C3_SDA, TIM3_CH1,
EVENTOUT
SPI1_MOSI,
SPI3_MOSI/I2S3_SD,
41 B4 57 91 C5 PB5 I/O FT - -
I2C1_SMBA, TIM3_CH2,
EVENTOUT
I2C1_SCL, USART1_TX,
42 C4 58 92 B5 PB6 I/O FT - -
TIM4_CH1, EVENTOUT
I2C1_SDA, USART1_RX,
43 D4 59 93 B4 PB7 I/O FT - -
TIM4_CH2, EVENTOUT

44 A5 60 94 A4 BOOT0 I B - - VPP

I2C1_SCL, TIM4_CH3,
45 B5 61 95 A3 PB8 I/O FT - TIM10_CH1, SDIO_D4, -
EVENTOUT
SPI2_NSS/I2S2_WS,
I2C1_SDA, TIM4_CH4,
46 C5 62 96 B3 PB9 I/O FT - -
TIM11_CH1, SDIO_D5,
EVENTOUT

- - - 97 C3 PE0 I/O FT - TIM4_ETR, EVENTOUT -

- - - 98 A2 PE1 I/O FT - EVENTOUT -

DS10086 Rev 4 43/138

54
Pinouts and pin description STM32F401xD STM32F401xE

Table 8. STM32F401xD/xE pin definitions (continued)

Pin Number

I/O structure
Pin type
Pin name

UFBGA100

Notes
Additional
WLCSP49

LQFP100
UQFN48

LQFP64

(function Alternate functions

functions
after reset)(1)

47 A6 63 99 - VSS S - - - -

- B6 - - H3 PDR_ON I FT - - -

48 A7 64 100 - VDD S - - - -

1. Function availability depends on the chosen device.

2. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3
mA), the use of GPIOs PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF.
- These I/Os must not be used as a current source (e.g. to drive an LED).
3. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after
reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC
register description sections in the STM32F401xx reference manual.
4. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1).
5. If the device is delivered in an UFBGA100 and the BYPASS_REG pin is set to VDD (Regulator off/internal reset ON mode),
then PA0 is used as an internal Reset (active low)

44/138 DS10086 Rev 4

 STM32F401xD STM32F401xE
Table 9. Alternate function mapping
AF00 AF01 AF02 AF03 AF04 AF05 AF06 AF07 AF08 AF09 AF10 AF11 AF12 AF13 AF14 AF15

Port TIM9/ SPI1/SPI2/ SPI3/I2S3/

TIM3/ I2C1/I2C2/ SPI2/I2S2/ I2C2/
SYS_AF TIM1/TIM2 TIM10/ I2S2/SPI3/ USART1/ USART6 OTG1_FS SDIO
TIM4/ TIM5 I2C3 SPI3/ I2S3 I2C3
TIM11 I2S3/SPI4 USART2

TIM2_CH1/ USART2_ EVENT

PA0 - TIM5_CH1 - - - - - - - - - - -
TIM2_ETR CTS OUT

USART2_ EVENT
PA1 - TIM2_CH2 TIM5_CH2 - - - - - - - - - - -
RTS OUT

USART2_ EVENT
PA2 - TIM2_CH3 TIM5_CH3 TIM9_CH1 - - - - - - - - - -
TX OUT

USART2_ EVENT
PA3 - TIM2_CH4 TIM5_CH4 TIM9_CH2 - - - - - - - - -
RX OUT

SPI3_NSS/ USART2_ EVENT

PA4 - - - - - SPI1_NSS - - - - - - -
I2S3_WS CK OUT

TIM2_CH1/ EVENT
PA5 - - - - SPI1_SCK - - - - - - - - -
DS10086 Rev 4

TIM2_ETR OUT

SPI1_ EVENT
PA6 - TIM1_BKIN TIM3_CH1 - - - - - - - - - - -
MISO OUT

SPI1_ - - - EVENT
PA7 - TIM1_CH1N TIM3_CH2 - - - - - - - -
MOSI OUT
Port A

USART1_ OTG_FS_ - - - EVENT

PA8 MCO_1 TIM1_CH1 - - I2C3_SCL - - - - -
CK SOF OUT

I2C3_ USART1_ OTG_FS_ EVENT

PA9 - TIM1_CH2 - - - - - - - - -- -
SMBA TX VBUS OUT

USART1_ OTG_FS_I EVENT

PA10 - TIM1_CH3 - - - - - - - - - - -
RX D OUT

Pinouts and pin description

USART1_ USART6_ OTG_FS_ EVENT
PA11 - TIM1_CH4 - - - - - - - - - -
CTS TX DM OUT

USART1_ USART6_ OTG_FS_ EVENT

PA12 - TIM1_ETR - - - - - - - - - -
RTS RX DP OUT

JTMS_ EVENT
PA13 - - - - - - - - - - - - - -
SWDIO OUT

JTCK_ EVENT
PA14 - - - - - - - - - - - - - -
SWCLK OUT

TIM2_CH1/ SPI3_NSS/ EVENT

PA15 JTDI - - - SPI1_NSS - - - - - - - -
TIM2_ETR I2S3_WS OUT
45/138
 Table 9. Alternate function mapping (continued)

Pinouts and pin description

46/138
AF00 AF01 AF02 AF03 AF04 AF05 AF06 AF07 AF08 AF09 AF10 AF11 AF12 AF13 AF14 AF15

Port TIM9/ SPI1/SPI2/ SPI3/I2S3/

TIM3/ I2C1/I2C2/ SPI2/I2S2/ I2C2/
SYS_AF TIM1/TIM2 TIM10/ I2S2/SPI3/ USART1/ USART6 OTG1_FS SDIO
TIM4/ TIM5 I2C3 SPI3/ I2S3 I2C3
TIM11 I2S3/SPI4 USART2

EVENT
PB0 - TIM1_CH2N TIM3_CH3 - - - - - - - - - - - -
OUT

EVENT
PB1 - TIM1_CH3N TIM3_CH4 - - - - - - - - - - - -
OUT

EVENT
PB2 - - - - - - - - - - - - - - -
OUT

JTDO- SPI3_SCK/ EVENT

PB3 TIM2_CH2 - - - SPI1_SCK - - I2C2_SDA - - - - -
SWO I2S3_CK OUT

SPI1_ I2S3ext_S EVENT

PB4 JTRST - TIM3_CH1 - - SPI3_MISO - I2C3_SDA - - - - -
MISO D OUT

I2C1_ SPI1 SPI3_MOSI/ EVENT

PB5 - - TIM3_CH2 - - - - - - - - -
SMBA _MOSI I2S3_SD OUT
DS10086 Rev 4

USART1_ EVENT
PB6 - - TIM4_CH1 - I2C1_SCL - - - - - - - - -
TX OUT

USART1_ EVENT
PB7 - - TIM4_CH2 - I2C1_SDA - - - - - - - - -
RX OUT
Port B

SDIO_ EVENT
PB8 - - TIM4_CH3 TIM10_CH1 I2C1_SCL - - - - - - - - -
D4 OUT

SPI2_NSS/I SDIO_ EVENT

PB9 - - TIM4_CH4 TIM11_CH1 I2C1_SDA - - - - - - - -
2S2_WS D5 OUT

SPI2_SCK/I EVENT
PB10 - TIM2_CH3 - - I2C2_SCL - - - - - - - - -
2S2_CK OUT

EVENT

STM32F401xD STM32F401xE
PB11 - TIM2_CH4 - - I2C2_SDA - - - - - - - - - -
OUT

I2C2_ SPI2_NSS/I EVENT

PB12 - TIM1_BKIN - - - - - - - - - - -
SMBA 2S2_WS OUT

SPI2_SCK/I EVENT
PB13 - TIM1_CH1N - - - - - - - - - - - -
2S2_CK OUT

EVENT
PB14 - TIM1_CH2N - - - SPI2_MISO I2S2ext_SD - - - - - - - -
OUT

RTC_ SPI2_MOSI EVENT

PB15 TIM1_CH3N - - - - - - - - - - - -
REFN /I2S2_SD OUT
 Table 9. Alternate function mapping (continued)

STM32F401xD STM32F401xE
AF00 AF01 AF02 AF03 AF04 AF05 AF06 AF07 AF08 AF09 AF10 AF11 AF12 AF13 AF14 AF15

Port TIM9/ SPI1/SPI2/ SPI3/I2S3/

TIM3/ I2C1/I2C2/ SPI2/I2S2/ I2C2/
SYS_AF TIM1/TIM2 TIM10/ I2S2/SPI3/ USART1/ USART6 OTG1_FS SDIO
TIM4/ TIM5 I2C3 SPI3/ I2S3 I2C3
TIM11 I2S3/SPI4 USART2

EVENT
PC0 - - - - - - - - - - - - - - -
OUT

EVENT
PC1 - - - - - - - - - - - - - - -
OUT

SPI2_ EVENT
PC2 - - - - - I2S2ext_SD - - - - - - - -
MISO OUT

SPI2_MOSI EVENT
PC3 - - - - - - - - - - - - - -
/I2S2_SD OUT

EVENT
PC4 - - - - - - - - - - - - - - -
OUT

EVENT
PC5 - - - - - - - - - - - - - - -
OUT
DS10086 Rev 4

USART6_ SDIO_ EVENT

PC6 - -- TIM3_CH1 - - I2S2_MCK - - - - - - -
TX D6 OUT

USART6_ SDIO_ EVENT

PC7 - TIM3_CH2 - - - I2S3_MCK - - - - - -
RX D7 OUT
Port C

USART6_ SDIO_ EVENT

PC8 - - TIM3_CH3 - - - - - - - - - -
CK D0 OUT

SDIO_ EVENT
PC9 MCO_2 - TIM3_CH4 - I2C3_SDA I2S_CKIN - - - - - - - -
D1 OUT

SPI3_SCK/ SDIO_ EVENT

PC10 - - - - - - - - - - - - -
I2S3_CK D2 OUT

I2S3ext_ SDIO_ EVENT

PC11 - - - - - SPI3_MISO - - - - - - -

Pinouts and pin description

SD D3 OUT

SPI3_MOSI/ SDIO_ EVENT

PC12 - - - - - - - - - - - - -
I2S3_SD CK OUT

EVENT
PC13 - - - - - - - - - - - - - - -
OUT

EVENT
PC14 - - - - - - - - - - - - - - -
OUT

EVENT
PC15 - - - - - - - - - - - - - - -
OUT
47/138
 Table 9. Alternate function mapping (continued)

Pinouts and pin description

48/138
AF00 AF01 AF02 AF03 AF04 AF05 AF06 AF07 AF08 AF09 AF10 AF11 AF12 AF13 AF14 AF15

Port TIM9/ SPI1/SPI2/ SPI3/I2S3/

TIM3/ I2C1/I2C2/ SPI2/I2S2/ I2C2/
SYS_AF TIM1/TIM2 TIM10/ I2S2/SPI3/ USART1/ USART6 OTG1_FS SDIO
TIM4/ TIM5 I2C3 SPI3/ I2S3 I2C3
TIM11 I2S3/SPI4 USART2

EVENT
PD0 - - - - - - - - - - - - - - -
OUT

EVENT
PD1 - - - - - - - - - - - - - - -
OUT

SDIO_ EVENT
PD2 - - TIM3_ETR - - - - - - - - - - -
CMD OUT

SPI2_SCK/ USART2_ EVENT

PD3 - - - - - - -- - - - - - -
I2S2_CK CTS OUT

USART2_ EVENT
PD4 - - - - - - - - - - - - -
RTS OUT

USART2_ EVENT
PD5 - - - - - - - - - - - - - -
TX OUT
DS10086 Rev 4

SPI3_MOSI USART2_ EVENT

PD6 - - - - - - - - - - - - -
/I2S3_SD RX OUT

USART2_ EVENT
PD7 - - - - - - - - - - - - - -
CK OUT
Port D

EVENT
PD8 - - - - - - - - - - - - - - -
OUT

EVENT
PD9 - - - - - - - - - - - - - - -
OUT

EVENT
PD10 - - - - - - - - - - - - - - -
OUT

EVENT

STM32F401xD STM32F401xE
PD11 - - - - - - - - - - - - - - -
OUT

EVENT
PD12 - - TIM4_CH1 - - - - - - - - - - - -
OUT

EVENT
PD13 - - TIM4_CH2 - - - - - - - - - - - -
OUT

EVENT
PD14 - - TIM4_CH3 - - - - - - - - - - - -
OUT

EVENT
PD15 - - TIM4_CH4 - - - - - - - - - - - -
OUT
 Table 9. Alternate function mapping (continued)

STM32F401xD STM32F401xE
AF00 AF01 AF02 AF03 AF04 AF05 AF06 AF07 AF08 AF09 AF10 AF11 AF12 AF13 AF14 AF15

Port TIM9/ SPI1/SPI2/ SPI3/I2S3/

TIM3/ I2C1/I2C2/ SPI2/I2S2/ I2C2/
SYS_AF TIM1/TIM2 TIM10/ I2S2/SPI3/ USART1/ USART6 OTG1_FS SDIO
TIM4/ TIM5 I2C3 SPI3/ I2S3 I2C3
TIM11 I2S3/SPI4 USART2

EVENT
PE0 - - TIM4_ETR - - - - - - - - - - - -
OUT

EVENT
PE1 - TIM1_CH2N - - - - - - - - - - - - -
OUT

TRACECL EVENT
PE2 - - - - SPI4_SCK - - - - - - - - -
K OUT

EVENT
PE3 TRACED0 - - - - - - - - - - - - - -
OUT

EVENT
PE4 TRACED1 - - - - SPI4_NSS - - - - - - - - -
OUT

EVENT
PE5 TRACED2 - - TIM9_CH1 - SPI4_MISO - - - - - - - - -
OUT
DS10086 Rev 4

EVENT
PE6 TRACED3 - - TIM9_CH2 - SPI4_MOSI - - - - - - - - -
OUT

EVENT
PE7 - TIM1_ETR - - - - - - - - - - - - -
OUT
Port E

EVENT
PE8 - TIM1_CH1N - - - - - - - - - - - - -
OUT

EVENT
PE9 - TIM1_CH1 - - - - - - - - - - - - -
OUT

EVENT
PE10 - TIM1_CH2N - - - - - - - - - - - - -
OUT

EVENT
PE11 - TIM1_CH2 - - - SPI4_NSS - - - - - - - - -

Pinouts and pin description

OUT

EVENT
PE12 - TIM1_CH3N - - - SPI4_SCK - - - - - - - - -
OUT

EVENT
PE13 - TIM1_CH3 - - - SPI4_MISO - - - - - - - - -
OUT

EVENT
PE14 - TIM1_CH4 - - - SPI4_MOSI - - - - - - - - -
OUT

EVENT
PE15 - TIM1_BKIN - - - - - - - - - - - - -
OUT
49/138
 Table 9. Alternate function mapping (continued)

Pinouts and pin description

50/138
AF00 AF01 AF02 AF03 AF04 AF05 AF06 AF07 AF08 AF09 AF10 AF11 AF12 AF13 AF14 AF15

Port TIM9/ SPI1/SPI2/ SPI3/I2S3/

TIM3/ I2C1/I2C2/ SPI2/I2S2/ I2C2/
SYS_AF TIM1/TIM2 TIM10/ I2S2/SPI3/ USART1/ USART6 OTG1_FS SDIO
TIM4/ TIM5 I2C3 SPI3/ I2S3 I2C3
TIM11 I2S3/SPI4 USART2

EVENT
PH0 - - - - - - - - - - - - - - -
OUT
Port H

EVENT
PH1 - - - - - - - - - - - - - - -
OUT
DS10086 Rev 4

STM32F401xD STM32F401xE
STM32F401xD STM32F401xE Memory mapping

5 Memory mapping

The memory map is shown in Figure 15.

Figure 15. Memory map

Reserved 0xE010 0000 - 0xFFFF FFFF

Cortex-M4 internal
peripherals 0xE000 0000 - 0xE00F FFFF
0xDFFF FFFF

Reserved

0x5004 0000
0x5003 FFFF
AHB2

0x5000 0000
Reserved 0x4002 6800 - 0x4FFF FFFF
0x4002 67FF

0xFFFF FFFF 512-Mbyte

block 7
Cortex-M4's
internal AHB1
0xE000 0000 peripherals
0xDFFF FFFF
512-Mbyte
block 6
Not used
0xC000 0000
0x4002 0000
0xBFFF FFFF
Reserved 0x4001 4C00 - 0x4001 FFFF
0x4001 4BFF

Reserved

0x6000 0000
0x5FFF FFFF
512-Mbyte APB2
block 2
Peripherals
0x4000 0000
0x3FFF FFFF
512-Mbyte
block 1
SRAM Reserved 0x2001 8000 - 0x3FFF FFFF
0x4001 0000
0x2000 0000 SRAM (96 KB aliased
by bit-banding) 0x2000 0000 - 0x2001 7FFF Reserved 0x4000 7400 - 0x4000 FFFF
0x1FFF FFFF
0x4000 73FF
512-Mbyte Reserved 0x1FFF C008 - 0x1FFF FFFF
block 0 Option bytes 0x1FFF C000 - 0x1FFF C007
Code
Reserved 0x1FFF 7A10 - 0x1FFF BFFF
0x0000 0000
System memory 0x1FFF 0000 - 0x1FFF 7A0F
Reserved 0x0808 0000 - 0x1FFE FFFF
Flash memory 0x0800 0000 - 0x0807 FFFF
Reserved 0x0008 0000 - 0x07FF FFFF APB1
Aliased to Flash, system
memory or SRAM depending
0x0000 0000 - 0x0007 FFFF
on the BOOT pins

0x4000 0000

MS31970V1

DS10086 Rev 4 51/138

54
Memory mapping STM32F401xD STM32F401xE

Table 10. STM32F401xD/xE

register boundary addresses
Bus Boundary address Peripheral

0xE010 0000 - 0xFFFF FFFF Reserved

®
Cortex -M4 0xE000 0000 - 0xE00F FFFF Cortex-M4 internal peripherals
0x5004 0000 - 0xDFFF FFFF Reserved
AHB2 0x5000 0000 - 0x5003 FFFF USB OTG FS
0x4002 6800 - 0x4FFF FFFF Reserved
0x4002 6400 - 0x4002 67FF DMA2
0x4002 6000 - 0x4002 63FF DMA1
0x4002 5000 - 0x4002 4FFF Reserved
0x4002 3C00 - 0x4002 3FFF Flash interface register
0x4002 3800 - 0x4002 3BFF RCC
0x4002 3400 - 0x4002 37FF Reserved
0x4002 3000 - 0x4002 33FF CRC
AHB1
0x4002 2000 - 0x4002 2FFF Reserved
0x4002 1C00 - 0x4002 1FFF GPIOH
0x4002 1400 - 0x4002 1BFF Reserved
0x4002 1000 - 0x4002 13FF GPIOE
0x4002 0C00 - 0x4002 0FFF GPIOD
0x4002 0800 - 0x4002 0BFF GPIOC
0x4002 0400 - 0x4002 07FF GPIOB
0x4002 0000 - 0x4002 03FF GPIOA

52/138 DS10086 Rev 4

STM32F401xD STM32F401xE Memory mapping

Table 10. STM32F401xD/xE

register boundary addresses (continued)
Bus Boundary address Peripheral

0x4001 4C00- 0x4001 FFFF Reserved

0x4001 4800 - 0x4001 4BFF TIM11
0x4001 4400 - 0x4001 47FF TIM10
0x4001 4000 - 0x4001 43FF TIM9
0x4001 3C00 - 0x4001 3FFF EXTI
0x4001 3800 - 0x4001 3BFF SYSCFG
0x4001 3400 - 0x4001 37FF SPI4/I2S4
0x4001 3000 - 0x4001 33FF SPI1
0x4001 2C00 - 0x4001 2FFF SDIO
APB2 0x4001 2400 - 0x4001 2BFF Reserved
0x4001 2000 - 0x4001 23FF ADC1
0x4001 1800 - 0x4001 1FFF Reserved
0x4001 1400 - 0x4001 17FF USART6
0x4001 1000 - 0x4001 13FF USART1
0x4001 0800 - 0x4001 0FFF Reserved
0x4001 0400 - 0x4001 07FF TIM8
0x4001 0000 - 0x4001 03FF TIM1
0x4000 7400 - 0x4000 FFFF Reserved

DS10086 Rev 4 53/138

54
Memory mapping STM32F401xD STM32F401xE

Table 10. STM32F401xD/xE

register boundary addresses (continued)
Bus Boundary address Peripheral

0x4000 7000 - 0x4000 73FF PWR

0x4000 6000 - 0x4000 6FFF Reserved
0x4000 5C00 - 0x4000 5FFF I2C3
0x4000 5800 - 0x4000 5BFF I2C2
0x4000 5400 - 0x4000 57FF I2C1
0x4000 4800 - 0x4000 53FF Reserved
0x4000 4400 - 0x4000 47FF USART2
0x4000 4000 - 0x4000 43FF I2S3ext
0x4000 3C00 - 0x4000 3FFF SPI3 / I2S3
APB1 0x4000 3800 - 0x4000 3BFF SPI2 / I2S2
0x4000 3400 - 0x4000 37FF I2S2ext
0x4000 3000 - 0x4000 33FF IWDG
0x4000 2C00 - 0x4000 2FFF WWDG
0x4000 2800 - 0x4000 2BFF RTC & BKP Registers
0x4000 1000 - 0x4000 27FF Reserved
0x4000 0C00 - 0x4000 0FFF TIM5
0x4000 0800 - 0x4000 0BFF TIM4
0x4000 0400 - 0x4000 07FF TIM3
0x4000 0000 - 0x4000 03FF TIM2

54/138 DS10086 Rev 4

STM32F401xD STM32F401xE Electrical characteristics

6 Electrical characteristics

6.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

6.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3 σ).

6.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the
1.7 V ≤VDD ≤3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ±2 σ).

6.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.

6.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 16.

Figure 16. Pin loading conditions

MCU pin

C = 50 pF

MS19011V2

DS10086 Rev 4 55/138

115
Electrical characteristics STM32F401xD STM32F401xE

6.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 17.

Figure 17. Input voltage measurement

MCU pin

VIN

MS19010V2

56/138 DS10086 Rev 4

STM32F401xD STM32F401xE Electrical characteristics

6.1.6 Power supply scheme

Figure 18. Power supply scheme

VBAT
Backup circuitry
VBAT = Power (OSC32K,RTC,
1.65 to 3.6V switch Wakeup logic
Backup registers)

Level shifter
OUT
IO
GPIOs
Logic
IN
VCAP_1 Kernel logic
VCAP_2 (CPU, digital
& RAM)
2 × 2.2 μF or 1 × 4.7 μF VDD
VDD
1/2/...4/ 5 Voltage
6 × 100 nF VSS regulator
+ 1 × 4.7 μF 1/2/...4 / 5

BYPASS_REG Flash memory

Reset
PDR_ON controller
VDD
VDDA

VREF VREF+
Analog:
100 nF 100 nF VREF- ADC RCs,
+ 1 μF + 1 μF PLL,..
VSSA

MS31488V2

1. To connect PDR_ON pin, refer to Section 3.14: Power supply supervisor.

2. The 4.7 µF ceramic capacitor must be connected to one of the VDD pin.
3. VCAP_2 pad is only available on LQFP100 and UFBGA100 packages.
4. VDDA=VDD and VSSA=VSS.
Caution: Each power supply pair (VDD/VSS, VDDA/VSSA ...) must be decoupled with filtering ceramic
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure good operation of the
device. It is not recommended to remove filtering capacitors to reduce PCB size or cost.
This might cause incorrect operation of the device.

DS10086 Rev 4 57/138

115
Electrical characteristics STM32F401xD STM32F401xE

6.1.7 Current consumption measurement

Figure 19. Current consumption measurement scheme

IDD_VBAT
VBAT

IDD
VDD

VDDA

ai14126

6.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 11: Voltage characteristics,
Table 12: Current characteristics, and Table 13: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability. Device mission profile (application conditions)
is compliant with JEDEC JESD47 Qualification Standard. Extended mission profiles are
available on demand.

Table 11. Voltage characteristics

Symbol Ratings Min Max Unit

External main supply voltage (including VDDA, VDD and

VDD–VSS –0.3 4.0
VBAT)(1)
Min(Min(
VDD,
Input voltage on FT pins(3) VSS–0.3 VDDA)+ V
3.6 V,
VIN(2)
5.5 V)
Input voltage on any other pin VSS–0.3 4.0
Input voltage for BOOT0 VSS 9.0
|ΔVDDx| Variations between different VDD power pins - 50
Variations between all the different ground pins mV
|VSSX −VSS| - 50
including VREF-
VESD(HBM) Electrostatic discharge voltage (human body model) see Section 6.3.14 -
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. When a FT_a pin is used by an analog peripheral such as ADC, the maximum VIN is 4 V.
3. VIN maximum value must always be respected. Refer to Table 12 for the values of the maximum allowed
injected current.

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STM32F401xD STM32F401xE Electrical characteristics

Table 12. Current characteristics

Symbol Ratings Max. Unit

ΣIVDD Total current into sum of all VDD_x power lines (source)(1) 160
(1)
Σ IVSS Total current out of sum of all VSS_x ground lines (sink) -160
(1)
IVDD Maximum current into each VDD_x power line (source) 100
IVSS Maximum current out of each VSS_x ground line (sink)(1) -100
Output current sunk by any I/O and control pin 25
IIO
Output current sourced by any I/O and control pin -25 mA
(2)
Total output current sunk by sum of all I/O and control pins 120
ΣIIO
Total output current sourced by sum of all I/Os and control pins(2) -120
(4)
Injected current on FT pins
IINJ(PIN) (3) –5/+0
Injected current on NRST and B pins (4)
ΣIINJ(PIN) Total injected current (sum of all I/O and control pins)(5) ±25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages.
3. Negative injection disturbs the analog performance of the device. See note in Section 6.3.20: 12-bit ADC characteristics.
4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum
value.
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and
negative injected currents (instantaneous values).

Table 13. Thermal characteristics

Symbol Ratings Value Unit

TSTG Storage temperature range –65 to +150

TJ Maximum junction temperature 125
°C
Maximum lead temperature during soldering (1)
TLEAD See note
(WLCSP49, LQFP64/100, UFQFPN48, UFBGA100)
1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb assembly), the ST ECOPACK
7191395 specification, and the European directive on Restrictions on Hazardous Substances (ROHS
directive 2011/65/EU, July 2011).

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6.3 Operating conditions

6.3.1 General operating conditions

Table 14. General operating conditions

Symbol Parameter Conditions Min Typ Max Unit

Power Scale3: Regulator ON,

0 - 60
VOS[1:0] bits in PWR_CR register = 0x01
fHCLK Internal AHB clock frequency
Power Scale2: Regulator ON,
0 - 84 MHz
VOS[1:0] bits in PWR_CR register = 0x10
fPCLK1 Internal APB1 clock frequency - 0 - 42
fPCLK2 Internal APB2 clock frequency - 0 - 84
VDD Standard operating voltage - 1.7(1) - 3.6 V
Analog operating voltage
1.7(1) - 2.4
VDDA (ADC limited to 1.2 M samples)
(2)(3) Must be the same potential as VDD(4) V
Analog operating voltage
2.4 - 3.6
(ADC limited to 2.4 M samples)
VBAT Backup operating voltage - 1.65 - 3.6 V
VOS[1:0] bits in PWR_CR register = 0x01
1.08(5) 1.14 1.20(5)
Regulator ON: 1.2 V internal Max frequency 60 MHz
V12 V
voltage on VCAP_1/VCAP_2 pins VOS[1:0] bits in PWR_CR register = 0x10
1.20(5) 1.26 1.32(5)
Max frequency 84 MHz
Regulator OFF: 1.2 V external Max. frequency 60 MHz. 1.1 1.14 1.2
V12 voltage must be supplied on V
VCAP_1/VCAP_2 pins Max. frequency 84 MHz. 1.2 1.26 1.32

Input voltage on RST and FT 2 V ≤ VDD ≤ 3.6 V –0.3 - 5.5

VIN pins(6) VDD ≤ 2 V –0.3 - 5.2 V
Input voltage on BOOT0 pin - 0 - 9
UFQFPN48 - - 625
WLCSP49 - - 392
Maximum allowed package
PD power dissipation for suffix 6 LQFP64 - - 313 mW
and 7(7)
LQFP100 - - 465
UFBGA100 - - 323

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Table 14. General operating conditions (continued)

Symbol Parameter Conditions Min Typ Max Unit

Ambient temperature for 6 Maximum power dissipation –40 - 85

suffix version Low power dissipation(8) –40 - 105
TA
Ambient temperature for 7 Maximum power dissipation –40 - 105
°C
suffix version Low power dissipation (8)
–40 - 125
6 suffix version –40 - 105
TJ Junction temperature range
7 suffix version –40 - 125
1. VDD/VDDA minimum value of 1.7 V with the use of an external power supply supervisor (refer to Section 3.14.2: Internal
reset OFF).
2. When the ADC is used, refer to Table 66: ADC characteristics.
3. If VREF+ pin is present, it must respect the following condition: VDDA-VREF+ < 1.2 V.
4. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and
VDDA can be tolerated during power-up and power-down operation.
5. Evaluated by test in production
6. To sustain a voltage higher than VDD+0.3, the internal Pull-up and Pull-Down resistors must be disabled
7. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax.
8. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax.

Table 15. Features depending on the operating power supply range

Maximum Flash Maximum
Operating memory access Flash memory Possible
Clock output
power ADC frequency access Flash
I/O operation frequency on
supply operation without wait frequency memory
I/O pins(3)
range states with wait states operations
(1)(2)
(fFlashmax)

8-bit erase
VDD =1.7 to 84 MHz with and program
20 MHz(5)
2.1 V(4) Conversion 4 wait states operations
No I/O only
time up to Up to 30 MHz
compensation
1.2 Msps 16-bit erase
VDD = 2.1 to 84 MHz with
22 MHz and program
2.4 V 3 wait states
operations
16-bit erase
VDD = 2.4 to 84 MHz with
24 MHz Up to 48 MHz and program
2.7 V 3 wait states
operations
Conversion I/O – Up to 84 MHz
time up to compensation when VDD =
2.4 Msps works 32-bit erase
VDD = 2.7 to 84 MHz with 3.0 to 3.6 V
30 MHz and program
3.6 V(6) 2 wait states – Up to 48 MHz operations
when VDD =
2.7 to 3.0 V
1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is
required.
2. Thanks to the ART accelerator and the 128-bit Flash memory, the number of wait states given here does not impact the
execution speed from Flash memory since the ART accelerator allows to achieve a performance equivalent to 0 wait state
program execution.

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3. Refer to for frequencies vs. external load.

4. VDD/VDDA minimum value of 1.7 V, with the use of an external power supply supervisor (refer to Section 3.14.2: Internal
reset OFF).
5. Prefetch is not available. Refer to AN3430 application note for details on how to adjust performance and power.
6. The voltage range for the USB full speed embedded PHY can drop down to 2.7 V. However the electrical characteristics of
D- and D+ pins will be degraded between 2.7 and 3 V.

6.3.2 VCAP_1/VCAP_2 external capacitors

Stabilization for the main regulator is achieved by connecting external capacitor CEXT to the
VCAP_1 and VCAP_2 pin. For packages supporting only 1 VCAP pin, the 2 CEXT
capacitors are replaced by a single capacitor.
CEXT is specified in Table 16.

Figure 20. External capacitor CEXT

ESR

R Leak
MS19044V2

1. Legend: ESR is the equivalent series resistance.

Table 16. VCAP_1/VCAP_2 operating conditions(1)

Symbol Parameter Conditions

Capacitance of external capacitor with available

CEXT 2.2 µF
VCAP_1 and VCAP_2 pins
ESR of external capacitor with available VCAP_1 and
ESR <2Ω
VCAP_2 pins
1. When bypassing the voltage regulator, the two 2.2 µF VCAP capacitors are not required and should be
replaced by two 100 nF decoupling capacitors.

6.3.3 Operating conditions at power-up / power-down (regulator ON)

Subject to general operating conditions for TA.

Table 17. Operating conditions at power-up / power-down (regulator ON)

Symbol Parameter Min Max Unit

VDD rise time rate 20 ∞

tVDD µs/V
VDD fall time rate 20 ∞

6.3.4 Operating conditions at power-up / power-down (regulator OFF)

Subject to general operating conditions for TA.

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Table 18. Operating conditions at power-up / power-down (regulator OFF)(1)

Symbol Parameter Conditions Min Max Unit

VDD rise time rate Power-up 20 ∞

tVDD
VDD fall time rate Power-down 20 ∞
µs/V
VCAP_1 and VCAP_2 rise time rate Power-up 20 ∞
tVCAP
VCAP_1 and VCAP_2 fall time rate Power-down 20 ∞
1. To reset the internal logic at power-down, a reset must be applied on pin PA0 when VDD reach below
1.08 V.

Note: This feature is only available for UFBGA100 package.

6.3.5 Embedded reset and power control block characteristics

The parameters given in Table 19 are derived from tests performed under ambient
temperature and VDD supply voltage @ 3.3V.

Table 19. Embedded reset and power control block characteristics

Symbol Parameter Conditions Min Typ Max Unit

PLS[2:0]=000 (rising edge) 2.09 2.14 2.19

PLS[2:0]=000 (falling edge) 1.98 2.04 2.08
PLS[2:0]=001 (rising edge) 2.23 2.30 2.37
PLS[2:0]=001 (falling edge) 2.13 2.19 2.25
PLS[2:0]=010 (rising edge) 2.39 2.45 2.51
PLS[2:0]=010 (falling edge) 2.29 2.35 2.39
PLS[2:0]=011 (rising edge) 2.54 2.60 2.65

Programmable voltage PLS[2:0]=011 (falling edge) 2.44 2.51 2.56

VPVD V
detector level selection PLS[2:0]=100 (rising edge) 2.70 2.76 2.82
PLS[2:0]=100 (falling edge) 2.59 2.66 2.71
PLS[2:0]=101 (rising edge) 2.86 2.93 2.99
PLS[2:0]=101 (falling edge) 2.75 2.84 2.92
PLS[2:0]=110 (rising edge) 2.96 3.03 3.10
PLS[2:0]=110 (falling edge) 2.85 2.93 2.99
PLS[2:0]=111 (rising edge) 3.07 3.14 3.21
PLS[2:0]=111 (falling edge) 2.95 3.03 3.09
(2)
VPVDhyst PVD hysteresis - - 100 - mV
(1)
Power-on/power-down Falling edge 1.60 1.68 1.76
VPOR/PDR V
reset threshold Rising edge 1.64 1.72 1.80
VPDRhyst(2) PDR hysteresis - - 40 - mV

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Table 19. Embedded reset and power control block characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit

Brownout level 1 Falling edge 2.13 2.19 2.24

VBOR1
threshold Rising edge 2.23 2.29 2.33

Brownout level 2 Falling edge 2.44 2.50 2.56

VBOR2 V
threshold Rising edge 2.53 2.59 2.63

Brownout level 3 Falling edge 2.75 2.83 2.88

VBOR3
threshold Rising edge 2.85 2.92 2.97
(2)
VBORhyst BOR hysteresis - - 100 - mV
TRSTTEMPO
(2)(3) POR reset timing - 0.5 1.5 3.0 ms

InRush current on
(2) voltage regulator power-
IRUSH - - 160 200 mA
on (POR or wake-up
from Standby)
InRush energy on
(2) voltage regulator power- VDD = 1.7 V, TA = 105 °C,
ERUSH - - 5.4 µC
on (POR or wake-up IRUSH = 171 mA for 31 µs
from Standby)
1. The product behavior is specified by design down to the minimum VPOR/PDR value.
2. Specified by design.
3. The reset timing is measured from the power-on (POR reset or wake-up from VBAT) to the instant when first
instruction is fetched by the user application code.

6.3.6 Supply current characteristics

The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 19: Current consumption
measurement scheme.
All the run-mode current consumption measurements given in this section are performed
with a reduced code that gives a consumption equivalent to CoreMark® code.

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Typical and maximum current consumption

The MCU is placed under the following conditions:
• All I/O pins are in input mode with a static value at VDD or VSS (no load).
• All peripherals are disabled except if it is explicitly mentioned.
• The Flash memory access time is adjusted to both fHCLK frequency and VDD ranges
(refer to Table 15: Features depending on the operating power supply range).
• The voltage scaling is adjusted to fHCLK frequency as follows:
– Scale 3 for fHCLK ≤ 60 MHz
– Scale 2 for 60 MHz < fHCLK ≤ 84 MHz
• The system clock is HCLK, fPCLK1 = fHCLK/2, and fPCLK2 = fHCLK.
• External clock is 4 MHz and PLL is on
• The maximum values are obtained for VDD = 3.6 V and a maximum ambient
temperature (TA), and the typical values for TA= 25 °C and VDD = 3.3 V unless
otherwise specified.

Table 20. Typical and maximum current consumption, code with data processing (ART
accelerator disabled) running from SRAM - VDD = 1.7 V
Typ Max(1)
fHCLK
Symbol Parameter Conditions Unit
(MHz) TA=
TA= 25 °C TA=85 °C TA=105 °C
25 °C

84 21.8 23.1 24.1 25.3(4)

External clock, 60 15.8 16.5 17.5 18.7
all peripherals
enabled(2)(3) 40 11.4 11.9 12.9 13.9

Supply current 20 6.0 6.3 7.3 8.3

IDD mA
in Run mode 84 12.7 13.5 14.5 16.3(4)
External clock, 60 9.2 10.5 11.5 12.8
all peripherals
40 6.7 7.1 8.1 9.1
disabled(3)
20 3.6 3.8 4.8 5.8
1. Evaluated by characterization, unless otherwise specified
2. When analog peripheral blocks such as ADC, HSE, LSE, HSI, or LSI are ON, an additional power consumption has to be
considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA for the
analog part.
4. Tested in production.

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Table 21. Typical and maximum current consumption, code with data processing (ART
accelerator disabled) running from SRAM
Max(1)
fHCLK
Symbol Parameter Conditions Typ Unit
(MHz)
TA= 25 °C TA=85 °C TA=105 °C

84 22.0 23.1 24.1 25.3

External clock, 60 16.0 16.9 17.9 19.8
all peripherals
enabled(2)(3) 40 11.6 12.1 13.1 14.1

Supply current 20 6.2 6.5 7.5 8.5

IDD mA
in Run mode 84 12.9 14.0 15.0 16.3
External clock,
60 9.5 10.5 11.5 12.8
all peripherals
disabled(3) 40 6.9 7.3 8.3 9.3
20 3.8 4.0 5.0 6.0
1. Evaluated by characterization, unless otherwise specified.
2. When analog peripheral blocks such as ADC, HSE, LSE, HSI, or LSI are ON, an additional power consumption has to be
considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA for the
analog part.

Table 22. Typical and maximum current consumption in run mode, code with data processing
(ART accelerator enabled except prefetch) running from Flash memory- VDD = 1.7 V
Max(1)
fHCLK
Symbol Parameter Conditions Typ Unit
(MHz) TA = TA = TA =
25 °C 85 °C 105 °C

84 23.2 24.5 25.6 26.6

60 15.1 16.3 17.4 18.4
External clock,
40 10.8 12.1 13.2 14.2
all peripherals enabled(2)(3)
30 8.8 10.0 11.1 12.2

Supply current 20 6.9 8.0 9.0 10.1

IDD mA
in Run mode 84 12.3 13.6 14.7 15.7
60 8.2 9.4 10.5 11.5
External clock,
40 6.0 7.3 8.3 9.4
all peripherals disabled(3)
30 4.9 6.2 7.2 8.3
20 4.0 5.1 6.1 7.2
1. Evaluated by characterization, unless otherwise specified.
2. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only
while the ADC is ON (ADON bit is set in the ADC_CR2 register).
3. When the ADC is ON (ADON bit set in the ADC_CR2), add an additional power consumption of 1.6mA per ADC for the
analog part.

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Table 23. Typical and maximum current consumption in run mode, code with data processing
(ART accelerator enabled except prefetch) running from Flash memory - VDD = 3.3 V
Max(1)
fHCLK
Symbol Parameter Conditions Typ Unit
(MHz) TA = TA = TA =
25 °C 85 °C 105 °C

84 23.4 24.7 25.8 26.8

60 15.3 16.5 17.6 18.6
External clock,
40 11.0 12.3 13.4 14.4
all peripherals enabled(2)(3)
30 9.0 10.2 11.3 12.4

Supply current 20 7.1 8.2 9.2 10.3

IDD mA
in Run mode 84 12.5 13.8 14.9 15.9
60 8.4 9.6 10.7 11.7
External clock,
40 6.2 7.5 8.5 9.6
all peripherals disabled(3)
30 5.1 6.4 7.4 8.5
20 4.2 5.3 6.3 7.4
1. Evaluated by characterization, unless otherwise specified.
2. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only
while the ADC is ON (ADON bit is set in the ADC_CR2 register).
3. When the ADC is ON (ADON bit set in the ADC_CR2), add an additional power consumption of 1.6mA per ADC for the
analog part.

.
Table 24. Typical and maximum current consumption in run mode, code with data processing
(ART accelerator disabled) running from Flash memory
Max(1)
fHCLK
Symbol Parameter Conditions Typ Unit
(MHz) TA = TA = TA =
25 °C 85 °C 105 °C

84 31.1 32.2 34.3 36.3

60 21.7 22.1 23.2 24.2
External clock,
40 15.5 16.1 17.1 18.1
all peripherals enabled(2)(3)
30 12.6 13.1 14.1 15.1

Supply current 20 9.8 10.1 11.1 12.1

IDD mA
in Run mode 84 20.2 21.3 23.4 25.4
60 14.9 15.3 16.3 17.3
External clock,
40 10.6 11.2 12.2 13.3
all peripherals disabled(3)
30 8.8 9.2 10.2 11.2
20 6.9 7.2 8.2 9.2
1. Evaluated by characterization, unless otherwise specified.
2. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only
while the ADC is ON (ADON bit is set in the ADC_CR2 register).

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3. When the ADC is ON (ADON bit set in the ADC_CR2), add an additional power consumption of 1.6mA per ADC for the
analog part.

Table 25. Typical and maximum current consumption in run mode, code with data processing
(ART accelerator enabled with prefetch) running from Flash memory
Max(1)
fHCLK
Symbol Parameter Conditions Typ Unit
(MHz) TA = TA = TA =
25 °C 85 °C 105 °C

84 32.5 33.3 34.3 35.4

60 22.2 23.3 24.3 25.3
External clock,
40 16.0 17.1 18.1 19.2
all peripherals enabled(2)(3)
30 12.9 14.1 15.1 16.1

Supply current 20 10.2 11.1 12.1 13.1

IDD mA
in Run mode 84 21.6 22.4 23.5 24.5
60 15.3 16.4 17.4 18.4
External clock,
40 11.2 12.3 13.3 14.3
all peripherals disabled(3)
30 9.0 10.2 11.2 12.3
20 7.3 8.2 9.2 10.2
1. Evaluated by characterization, unless otherwise specified.
2. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only
while the ADC is ON (ADON bit is set in the ADC_CR2 register).
3. When the ADC is ON (ADON bit set in the ADC_CR2), add an additional power consumption of 1.6mA per ADC for the
analog part.

Table 26. Typical and maximum current consumption in Sleep mode

Max(1)
fHCLK
Symbol Parameter Conditions Typ Unit
(MHz) TA = TA = TA =
25 °C 85 °C 105 °C

84 16.6 17.4 18.4 19.5

60 10.8 11.2 12.3 13.3
External clock,
40 8.3 9.0 10.0 11.0
all peripherals enabled(2)(3)
30 6.8 7.1 8.1 9.1

Supply current 20 5.9 6.1 7.1 8.1

IDD mA
in Sleep mode 84 5.3 6.1 7.1 8.2
60 3.7 4.1 5.1 6.1
External clock,
40 2.9 3.1 4.1 5.1
all peripherals disabled(3)(4)
30 2.7 3.1 4.1 5.1
20 2.7 3.1 4.1 5.1

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1. Evaluated by characterization, unless otherwise specified.

2. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only
while the ADC is ON (ADON bit is set in the ADC_CR2 register).
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA for the
analog part.
4. Same current consumption for fHCLK at 30 MHz and 20 MHz due to VCO running slower at 30 MHz.

Table 27. Typical and maximum current consumptions in Stop mode - VDD=1.8 V
Typ Max(1)

Symbol Parameter Conditions TA = TA = Unit

TA = TA =
85 ° 105 °
25 °C 25 °C
C C

Main regulator usage Flash in Stop mode, all 109 135 440 650
oscillators OFF, no
Low power regulator usage independent watchdog 41 65 310 530(2)
IDD_STO
Main regulator usage Flash in Deep power 72 95 345 530 µA
P
down mode, all
Low power regulator usage 12 36 260 510(2)
oscillators OFF, no
Low power low voltage regulator usage independent watchdog 10 27 230 460
1. Evaluated by characterization.
2. Evaluated by test in production.

Table 28. Typical and maximum current consumption in Stop mode - VDD=3.3 V
Typ Max(1)

Symbol Parameter Conditions TA = Unit

TA = TA = TA =
105 °
25 °C 25 °C 85 °C
C

Main regulator usage Flash in Stop mode, all 111 140 450 670
oscillators OFF, no
Low power regulator usage independent watchdog 42 65 330 560
IDD_STO
Main regulator usage Flash in Deep power 73 100 360 560 µA
P
down mode, all
Low power regulator usage 12 36 270 520
oscillators OFF, no
Low power low voltage regulator usage independent watchdog 10 28 230 470
1. Evaluated by characterization.

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Table 29. Typical and maximum current consumption in Standby mode - VDD=1.8 V
Typ(1) Max(2)
Symbol Parameter Conditions Unit
TA = TA = TA = TA =
25 °C 25 °C 85 °C 105 °C

Supply current in Low-speed oscillator (LSE) and RTC ON 2.4 4.0 12.0 24.0
IDD_STBY µA
Standby mode RTC and LSE OFF 1.8 3.0(3) 11.0 23.0(3)
1. When the PDR is OFF (internal reset is OFF), the typical current consumption is reduced by 1.2 µA.
2. Evaluated by characterization, unless otherwise specified.
3. Evaluated by test in production.

Table 30. Typical and maximum current consumption in Standby mode - VDD=3.3 V
Typ(1) Max(2)
Uni
Symbol Parameter Conditions
TA = TA = TA = TA = t
25 °C 25 °C 85 °C 105 °C

Supply current in Low-speed oscillator (LSE) and RTC ON 2.8 5.0 14.0 28.0
IDD_STBY µA
Standby mode RTC and LSE OFF 2.1 4.0(3) 13.0 27.0(3)
1. When the PDR is OFF (internal reset is OFF), the typical current consumption is reduced by 1.2 µA.
2. Evaluated by characterization, unless otherwise specified.
3. Evaluated by test in production.

Table 31. Typical and maximum current consumptions in VBAT mode

Typ Max(2)

TA = TA =
TA = 25 °C
85 °C 105 °C Uni
Symbol Parameter Conditions(1)
t
VBAT VBAT
VBAT=
= = VBAT = 3.6 V
2.4 V
1.7 V 3.3 V

Backup Low-speed oscillator (LSE) and RTC

0.66 0.76 0.97 3.0 5.0
IDD_VBA domain ON
µA
T supply
current RTC and LSE OFF 0.1 0.1 0.1 2.0 4.0

1. Crystal used: Abracon ABS07-120-32.768 kHz-T with a CL of 6 pF for typical values.

2. Evaluated by characterization.

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Figure 21. Typical VBAT current consumption (LSE and RTC ON)

2.5
IDD_VBAT (μA)

1.65V
1.5 1.7V
1.8V
2V
1 2.4V
2.7V
3V
0.5
3.3V
3.6V
0
0°C 25°C 55°C 85°C 105°C
Temperature
MS30490V1

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull resistors generate current consumption when the pin is
externally held to the opposite level. The value of this current consumption can be simply
computed by using the pull-up/pull-down resistors values given inTable 54: I/O static
characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption (see Table 33: Peripheral current
consumption), the I/Os used by an application also contribute to the current consumption.
When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O

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pin circuitry and to charge/discharge the capacitive load (internal or external) connected to
the pin:

I SW = V DD × f SW × C

where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDD is the MCU supply voltage
fSW is the I/O switching frequency
C is the total capacitance seen by the I/O pin: C = CINT+ CEXT
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.

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Table 32. Switching output I/O current consumption

I/O toggling
Symbol Parameter Conditions(1) Typ Unit
frequency (fSW)

2 MHz 0.05
8 MHz 0.15

VDD = 3.3 V 25 MHz 0.45

C = CINT 50 MHz 0.85
60 MHz 1.00
84 MHz 1.40
2 MHz 0.10
8 MHz 0.35
VDD = 3.3 V 25 MHz 1.05
CEXT = 0 pF
50 MHz 2.20
C = CINT + CEXT + CS
60 MHz 2.40
84 MHz 3.55
2 MHz 0.20
I/O switching
IDDIO 8 MHz 0.65 mA
current
VDD = 3.3 V 25 MHz 1.85
CEXT =10 pF
50 MHz 2.45
C = CINT + CEXT + CS
60 MHz 4.70
84 MHz 8.80
2 MHz 0.25

VDD = 3.3 V 8 MHz 1.00

CEXT = 22 pF 25 MHz 3.45
C = CINT + CEXT + CS 50 MHz 7.15
60 MHz 11.55
2 MHz 0.32
VDD = 3.3 V 8 MHz 1.27
CEXT = 33 pF
25 MHz 3.88
C = CINT + CEXT + CS
50 MHz 12.34
1. CS is the PCB board capacitance including the pad pin. CS = 7 pF (estimated value).

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On-chip peripheral current consumption

The MCU is placed under the following conditions:
• At startup, all I/O pins are in analog input configuration.
• All peripherals are disabled unless otherwise mentioned.
• The ART accelerator is ON.
• Voltage Scale 2 mode selected, internal digital voltage V12 = 1.26 V.
• HCLK is the system clock at 84 MHz. fPCLK1 = fHCLK/2, and fPCLK2 = fHCLK.
The given value is calculated by measuring the difference of current consumption
– with all peripherals clocked off
– with only one peripheral clocked on
• Ambient operating temperature is 25 °C and VDD=3.3 V.

Table 33. Peripheral current consumption

Peripheral IDD (typ) Unit

GPIOA 1.55
GPIOB 1.55
GPIOC 1.55
GPIOD 1.55
AHB1
GPIOE 1.55 µA/MHz
(up to 84 MHz)
GPIOH 1.55
CRC 0.36
DMA1 20.24
DMA2 21.07
TIM2 11.19
TIM3 8.57
TIM4 8.33
TIM5 11.19
PWR 0.71

APB1 USART2 3.33

µA/MHz
(up to 42 MHz) I2C1/2/3 3.10
SPI2(1) 2.62
SPI3(1) 2.86
I2S2 1.90
I2S3 1.67
WWDG 0.71
AHB2
OTG_FS 23.93 µA/MHz
(up to 84 MHz)

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Table 33. Peripheral current consumption (continued)

Peripheral IDD (typ) Unit

TIM1 5.71
TIM9 2.86
TIM10 1.79
TIM11 2.02
(2)
ADC1 2.98
APB2
SPI1 1.19 µA/MHz
(up to 84 MHz)
USART1 3.10
USART6 2.86
SDIO 5.95
SPI4 1.31
SYSCFG 0.71
1. I2SMOD bit set in SPI_I2SCFGR register, and then the I2SE bit set to enable I2S peripheral.
2. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6
mA for the analog part.

6.3.7 Wake-up time from low-power modes

The wake-up times given in Table 34 are measured starting from the wake-up event trigger
up to the first instruction executed by the CPU:
• For Stop or Sleep modes: the wake-up event is WFE.
• WKUP (PA0) pin is used to wake-up from Standby, Stop and Sleep modes.
All timings are derived from tests performed under ambient temperature and VDD=3.3 V.

Table 34. Low-power mode wake-up timings(1)

Symbol Parameter Min(1) Typ(1) Max(1) Unit

CPU
tWUSLEEP(2) Wake-up from Sleep mode - 4 6 clock
cycle
Wake-up from Stop mode, usage of main regulator - 13.5 14.5
Wake-up from Stop mode, usage of main regulator, flash
- 105 111
memory in Deep power down mode
tWUSTOP(2) µs
Wake-up from Stop mode, regulator in low power mode - 21 33
Wake-up from Stop mode, regulator in low power mode,
- 113 130
flash memory in Deep power down mode
tWUSTDBY(2)(3) Wake-up from Standby mode - 314 407 µs
1. Evaluated by characterization.
2. The wake-up times are measured from the wake-up event to the point in which the application code reads the first
instruction.
3. tWUSTDBY maximum value is given at –40 °C.

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6.3.8 External clock source characteristics

High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 54. However, the recommended clock input
waveform is shown in Figure 22.
The characteristics given in Table 35 result from tests performed using an high-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 14.

Table 35. High-speed external user clock characteristics

Symbol Parameter Conditions Min Typ Max Unit

External user clock source

fHSE_ext 1 - 50 MHz
frequency(1)
VHSEH OSC_IN input pin high level voltage 0.7VDD - VDD
V
VHSEL OSC_IN input pin low level voltage VSS - 0.3VDD
-
tw(HSE)
OSC_IN high or low time(1) 5 - -
tw(HSE)
ns
tr(HSE)
OSC_IN rise or fall time(1) - - 10
tf(HSE)
Cin(HSE) OSC_IN input capacitance(1) - - 5 - pF
DuCy(HSE) Duty cycle - 45 - 55 %
IL OSC_IN Input leakage current VSS ≤VIN ≤VDD - - ±1 µA
1. Specified by design.

Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 54. However, the recommended clock input
waveform is shown in Figure 23.
The characteristics given in Table 36 result from tests performed using an low-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 14.

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Table 36. Low-speed external user clock characteristics

Symbol Parameter Conditions Min Typ Max Unit

User External clock source

fLSE_ext - 32.768 1000 kHz
frequency(1)
OSC32_IN input pin high level
VLSEH 0.7VDD - VDD
voltage V
VLSEL OSC32_IN input pin low level voltage - VSS - 0.3VDD
tw(LSE)
OSC32_IN high or low time(1) 450 - -
tf(LSE)
ns
tr(LSE)
OSC32_IN rise or fall time(1) - - 50
tf(LSE)
Cin(LSE) OSC32_IN input capacitance(1) - - 5 - pF
DuCy(LSE) Duty cycle - 30 - 70 %
IL OSC32_IN Input leakage current VSS ≤ VIN ≤ VDD - - ±1 µA
1. Specified by design.

Figure 22. High-speed external clock source AC timing diagram

VHSEH
90 %
10 %
VHSEL
tr(HSE) tf(HSE) tW(HSE) tW(HSE) t

THSE

External fHSE_ext
IL
clock source OSC_IN
STM32F

ai17528

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Figure 23. Low-speed external clock source AC timing diagram

VLSEH
90%
10%
VLSEL
tr(LSE) tf(LSE) tW(LSE) tW(LSE) t

TLSE

External fLSE_ext
OSC32_IN IL
clock source
STM32F

ai17529

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 37. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).

Table 37. HSE 4-26 MHz oscillator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fOSC_IN Oscillator frequency - 4 - 26 MHz

RF Feedback resistor - - 200 - kΩ
VDD=3.3 V,
ESR= 30 Ω, - 450 -
CL=5 pF @25 MHz
IDD HSE current consumption µA
VDD=3.3 V,
ESR= 30 Ω, - 530 -
CL=10 pF @25 MHz
Gm_crit_max Maximum critical crystal gm Startup - - 1 mA/V
tSU(HSE)(2) Startup time VDD is stabilized - 2 - ms
1. Specified by design.
2. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer

For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 24). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF

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can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2.
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.

Figure 24. Typical application with an 8 MHz crystal

Resonator with
integrated capacitors
CL1
OSC_IN fHSE
Bias
8 MHz RF controlled
resonator
gain

REXT(1) OSC_OU T STM32F

CL2
ai17530

1. REXT value depends on the crystal characteristics.

Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 38. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).

Table 38. LSE oscillator characteristics (fLSE = 32.768 kHz) (1)

Symbol Parameter Conditions Min Typ Max Unit

RF Feedback resistor - - 18.4 - MΩ

IDD LSE current consumption - - - 1 µA
Gm_crit_max Maximum critical crystal gm Startup - - 0.56 µA/V
tSU(LSE)(2) startup time VDD is stabilized - 2 - s
1. Specified by design.
2. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized
32.768 kHz oscillation is reached. This value is evaluated by characterization. It is measured for a
standard crystal resonator and it can vary significantly with the crystal manufacturer.

Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.

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Figure 25. Typical application with a 32.768 kHz crystal

Resonator with
integrated capacitors
CL1
OSC32_IN fLSE
Bias
32.768 kH z RF controlled
resonator
gain
OSC32_OU T STM32F
CL2
ai17531

6.3.9 Internal clock source characteristics

The parameters given in Table 39: HSI oscillator characteristics and Table 40: LSI oscillator
characteristics are derived from tests performed under ambient temperature and VDD supply
voltage conditions summarized in Table 14: General operating conditions.

High-speed internal (HSI) RC oscillator

Table 39. HSI oscillator characteristics (1)

Symbol Parameter Conditions Min Typ Max Unit

fHSI Frequency - - 16 - MHz

HSI user trimming step(2) - - - 1 %
TA = –40 to 105 °C(3) –8 - 4.5 %
ACCHSI
Accuracy of the HSI oscillator TA = –10 to 85 °(3) –4 - 4 %
TA = 25 °C(4) –1 - 1 %
(2)
tsu(HSI) HSI oscillator startup time - - 2.2 4 µs
HSI oscillator power
IDD(HSI)(2) - - 60 80 µA
consumption
1. VDD = 3.3 V, PLL OFF, TA = –40 to 105 °C unless otherwise specified.
2. Specified by design.
3. Evaluated by characterization.
4. Factory calibrated, parts not soldered.

Figure 26. ACCHSI versus temperature

0.06

0.04

0.02
ACCHSI

0
-40 0 25 55 85 105 125 TA (°C)
-0.02

-0.04
Min
Max
-0.06 Typical
-0.08
MS30492V2

1. Evaluated by characterization.

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Low-speed internal (LSI) RC oscillator

Table 40. LSI oscillator characteristics (1)

Symbol Parameter Min Typ Max Unit

fLSI(2) Frequency 17 32 47 kHz

tsu(LSI)(3) LSI oscillator startup time - 15 40 µs
IDD(LSI)(3) LSI oscillator power consumption - 0.4 0.6 µA
1. VDD = 3 V, TA = - 40 to 105 °C unless otherwise specified.
2. Evaluated by characterization.
3. Specified by design.

Figure 27. ACCLSI versus temperature

50
max
40 avg
min
30
Normalized deviati on (%)

20

10

-10

-20

-30

-40
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105
Temperat ure (°C)

MS19013V1

6.3.10 PLL characteristics

The parameters given in Table 41 and Table 42 are derived from tests performed under
temperature and VDD supply voltage conditions summarized in Table 14.

Table 41. Main PLL characteristics

Symbol Parameter Conditions Min Typ Max Unit

fPLL_IN PLL input clock(1) - 0.95(2) 1 2.10

fPLL_OUT PLL multiplier output clock - 24 - 84
MHz
fPLL48_OUT 48 MHz PLL multiplier output clock - - 48 75
fVCO_OUT PLL VCO output - 192 - 432

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Table 41. Main PLL characteristics (continued)

Symbol Parameter Conditions Min Typ Max Unit

VCO freq = 192 MHz 75 - 200

tLOCK PLL lock time µs
VCO freq = 432 MHz 100 - 300
RMS - 25 -
Cycle-to-cycle jitter peak to
- ±150 -
System clock peak
(3)
Jitter ps
84 MHz RMS - 15 -
Period Jitter peak to
- ±200 -
peak
VCO freq = 192 MHz 0.15 0.40
IDD(PLL)(4) PLL power consumption on VDD -
VCO freq = 432 MHz 0.45 0.75
mA
VCO freq = 192 MHz 0.30 0.40
IDDA(PLL)(4) PLL power consumption on VDDA -
VCO freq = 432 MHz 0.55 0.85
1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared
between PLL and PLLI2S.
2. Specified by design.
3. The use of two PLLs in parallel can degrade the Jitter up to +30%.
4. Evaluated by characterization.

Table 42. PLLI2S (audio PLL) characteristics

Symbol Parameter Conditions Min Typ Max Unit

fPLLI2S_IN PLLI2S input clock(1) - 0.95(2) 1 2.10

fPLLI2S_OUT PLLI2S multiplier output clock - - - 216 MHz
fVCO_OUT PLLI2S VCO output - 192 - 432
VCO freq = 192 MHz 75 - 200
tLOCK PLLI2S lock time µs
VCO freq = 432 MHz 100 - 300
Cycle to cycle at RMS - 90 - -
12.288 MHz on
48 KHz period, peak to
- ±280 -
N=432, R=5 peak
Master I2S clock jitter
Average frequency of
Jitter(3) 12.288 MHz
- 90 - ps
N = 432, R = 5
on 1000 samples
Cycle to cycle at 48 KHz
WS I2S clock jitter - 400 -
on 1000 samples
PLLI2S power consumption on VCO freq = 192 MHz 0.15 0.40
IDD(PLLI2S)(4) -
VDD VCO freq = 432 MHz 0.45 0.75
mA
PLLI2S power consumption on VCO freq = 192 MHz 0.30 0.40
IDDA(PLLI2S)(4) -
VDDA VCO freq = 432 MHz 0.55 0.85
1. Take care of using the appropriate division factor M to have the specified PLL input clock values.

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2. Specified by design.
3. Value given with main PLL running.
4. Evaluated by characterization.

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6.3.11 PLL spread spectrum clock generation (SSCG) characteristics

The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic
interferences(see Table 49: EMI characteristics for WLCSP49). It is available only on the
main PLL.

Table 43. SSCG parameters constraint

Symbol Parameter Min Typ Max(1) Unit

fMod Modulation frequency - - 10 KHz

md Peak modulation depth 0.25 - 2 %
MODEPER * INCSTEP - - - 215 -1 -
1. Specified by design.

Equation 1
The frequency modulation period (MODEPER) is given by the equation below:
MODEPER = round [ f PLL_IN ⁄ ( 4 × f Mod ) ]

fPLL_IN and fMod must be expressed in Hz.

As an example:
If fPLL_IN = 1 MHz, and fMOD = 1 kHz, the modulation depth (MODEPER) is given by
equation 1:
6 3
MODEPER = round [ 10 ⁄ ( 4 × 10 ) ] = 250

Equation 2
Equation 2 allows to calculate the increment step (INCSTEP):
15
INCSTEP = round [ ( ( 2 – 1 ) × md × PLLN ) ⁄ ( 100 × 5 × MODEPER ) ]

fVCO_OUT must be expressed in MHz.

With a modulation depth (md) = ±2 % (4 % peak to peak), and PLLN = 240 (in MHz):
15
INCSTEP = round [ ( ( 2 – 1 ) × 2 × 240 ) ⁄ ( 100 × 5 × 250 ) ] = 126md(quantitazed)%

An amplitude quantization error may be generated because the linear modulation profile is
obtained by taking the quantized values (rounded to the nearest integer) of MODPER and
INCSTEP. As a result, the achieved modulation depth is quantized. The percentage
quantized modulation depth is given by the following formula:
15
md quantized % = ( MODEPER × INCSTEP × 100 × 5 ) ⁄ ( ( 2 – 1 ) × PLLN )

As a result:
15
md quantized % = ( 250 × 126 × 100 × 5 ) ⁄ ( ( 2 – 1 ) × 240 ) = 2.002%(peak)

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Figure 28 and Figure 29 show the main PLL output clock waveforms in center spread and
down spread modes, where:
F0 is fPLL_OUT nominal.
Tmode is the modulation period.
md is the modulation depth.

Figure 28. PLL output clock waveforms in center spread mode

Frequency (PLL_OUT)

md
F0
md

Time
tmode 2xtmode
ai17291

Figure 29. PLL output clock waveforms in down spread mode

Frequency (PLL_OUT)

F0
2xmd

Time
tmode 2xtmode
ai17292b

6.3.12 Memory characteristics

Flash memory
The characteristics are given at TA = –40 to 105 °C unless otherwise specified.
The devices are shipped to customers with the Flash memory erased.

Table 44. Flash memory characteristics

Symbol Parameter Conditions Min Typ Max Unit

Write / Erase 8-bit mode, VDD = 1.7 V - 5 -

IDD Supply current Write / Erase 16-bit mode, VDD = 2.1 V - 8 - mA
Write / Erase 32-bit mode, VDD = 3.3 V - 12 -

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Table 45. Flash memory programming

Symbol Parameter Conditions Min(1) Typ Max(1) Unit

Program/erase parallelism
tprog Word programming time - 16 100(2) µs
(PSIZE) = x 8/16/32
Program/erase parallelism
- 400 800
(PSIZE) = x 8
Program/erase parallelism
tERASE16KB Sector (16 KB) erase time - 300 600 ms
(PSIZE) = x 16
Program/erase parallelism
- 250 500
(PSIZE) = x 32
Program/erase parallelism
- 1200 2400
(PSIZE) = x 8
Program/erase parallelism
tERASE64KB Sector (64 KB) erase time - 700 1400 ms
(PSIZE) = x 16
Program/erase parallelism
- 550 1100
(PSIZE) = x 32
Program/erase parallelism
- 2 4
(PSIZE) = x 8
Program/erase parallelism
tERASE128KB Sector (128 KB) erase time - 1.3 2.6 s
(PSIZE) = x 16
Program/erase parallelism
- 1 2
(PSIZE) = x 32
Program/erase parallelism
- 8 16
(PSIZE) = x 8
Program/erase parallelism
tME Mass erase time - 5.5 11 s
(PSIZE) = x 16
Program/erase parallelism
- 4 8
(PSIZE) = x 32
32-bit program operation 2.7 - 3.6 V
Vprog Programming voltage 16-bit program operation 2.1 - 3.6 V
8-bit program operation 1.7 - 3.6 V
1. Evaluated by characterization.
2. The maximum programming time is measured after 100K erase operations.

Table 46. Flash memory programming with VPP voltage

Symbol Parameter Conditions Min(1) Typ Max(1) Unit

tprog Double word programming - 16 100(2) µs

tERASE16KB Sector (16 KB) erase time TA = 0 to +40 °C - 230 -
tERASE64KB Sector (64 KB) erase time VDD = 3.3 V - 490 - ms
tERASE128KB Sector (128 KB) erase time VPP = 8.5 V - 875 -
tME Mass erase time - 1.750 - s
Vprog Programming voltage - 2.7 - 3.6 V

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Table 46. Flash memory programming with VPP voltage (continued)

Symbol Parameter Conditions Min(1) Typ Max(1) Unit

VPP VPP voltage range - 7 - 9 V

Minimum current sunk on
IPP - 10 - - mA
the VPP pin
Cumulative time during
tVPP(3) - - - 1 hour
which VPP is applied
1. Specified by design.
2. The maximum programming time is measured after 100K erase operations.
3. VPP should only be connected during programming/erasing.

Table 47. Flash memory endurance and data retention

Value Unit
Symbol Parameter Conditions
Max(1) -

TA = –40 to +85 °C (6 suffix versions)

NEND Endurance 10 Kcycles
TA = –40 to +105 °C (7 suffix versions)
1 kcycle(2) at TA = 85 °C 30
(2)
tRET Data retention 1 kcycle at TA = 105 °C 10 Years
10 kcycles(2) at TA = 55 °C 20
1. Specified by design.
2. Cycling performed over the whole temperature range.

6.3.13 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant
with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 48. They are based on the EMS levels and classes
defined in application note AN1709.

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Table 48. EMS characteristics for LQFP100 package

Level/
Symbol Parameter Conditions
Class

VDD = 3.3 V, LQFP100, WLCSP49,

Voltage limits to be applied on any I/O pin
VFESD TA = +25 °C, fHCLK = 84 MHz, 2B
to induce a functional disturbance
conforms to IEC 61000-4-2
Fast transient voltage burst limits to be VDD = 3.3 V, LQFP100, WLCSP49,
VEFTB applied through 100 pF on VDD and VSS TA = +25 °C, fHCLK = 84 MHz, 4A
pins to induce a functional disturbance conforms to IEC 61000-4-4

When the application is exposed to a noisy environment, it is recommended to avoid pin

exposition to disturbances. The pins showing a middle range robustness are: PA0, PA1,
PA2, on LQFP100 packages and PDR_ON on WLCSP49.
As a consequence, it is recommended to add a serial resistor (1 kΩ maximum) located as
close as possible to the MCU to the pins exposed to noise (connected to tracks longer than
50 mm on PCB).

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
• Corrupted program counter
• Unexpected reset
• Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).

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Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application,
executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2
standard which specifies the test board and the pin loading.

Table 49. EMI characteristics for WLCSP49

Max vs.
Monitored [fHSE/fCPU]
Symbol Parameter Conditions Unit
frequency band
8/84 MHz

0.1 to 30 MHz -4

VDD = 3.6 V, TA = 25 °C, conforming to 30 to 130 MHz -4 dBµV

SEMI Peak level
IEC61967-2 130 MHz to 1 GHz -2
SAE EMI Level 1.5 -

Table 50. EMI characteristics for LQFP100

Max vs.
Monitored [fHSE/fCPU]
Symbol Parameter Conditions Unit
frequency band
8/84 MHz

0.1 to 30 MHz 19

VDD = 3.6 V, TA = 25 °C, conforming to 30 to 130 MHz 19 dBµV

SEMI Peak level
IEC61967-2 130 MHz to 1 GHz 11
SAE EMI Level 3.5 -

6.3.14 Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.

Table 51. ESD absolute maximum ratings

Maximum
Symbol Ratings Conditions Class Unit
value(1)

Electrostatic discharge voltage TA = +25 °C conforming to

VESD(HBM) 2 2000
(human body model) JESD22-A114
V
Electrostatic discharge voltage TA = +25 °C conforming to
VESD(CDM) II 400
(charge device model) ANSI/ESD STM5.3.1

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1. Evaluated by characterization.

Static latchup
Two complementary static tests are required on six parts to assess the latchup
performance:
• A supply overvoltage is applied to each power supply pin
• A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latchup standard.

Table 52. Electrical sensitivities

Symbol Parameter Conditions Class

LU Static latch-up class TA = + 105 °C conforming to JESD78A II level A

6.3.15 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product
operation. However, in order to give an indication of the robustness of the microcontroller in
cases when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.

Functional susceptibilty to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit
(>5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins
(out of –5 µA/+0 µA range), or other functional failure (for example reset, oscillator
frequency deviation).
Negative induced leakage current is caused by negative injection and positive induced
leakage current by positive injection.
The test results are given in Table 53.

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Table 53. I/O current injection susceptibility(1)

Functional susceptibility
Symbol Description Unit
Negative Positive
injection injection

Injected current on BOOT0 pin –0 NA

Injected current on NRST pin –0 NA
Injected current on PB3, PB4, PB5, PB6,
PB7, PB8, PB9, PC13, PC14, PC15, PH1,
IINJ –0 NA mA
PDR_ON, PC0, PC1,PC2, PC3, PD1, PD5,
PD6, PD7, PE0, PE2, PE3, PE4, PE5, PE6
Injected current on any other FT pin –5 NA
Injected current on any other pins –5 +5
1. NA = not applicable.

Note: It is recommended to add a Schottky diode (pin to ground) to analog pins which may
potentially inject negative currents.

6.3.16 I/O port characteristics

General input/output characteristics
Unless otherwise specified, the parameters given in Table 54 are derived from tests
performed under the conditions summarized in Table 14. All I/Os are CMOS and TTL
compliant.
Note: For information on GPIO configuration, refer to the application note AN4899 “STM32 GPIO
configuration for hardware settings and low-power consumption”, available from
www.st.com.

Table 54. I/O static characteristics

Symbol Parameter Conditions Min Typ Max Unit

FT, and NRST I/O input low

1.7 V≤VDD≤3.6 V - - 0.3VDD(1)
level voltage
1.75 V≤VDD ≤ 3.6 V,
VIL - - V
BOOT0 I/O input low level -40 °C≤TA ≤ 105 °C
0.1VDD+0.1
voltage 1.7 V≤VDD ≤3.6 V,
- -
0 °C≤TA ≤ 105 °C
FT and NRST I/O input high
1.7 V≤VDD≤3.6 V 0.7VDD(2) - -
level voltage(5)
1.75 V≤VDD ≤3.6 V,
VIH V
BOOT0 I/O input high level -40 °C≤TA ≤ 105 °C
0.17VDD+0.7(2) - -
voltage 1.7 V≤VDD ≤3.6 V,
0 °C≤TA ≤ 105 °C

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Table 54. I/O static characteristics (continued)

Symbol Parameter Conditions Min Typ Max Unit

FT and NRST I/O input 10%

1.7 V≤VDD≤3.6 V - - V
hysteresis VDD(3)
1.75 V≤VDD ≤3.6 V,
VHYS
-40 °C≤TA ≤ 105 °C
BOOT0 I/O input hysteresis - 100 - mV
1.7 V≤VDD ≤3.6 V,
0 °C≤TA ≤ 105 °C
I/O input leakage current (4) VSS ≤VIN ≤VDD - - ±1
Ilkg µA
(5)
I/O FT input leakage current VIN = 5 V - - 3
All pins except
Weak pull-up for PA10 30 40 50
RPU equivalent (OTG_FS_ID) VIN = VSS
resistor(6) PA10
7 10 14
(OTG_FS_ID)
kΩ
All pins except
Weak pull- for PA10 30 40 50
down (OTG_FS_ID)
RPD VIN = VDD
equivalent
resistor(7) PA10
7 10 14
(OTG_FS_ID)
CIO(8) I/O pin capacitance - - 5 - pF
1. Evaluated by test in production.
2. Specified by design.
3. With a minimum of 200 mV.
4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins, Refer to Table 53: I/O
current injection susceptibility
5. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled. Leakage could be
higher than the maximum value, if negative current is injected on adjacent pins.Refer to Table 53: I/O current injection
susceptibility
6. Pull-up resistors are designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the
series resistance is minimum (~10% order).
7. Pull-down resistors are designed with a true resistance in series with a switchable NMOS. This NMOS contribution to the
series resistance is minimum (~10% order).
8. Hysteresis voltage between Schmitt trigger switching levels. Evaluated by characterization.

All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements for FT I/Os is shown in Figure 30.

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Figure 30. FT I/O input characteristics

VIL/VIH (V)

2.52 DD
7V
0.
=
in
m
V IH
ent
m
u ire
eq TTL requirement
r
VIHmin = 2V
2.00 OS
1.92 - CM
.3
n +0
ctio VD D

o du 0.45
pr n=
in IHmi
t ed ,V
s ns
Te tio
ula
im
ns
1.22 do Area not
se 0.04
1.19 Ba D-
determined 35V D
ax = 0.
1.065 , VILm
tions
ns imula
0.80 ed o
Bas TTL requirement
-
0.55 c n
ti o VILmax = 0.8V
rodu ent
0.51 d in p em
Teste S requir V DD
CMO ax = 0.3
VILm

VDD (V)
1.7 2.0 2.4 2.7 3.3 3.6
MS33746V3

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA (with a relaxed VOL/VOH) except PC13, PC14 and PC15 which can
sink or source up to ±3mA. When using the PC13 to PC15 GPIOs in output mode, the speed
should not exceed 2 MHz with a maximum load of 30 pF.
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2. In particular:
• The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
ΣIVDD (see Table 12).
• The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
ΣIVSS (see Table 12).

Output voltage levels

Unless otherwise specified, the parameters given in Table 55 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 14. All I/Os are CMOS and TTL compliant.

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Table 55. Output voltage characteristics

Symbol Parameter Conditions Min Max Unit

VOL(1) Output low level voltage for an I/O pin CMOS port(2) - 0.4
IIO = +8 mA V
VOH(3) Output high level voltage for an I/O pin
2.7 V ≤VDD ≤3.6 V
VDD–0.4 -

VOL (1) Output low level voltage for an I/O pin TTL port(2) - 0.4
IIO =+8 mA V
VOH (3) Output high level voltage for an I/O pin
2.7 V ≤VDD ≤3.6 V
2.4 -

VOL(1) Output low level voltage for an I/O pin IIO = +20 mA - 1.3(4)
V
VOH(3) Output high level voltage for an I/O pin 2.7 V ≤VDD ≤3.6 V VDD–1.3(4) -
VOL(1) Output low level voltage for an I/O pin IIO = +6 mA - 0.4(4)
V
VOH(3) Output high level voltage for an I/O pin 1.8 V ≤VDD ≤3.6 V VDD–0.4(4) -
VOL(1) Output low level voltage for an I/O pin IIO = +4 mA - 0.4(5)
V
VOH(3) Output high level voltage for an I/O pin 1.7 V ≤VDD ≤3.6 V VDD–0.4(5) -
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 12.
and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 12 and the sum of IIO (I/O ports and control pins) must not exceed IVDD.
4. Evaluated by characterization.
5. Specified by design.

Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 31 and ,
respectively.
Unless otherwise specified, the parameters given in Table 56 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 14.

Table 56. I/O AC characteristics(1)(2)

OSPEEDRy
[1:0] bit Symbol Parameter Conditions Min Typ Max Unit
value(1)

CL = 50 pF, VDD ≥ 2.70 V - - 4

CL = 50 pF, VDD≥ 1.7 V - - 2
fmax(IO)out Maximum frequency(3) MHz
CL = 10 pF, VDD ≥ 2.70 V - - 8
00
CL = 10 pF, VDD ≥ 1.7 V - - 4
Output high to low level fall
tf(IO)out/ CL = 50 pF, VDD = 1.7 V to
time and output low to high - - 100 ns
tr(IO)out 3.6 V
level rise time

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Table 56. I/O AC characteristics(1)(2) (continued)

OSPEEDRy
[1:0] bit Symbol Parameter Conditions Min Typ Max Unit
value(1)

CL = 50 pF, VDD ≥ 2.70 V - - 25

CL = 50 pF, VDD ≥ 1.7 V - - 12.5
fmax(IO)out Maximum frequency(3) MHz
CL = 10 pF, VDD ≥ 2.70 V - - 50
CL = 10 pF, VDD ≥ 1.7 V - - 20
01
CL = 50 pF, VDD ≥2.7 V - - 10
Output high to low level fall CL = 50 pF, VDD ≥ 1.7 V - - 20
tf(IO)out/
time and output low to high ns
tr(IO)out CL = 10 pF, VDD ≥ 2.70 V - - 6
level rise time
CL = 10 pF, VDD ≥ 1.7 V - - 10
CL = 40 pF, VDD ≥ 2.70 V - - 50(4)
CL = 40 pF, VDD ≥ 1.7 V - - 25
fmax(IO)out Maximum frequency(3) MHz
CL = 10 pF, VDD ≥ 2.70 V - - 100(4)
CL = 10 pF, VDD ≥ 1.7 V - - 50(4)
10
CL = 40 pF, VDD≥ 2.70 V - - 6
Output high to low level fall CL = 40 pF, VDD≥ 1.7 V - - 10
tf(IO)out/
time and output low to high ns
tr(IO)out CL = 10 pF, VDD≥ 2.70 V - - 4
level rise time
CL = 10 pF, VDD≥ 1.7 V - - 6
CL = 30 pF, VDD ≥ 2.70 V - - 100(4)
CL = 30 pF, VDD ≥ 1.7 V - - 50(4)
Fmax(IO)out Maximum frequency(3) MHz
CL = 10 pF, VDD ≥ 2.70 V - - 180(4)
CL = 10 pF, VDD≥ 1.7 V - - 100(4)
11
CL = 30 pF, VDD ≥ 2.70 V - - 4
Output high to low level fall CL = 30 pF, VDD ≥ 1.7 V - - 6
tf(IO)out/
time and output low to high ns
tr(IO)out CL = 10 pF, VDD≥ 2.70 V - - 2.5
level rise time
CL = 10 pF, VDD≥ 1.7 V - - 4
Pulse width of external
- tEXTIpw signals detected by the EXTI - 10 - - ns
controller
1. Evaluated by characterization.
2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F4xx reference manual for a description of
the GPIOx_SPEEDR GPIO port output speed register.
3. The maximum frequency is defined in Figure 31.
4. For maximum frequencies above 50 MHz and VDD > 2.4 V, the compensation cell should be used.

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Figure 31. I/O AC characteristics definition

90% 10%

50% 50%

10% 90%

EXTERNAL tr(IO)out tf(IO)out

OUTPUT
ON CL T

Maximum frequency is achieved if (tr + tf ”  7DQGLIWKHGXW\F\FOHLV  

ZKHQORDGHGE\&LVSHFLILHGLQWKHWDEOH³I/O AC characteristics”.

ai14131d

6.3.17 NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 54).
Unless otherwise specified, the parameters given in Table 57 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 14. Refer to Table 54: I/O static characteristics for the values of VIH and VIL for
NRST pin.

Table 57. NRST pin characteristics

Symbol Parameter Conditions Min Typ Max Unit

Weak pull-up equivalent

RPU VIN = VSS 30 40 50 kΩ
resistor(1)
VF(NRST)(2) NRST Input filtered pulse - - - 100 ns
VNF(NRST)(2) NRST Input not filtered pulse VDD > 2.7 V 300 - - ns
Internal Reset
TNRST_OUT Generated reset pulse duration 20 - - µs
source
1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance must be minimum (~10% order).
2. Specified by design.

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Figure 32. Recommended NRST pin protection

VDD
External
reset circuit (1)
RPU
NRST (2) Internal Reset
Filter

0.1 μF

STM32F

ai14132c

1. The reset network protects the device against parasitic resets.

2. The external capacitor must be placed as close as possible to the device.
3. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 57. Otherwise the reset is not taken into account by the device.

6.3.18 TIM timer characteristics

The parameters given in Table 58 are specified by design.
Refer to Section 6.3.16: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).

Table 58. TIMx characteristics(1)(2)

Symbol Parameter Conditions(3) Min Max Unit

AHB/APBx prescaler=1 1 - tTIMxCLK

or 2 or 4, fTIMxCLK =
84 MHz 11.9 - ns
tres(TIM) Timer resolution time
AHB/APBx prescaler>4, 1 - tTIMxCLK
fTIMxCLK = 84 MHz 11.9 - ns

Timer external clock 0 fTIMxCLK/2 MHz

fEXT
frequency on CH1 to CH4 fTIMxCLK = 84 MHz 0 42 MHz
ResTIM Timer resolution - 16/32 bit
16-bit counter clock period
tCOUNTER when internal clock is fTIMxCLK = 84 MHz 0.0119 780 µs
selected

Maximum possible count with - - 65536 × 65536 tTIMxCLK

tMAX_COUNT
32-bit counter fTIMxCLK = 84 MHz - 51.1 S
1. TIMx is used as a general term to refer to the TIM1 to TIM11 timers.
2. Specified by design.
3. The maximum timer frequency on APB1 is 42 MHz and on APB2 is up to 84 MHz, by setting the TIMPRE bit in the
RCC_DCKCFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = HCKL, otherwise TIMxCLK >= 4x PCLKx.

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6.3.19 Communications interfaces

I2C interface characteristics
The I2C interface meets the requirements of the standard I2C communication protocol with
the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-
drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is
disabled, but is still present.
The I2C characteristics are described in Table59. Refer also to Section 6.3.16: I/O port
characteristics for more details on the input/output alternate function characteristics (SDA
and SCL).
The I2C bus interface supports standard mode (up to 100 kHz) and fast mode (up to 400
kHz). The I2C bus frequency can be increased up to 1 MHz. For more details about the
complete solution, please contact your local ST sales representative.

Table 59. I2C characteristics

Standard mode I2C(1) Fast mode I2C(1)(2)
Symbol Parameter Unit
Min Max Min Max

tw(SCLL) SCL clock low time 4.7 - 1.3 -

µs
tw(SCLH) SCL clock high time 4.0 - 0.6 -
tsu(SDA) SDA setup time 250 - 100 -
th(SDA) SDA data hold time 0 - 0 900(3)
tr(SDA) ns
SDA and SCL rise time - 1000 300
tr(SCL)
tf(SDA)
SDA and SCL fall time - 300 - 300
tf(SCL)
th(STA) Start condition hold time 4.0 - 0.6 -
µs
tsu(STA) Repeated Start condition setup time 4.7 - 0.6 -
tsu(STO) Stop condition setup time 4.0 - 0.6 - µs
tw(STO:STA) Stop to Start condition time (bus free) 4.7 - 1.3 - µs
Pulse width of the spikes that are
tSP suppressed by the analog filter for 0 50(4) 0 50(4) ns
standard fast mode
Cb Capacitive load for each bus line - 400 - 400 pF
1. Specified by design.
2. fPCLK1 must be at least 2 MHz to achieve standard mode I2C frequencies. It must be at least 4 MHz to achieve fast mode
I2C frequencies, and a multiple of 10 MHz to reach the 400 kHz maximum I2C fast mode clock.
3. The maximum data hold time has only to be met if the interface does not stretch the low period of SCL signal.
4. The minimum width of the spikes filtered by the analog filter is above tSP (max).

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Figure 33. I2C bus AC waveforms and measurement circuit

V DD_I2C V DD_I2C

RP RP STM32Fxx
RS
SDA
I²C bus RS
SCL

START REPEATED
START

START
tsu(STA)

SDA
tf(SDA) tr(SDA) tsu(SDA)
STOP tw(STO:STA)
th(STA) tw(SCLH) th(SDA)

SCL
tw(SCLL) tr(SCL) tf(SCL) tsu(STO)

ai14979c

1. RS = series protection resistor.

2. RP = external pull-up resistor.
3. VDD_I2C is the I2C bus power supply.

Table 60. SCL frequency (fPCLK1= 42 MHz, VDD = VDD_I2C = 3.3 V)(1)(2)
I2C_CCR value
fSCL (kHz)
RP = 4.7 kΩ

400 0x8019
300 0x8021
200 0x8032
100 0x0096
50 0x012C
20 0x02EE
1. RP = External pull-up resistance, fSCL = I2C speed
2. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the
tolerance on the achieved speed is ±2%. These variations depend on the accuracy of the external
components used to design the application.

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SPI interface characteristics

Unless otherwise specified, the parameters given in Table 61 for the SPI interface are
derived from tests performed under the ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized in Table 14, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5VDD
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).

Table 61. SPI dynamic characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

Master mode, SPI1/4,

42
2.7 V < VDD < 3.6 V
Slave mode, SPI1/4,
42
2.7 V < VDD < 3.6 V
fSCK Slave transmitter/full-duplex mode,
SPI clock frequency - - 38(2) MHz
1/tc(SCK) SPI1/4, 2.7 V < VDD < 3.6 V
Master mode, SPI1/2/3/4,
21
1.7 V < VDD < 3.6 V
Slave mode, SPI1/2/3/4,
21
1.7 V < VDD < 3.6 V
Duty cycle of SPI clock
Duty(SCK) Slave mode 30 50 70 %
frequency
tw(SCKH)
SCK high and low time Master mode, SPI presc = 2 TPCLK−1.5 TPCLK TPCLK+1.5 ns
tw(SCKL)
tsu(NSS) NSS setup time Slave mode, SPI presc = 2 4TPCLK - - ns
th(NSS) NSS hold time Slave mode, SPI presc = 2 2TPCLK - - ns
tsu(MI) Master mode 0 - - ns
Data input setup time
tsu(SI) Slave mode 2.5 - - ns
th(MI) Master mode 6 - - ns
Data input hold time
th(SI) Slave mode 2.5 - - ns
ta(SO) Data output access time Slave mode 9 - 20 ns
tdis(SO) Data output disable time Slave mode 8 - 13 ns
Slave mode (after enable edge),
- 9.5 13 ns
2.7 V < VDD < 3.6 V
tv(SO) Data output valid time
Slave mode (after enable edge),
- 9.5 17 ns
1.7 V < VDD < 3.6 V
Slave mode (after enable edge),
5.5 - - ns
2.7 V < VDD < 3.6 V
th(SO) Data output hold time
Slave mode (after enable edge),
3.5 - - ns
1.7 V < VDD < 3.6 V

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Table 61. SPI dynamic characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

tv(MO) Data output valid time Master mode (after enable edge) - 3 5 ns
th(MO) Data output hold time Master mode (after enable edge) 2 - - ns
1. Evaluated by characterization.
2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or
high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having tsu(MI) = 0 while Duty(SCK) = 50%

Figure 34. SPI timing diagram - slave mode and CPHA = 0

NSS input

tc(SCK) th(NSS)

tsu(NSS) tw(SCKH)
CPHA=0
SCK input

CPOL=0

CPHA=0
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO)

MISO output First bit OUT Next bits OUT Last bit OUT

tsu(SI) th(SI)

MOSI input First bit IN Next bits IN Last bit IN

MSv41658V2

Figure 35. SPI timing diagram - slave mode and CPHA = 1(1)

NSS input

tc(SCK) th(NSS)
tsu(NSS) tw(SCKH)
CPHA=1
SCK input

CPOL=0

CPHA=1
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO)

MISO output First bit OUT Next bits OUT Last bit OUT

tsu(SI) th(SI)

MOSI input First bit IN Next bits IN Last bit IN

MSv41659V2

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Figure 36. SPI timing diagram - master mode(1)

High

NSS input
tc(SCK)
tw(SCKH)
CPHA=0
SCK output

CPOL=0

CPHA=0
CPOL=1
tw(SCKL)
CPHA=1
SCK output

CPOL=0

CPHA=1
CPOL=1
tsu(MI) th(MI)

MISO input First bit IN Next bits IN Last bit IN

MOSI output First bit OUT Next bits OUT Last bit OUT

tv(MO) th(MO)
MSv72626V1

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I2S interface characteristics

Unless otherwise specified, the parameters given in Table 62 for the I2S interface are
derived from tests performed under the ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized in Table 14, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5VDD
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics (CK, SD, WS).

Table 62. I2S dynamic characteristics(1)

Symbol Parameter Conditions Min Max Unit

fMCK I2S Main clock output - 256x8K 256xFs(2) MHz

Master data: 32 bits - 64xFs
fCK I2S clock frequency MHz
Slave data: 32 bits - 64xFs
DCK I2S clock frequency duty cycle Slave receiver 30 70 %
tv(WS) WS valid time Master mode 0 6
th(WS) WS hold time Master mode 0 -
tsu(WS) WS setup time Slave mode 1 -
th(WS) WS hold time Slave mode 0 -
tsu(SD_MR) Master receiver 7.5 -
Data input setup time
tsu(SD_SR) Slave receiver 2 -
ns
th(SD_MR) Master receiver 0 -
Data input hold time
th(SD_SR) Slave receiver 0 -
tv(SD_ST)
Slave transmitter (after enable edge) - 27
th(SD_ST) Data output valid time
tv(SD_MT) Master transmitter (after enable edge) - 20
th(SD_MT) Data output hold time Master transmitter (after enable edge) 2.5 -
1. Evaluated by characterization.
2. The maximum value of 256xFs is 42 MHz (APB1 maximum frequency).

Note: Refer to the I2S section of the reference manual for more details on the sampling frequency
(FS).
fMCK, fCK, and DCK values reflect only the digital peripheral behavior. The values of these
parameters might be slightly impacted by the source clock precision. DCK depends mainly
on the value of ODD bit. The digital contribution leads to a minimum value of
(I2SDIV/(2*I2SDIV+ODD) and a maximum value of (I2SDIV+ODD)/(2*I2SDIV+ODD). FS
maximum value is supported for each mode/condition.

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Figure 37. I2S slave timing diagram (Philips protocol)(1)

tc(CK)

CK Input CPOL = 0

CPOL = 1

tw(CKH) tw(CKL) th(WS)

WS input

tsu(WS) tv(SD_ST) th(SD_ST)

SDtransmit
LSB transmit(2) MSB transmit Bitn transmit LSB transmit

tsu(SD_SR) th(SD_SR)

SDreceive LSB receive(2) MSB receive Bitn receive LSB receive

ai14881b

1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.

Figure 38. I2S master timing diagram (Philips protocol)(1)

tf(CK) tr(CK)

tc(CK)
CK output

CPOL = 0
tw(CKH)

CPOL = 1
tv(WS) tw(CKL) th(WS)

WS output

tv(SD_MT) th(SD_MT)

SDtransmit LSB transmit(2) MSB transmit Bitn transmit LSB transmit

tsu(SD_MR) th(SD_MR)

SDreceive LSB receive(2) MSB receive Bitn receive LSB receive

ai14884b

1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.

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USB OTG full speed (FS) characteristics

This interface is present in USB OTG FS controller.

Table 63. USB OTG FS startup time

Symbol Parameter Max Unit

tSTARTUP(1) USB OTG FS transceiver startup time 1 µs

1. Specified by design.

Table 64. USB OTG FS DC electrical characteristics

Symbol Parameter Conditions Min.(1) Typ. Max.(1) Unit

USB OTG FS operating

VDD - 3.0(2) - 3.6 V
voltage
VDI(3) Differential input sensitivity I(USB_FS_DP/DM) 0.2 - -
Input
levels Differential common mode
VCM(3) Includes VDI range 0.8 - 2.5
range V
Single ended receiver
VSE(3) - 1.3 - 2.0
threshold

Output VOL Static output level low RL of 1.5 kΩ to 3.6 V(4) - - 0.3
V
levels VOH Static output level high RL of 15 kΩ to VSS(4) 2.8 - 3.6
PA11, PA12
17 21 24
RPD (USB_FS_DM/DP) VIN = VDD
PA9 (OTG_FS_VBUS) 0.65 1.1 2.0
kΩ
PA11, PA12
VIN = VSS 1.5 1.8 2.1
RPU (USB_FS_DM/DP)
PA9 (OTG_FS_VBUS) VIN = VSS 0.25 0.37 0.55
1. All the voltages are measured from the local ground potential.
2. The USB OTG FS functionality is ensured down to 2.7 V but not the full USB full speed electrical
characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range.
3. Specified by design.
4. RL is the load connected on the USB OTG FS drivers.

Note: When VBUS sensing feature is enabled, PA9 should be left at their default state (floating
input), not as alternate function. A typical 200 µA current consumption of the embedded
sensing block (current to voltage conversion to determine the different sessions) can be
observed on PA9 when the feature is enabled.

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Figure 39. USB OTG FS timings: definition of data signal rise and fall time

Cross over
points
Differential
data lines

VCRS

VSS

tf tr
ai14137b

Table 65. USB OTG FS electrical characteristics(1)

Driver characteristics

Symbol Parameter Conditions Min Max Unit

tr Rise time(2) CL = 50 pF 4 20 ns
tf Fall time(2) CL = 50 pF 4 20 ns
trfm Rise/ fall time matching tr/tf 90 110 %
VCRS Output signal crossover voltage - 1.3 2.0 V
1. Specified by design.
2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).

6.3.20 12-bit ADC characteristics

Unless otherwise specified, the parameters given in Table 66 are derived from tests
performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage
conditions summarized in Table 14.

Table 66. ADC characteristics

Symbol Parameter Conditions Min Typ Max Unit

VDDA Power supply 1.7(1) - 3.6

VDDA −VREF+ < 1.2 V
VREF+ Positive reference voltage 1.7(1) - VDDA V
VREF- Negative reference voltage - - 0 -
VDDA = 1.7(1) to 2.4 V 0.6 15 18 MHz
fADC ADC clock frequency
VDDA = 2.4 to 3.6 V 0.6 30 36 MHz
fADC = 30 MHz,
- - 1764 kHz
fTRIG(2) External trigger frequency 12-bit resolution
- - - 17 1/fADC
0 (VSSA or VREF-
VAIN Conversion voltage range(3) - - VREF+ V
tied to ground)
See Equation 1 for
RAIN(2) External input impedance - - 50 κΩ
details
RADC(2)(4) Sampling switch resistance - - - 6 κΩ

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Table 66. ADC characteristics (continued)

Symbol Parameter Conditions Min Typ Max Unit

Internal sample and hold

CADC(2) - 4 7 pF
capacitor

Injection trigger conversion fADC = 30 MHz - - 0.100 µs

tlat(2)
latency - - - 3(5) 1/fADC

Regular trigger conversion fADC = 30 MHz - - 0.067 µs

tlatr(2)
latency - - - 2(5)
1/fADC
fADC = 30 MHz 0.100 - 16 µs
tS(2) Sampling time
- 3 - 480 1/fADC
tSTAB(2) Power-up time - - 2 3 µs
fADC = 30 MHz
0.50 - 16.40 µs
12-bit resolution
fADC = 30 MHz
0.43 - 16.34 µs
10-bit resolution
Total conversion time (including fADC = 30 MHz
tCONV(2) 0.37 - 16.27 µs
sampling time) 8-bit resolution
fADC = 30 MHz
0.30 - 16.20 µs
6-bit resolution
9 to 492 (tS for sampling +n-bit resolution for successive
1/fADC
approximation)
12-bit resolution
- - 2 Msps
Single ADC
12-bit resolution
Sampling rate
Interleave Dual ADC - - 3.75 Msps
fS(2) (fADC = 30 MHz, and
mode
tS = 3 ADC cycles)
12-bit resolution
Interleave Triple ADC - - 6 Msps
mode
ADC VREF DC current
IVREF+(2) consumption in conversion - - 300 500 µA
mode
ADC VDDA DC current
IVDDA(2) consumption in conversion - - 1.6 1.8 mA
mode
1. VDDA minimum value of 1.7 V is possible with the use of an external power supply supervisor (refer to Section 3.14.2:
Internal reset OFF).
2. Evaluated by characterization.
3. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA.
4. RADC maximum value is given for VDD=1.7 V, and minimum value for VDD=3.3 V.
5. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 66.

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Equation 1: RAIN max formula

R AIN
( k – 0.5 )
= ---------------------------------------------------------------
- – R ADC
N+2
f ADC × C ADC × ln ( 2 )

The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of
sampling periods defined in the ADC_SMPR1 register.

Table 67. ADC accuracy at fADC = 18 MHz

Symbol Parameter Test conditions Typ Max(1) Unit

ET Total unadjusted error ±3 ±4

fADC =18 MHz
EO Offset error ±2 ±3
VDDA = 1.7 to 3.6 V
LSB
EG Gain error VREF = 1.7 to 3.6 V ±1 ±3
ED Differential linearity error VDDA −VREF < 1.2 V ±1 ±2
EL Integral linearity error ±2 ±3
1. Evaluated by characterization.

Table 68. ADC accuracy at fADC = 30 MHz

Symbol Parameter Test conditions Typ Max(1) Unit

ET Total unadjusted error ±2 ±5

fADC = 30 MHz,
EO Offset error ±1.5 ±2.5
RAIN < 10 kΩ,
EG Gain error VDDA = 2.4 to 3.6 V, ±1.5 ±4 LSB
VREF = 1.7 to 3.6 V,
ED Differential linearity error ±1 ±2
VDDA −VREF < 1.2 V
EL Integral linearity error ±1.5 ±3
1. Evaluated by characterization.

Table 69. ADC accuracy at fADC = 36 MHz

Symbol Parameter Test conditions Typ Max(1) Unit

ET Total unadjusted error ±4 ±7

EO Offset error fADC =36 MHz, ±2 ±3

VDDA = 2.4 to 3.6 V,
EG Gain error ±3 ±6 LSB
VREF = 1.7 to 3.6 V
ED Differential linearity error VDDA −VREF < 1.2 V ±2 ±3
EL Integral linearity error ±3 ±6
1. Evaluated by characterization.

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Table 70. ADC dynamic accuracy at fADC = 18 MHz - limited test conditions(1)
Symbol Parameter Test conditions Min Typ Max Unit

ENOB Effective number of bits 10.3 10.4 - bits

fADC =18 MHz
Signal-to-noise and distortion
SINAD VDDA = VREF+= 1.7 V 64 64.2 -
ratio
Input Frequency = 20 KHz dB
SNR Signal-to-noise ratio 64 65 -
Temperature = 25 °C
THD Total harmonic distortion -67 -72 -
1. Evaluated by characterization.

Table 71. ADC dynamic accuracy at fADC = 36 MHz - limited test conditions(1)
Symbol Parameter Test conditions Min Typ Max Unit

ENOB Effective number of bits 10.6 10.8 - bits

fADC = 36 MHz
Signal-to noise and distortion VDDA = VREF+ = 3.3 V
SINAD 66 67 -
ratio Input Frequency =
20 KHz dB
SNR Signal-to noise ratio 64 68 -
Temperature = 25 °C
THD Total harmonic distortion -70 -72 -
1. Evaluated by characterization.

Note: ADC accuracy vs. negative injection current: injecting a negative current on any analog
input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to
ground) to analog pins which may potentially inject negative currents.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in
Section 6.3.16 does not affect the ADC accuracy.

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Figure 40. ADC accuracy characteristics

VREF+ VDDA
[1LSB = (or )]
Output code 2n 2n
EG
(1) Example of an actual transfer curve
2n-1 (2) Ideal transfer curve
2n-2 (3) End-point correlation line
2n-3 (2)
n = ADC resolution
ET = total unadjusted error: maximum deviation
(3) between the actual and ideal transfer curves
ET
7 (1) EO = offset error: maximum deviation between the first
actual transition and the first ideal one
6
EL EG = gain error: deviation between the last ideal
5 EO
transition and the last actual one
4 ED = differential linearity error: maximum deviation
ED between actual steps and the ideal one
3
2 EL = integral linearity error: maximum deviation between
1 any actual transition and the end point correlation line
1 LSB ideal
0 VREF+ (VDDA)
(1/2n)*VREF+
(2/2n)*VREF+
(3/2n)*VREF+
(4/2n)*VREF+
(5/2n)*VREF+
(6/2n)*VREF+
(7/2n)*VREF+

(2n-3/2n)*VREF+
(2n-2/2n)*VREF+
(2n-1/2n)*VREF+
(2n/2n)*VREF+
VSSA

MSv19880V6

1. See also Table 68.

2. Example of an actual transfer curve.
3. Ideal transfer curve.
4. End point correlation line.
5. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.
EO = Offset Error: deviation between the first actual transition and the first ideal one.
EG = Gain Error: deviation between the last ideal transition and the last actual one.
ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.
EL = Integral Linearity Error: maximum deviation between any actual transition and the end point
correlation line.

Figure 41. Typical connection diagram when using the ADC with FT/TT pins featuring
analog switch function

VDDA(4) VREF+(4)

I/O Sample-and-hold ADC converter

analog
RAIN(1) switch RADC
Converter

Cparasitic(2) Ilkg(3) CADC

VAIN Sampling
switch with
multiplexing

VSS VSS VSSA

MSv67871V3

1. Refer to Table 66 for the values of RAIN, RADC and CADC.

2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this,
fADC should be reduced.
3. Refer to Table 54: I/O static characteristics for the value of Ilkg.
4. Refer toFigure 18: Power supply scheme.

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General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 42 or Figure 43,
depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be
ceramic (good quality). They should be placed them as close as possible to the chip.

Figure 42. Power supply and reference decoupling (VREF+ not connected to VDDA)

STM32F

VREF+ (1)

1 μF // 10 nF
VDDA

1 μF // 10 nF

(1)
VSSA/VREF-

ai17535b

1. VREF+ and VREF- inputs are both available on UFBGA100. VREF+ is also available on LQFP100. When
VREF+ and VREF- are not available, they are internally connected to VDDA and VSSA.

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Figure 43. Power supply and reference decoupling (VREF+ connected to VDDA)

STM32F

VREF+/VDDA (1)

1 μF // 10 nF

(1)
VREF-/VSSA

ai17536c

1. VREF+ and VREF- inputs are both available on UFBGA100. VREF+ is also available on LQFP100. When
VREF+ and VREF- are not available, they are internally connected to VDDA and VSSA.

6.3.21 Temperature sensor characteristics

Table 72. Temperature sensor characteristics

Symbol Parameter Min Typ Max Unit

TL(1) VSENSE linearity with temperature - ±1 ±2 °C

Avg_Slope(1) Average slope - 2.5 - mV/°C
V25(1) Voltage at 25 °C - 0.76 - V
tSTART(2) Startup time - 6 10 µs
TS_temp(2) ADC sampling time when reading the temperature (1 °C accuracy) 10 - - µs
1. Evaluated by characterization.
2. Specified by design.

Table 73. Temperature sensor calibration values

Symbol Parameter Memory address

TS_CAL1 TS ADC raw data acquired at temperature of 30 °C, VDDA= 3.3 V 0x1FFF 7A2C - 0x1FFF 7A2D
TS_CAL2 TS ADC raw data acquired at temperature of 110 °C, VDDA= 3.3 V 0x1FFF 7A2E - 0x1FFF 7A2F

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6.3.22 VBAT monitoring characteristics

Table 74. VBAT monitoring characteristics

Symbol Parameter Min Typ Max Unit

R Resistor bridge for VBAT - 50 - KΩ

Q Ratio on VBAT measurement - 4 - -
(1)
Er Error on Q –1 - +1 %
ADC sampling time when reading the VBAT
TS_vbat(2)(2) 5 - - µs
1 mV accuracy
1. Specified by design.
2. Shortest sampling time can be determined in the application by multiple iterations.

6.3.23 Embedded reference voltage

The parameters given in Table 75 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 14.

Table 75. Embedded internal reference voltage

Symbol Parameter Conditions Min Typ Max Unit

VREFINT Internal reference voltage –40 °C < TA < + 105 °C 1.18 1.21 1.24 V
ADC sampling time when reading the
TS_vrefint(1) - 10 - - µs
internal reference voltage
Internal reference voltage spread over the
VRERINT_s(2) VDD = 3V ± 10mV - 3 5 mV
temperature range
TCoeff(2) Temperature coefficient - - 30 50 ppm/°C
tSTART(2) Startup time - - 6 10 µs
1. Shortest sampling time can be determined in the application by multiple iterations.
2. Specified by design.

Table 76. Internal reference voltage calibration values

Symbol Parameter Memory address

Raw data acquired at temperature of

VREFIN_CAL 0x1FFF 7A2A - 0x1FFF 7A2B
30 °C VDDA = 3.3 V

6.3.24 SD/SDIO MMC card host interface (SDIO) characteristics

Unless otherwise specified, the parameters given in Table 77 for the SDIO/MMC interface
are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDD
supply voltage conditions summarized in Table 14, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5VDD

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Refer to Section 6.3.16: I/O port characteristics for more details on the input/output
characteristics.

Figure 44. SDIO high-speed mode

tf tr

tC

tW(CKH) tW(CKL)

CK

tOV tOH
D, CMD
(output)

tISU tIH

D, CMD
(input)
ai14887

Figure 45. SD default mode

CK
tOVD tOHD
D, CMD
(output)

ai14888

Table 77. Dynamic characteristics: SD / MMC characteristics(1)(2)

Symbol Parameter Conditions Min Typ Max Unit

fPP Clock frequency in data transfer mode - 0 - 48 MHz

- SDIO_CK/fPCLK2 frequency ratio - - - 8/3 -
tW(CKL) Clock low time fpp = 48MHz 8.5 9 -
ns
tW(CKH) Clock high time fpp = 48MHz 8.3 10 -

CMD, D inputs (referenced to CK) in MMC and SD HS mode

tISU Input setup time HS fpp = 48MHz 3.5 - -

ns
tIH Input hold time HS fpp = 48MHz 0 - -

CMD, D outputs (referenced to CK) in MMC and SD HS mode

tOV Output valid time HS fpp = 48MHz - 4.5 7

ns
tOH Output hold time HS fpp = 48MHz 3 - -

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Table 77. Dynamic characteristics: SD / MMC characteristics(1)(2) (continued)

Symbol Parameter Conditions Min Typ Max Unit

CMD, D inputs (referenced to CK) in SD default mode

tISUD Input setup time SD fpp = 24MHz 1.5 - -

ns
tIHD Input hold time SD fpp = 24MHz 0.5 - -

CMD, D outputs (referenced to CK) in SD default mode

tOVD Output valid default time SD fpp =24MHz - 4.5 6.5

ns
tOHD Output hold default time SD fpp =24MHz 3.5 - -
1. Evaluated by characterization results.
2. VDD = 2.7 to 3.6 V.

6.3.25 RTC characteristics

Table 78. RTC characteristics

Symbol Parameter Conditions Min Max

Any read/write operation

- fPCLK1/RTCCLK frequency ratio 4 -
from/to an RTC register

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7 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.

7.1 Device marking

Refer to technical note “Reference device marking schematics for STM32 microcontrollers
and microprocessors” (TN1433) available on www.st.com, for the location of pin 1 / ball A1
as well as the location and orientation of the marking areas versus pin 1 / ball A1.
Parts marked as “ES”, “E” or accompanied by an engineering sample notification letter, are
not yet qualified and therefore not approved for use in production. ST is not responsible for
any consequences resulting from such use. In no event will ST be liable for the customer
using any of these engineering samples in production. ST’s Quality department must be
contacted prior to any decision to use these engineering samples to run a qualification
activity.

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7.2 WLCSP49 package information (A0ZV)

This WLCSP is a 49-ball, 2.999 x 3.185 mm, 0.4 mm pitch wafer level chip scale

Figure 46. WLCSP49 - Outline

e1
bbb Z
F
A1 ball location
7 1
A

G
Detail A
e2 E
e

G
A
e A2

Bump side Side view

A3

Front view Bump

D
A1
eee Z

b
Seating plane
E ccc Z XY Note 1
A1 orientation ddd Z
reference Note 2
Detail A
(rotated 90 °)
aaa
(4X)

Wafer back side A0ZV_ME_V1

1. Drawing is not to scale.

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Table 79. WLCSP49 - Mechanical data

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max
A 0.525 0.555 0.585 0.0207 0.0219 0.0230
A1 - 0.175 - - 0.0069 -
A2 - 0.380 - - 0.0150 -
(2)
A3 - 0.025 - - 0.0010 -
b(3) 0.220 0.250 0.280 0.0087 0.0098 0.0110
D 2.964 2.999 3.034 0.1167 0.1181 0.1194
E 3.150 3.185 3.220 0.1240 0.1254 0.1268
e - 0.400 - - 0.0157 -
e1 - 2.400 - - 0.0945 -
e2 - 2.400 - - 0.0945 -
F - 0.2995 - - 0.0118 -
G - 0.3925 - - 0.0155 -
aaa - - 0.100 - - 0.0039
bbb - - 0.100 - - 0.0039
ccc - - 0.100 - - 0.0039
ddd - - 0.050 - - 0.0020
eee - - 0.050 - - 0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Back side coating
3. Dimension is measured at the maximum bump diameter parallel to primary datum Z.

Figure 47. WLCSP49 - Footprint example

Dpad
Dsm MS18965V2

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Table 80. WLCSP49 - Example of PCB design rules (0.4 mm pitch)

Dimension Recommended values
Pitch 0.4
260 µm max. (circular)
Dpad
220 µm recommended
Dsm 300 µm min. (for 260 µm diameter pad)
PCB pad design Non-solder mask defined via underbump allowed.

Device marking for WLCSP49

The following figure gives an example of topside marking orientation versus ball A1 identifier
location. The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.

Figure 48. WLCSP49 marking(package top view)

Ball 1
indentifier

Product identification(1)
F401CD6

Revision code
Date code

Y WW R

MSv37216V1

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.

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7.3 UFQFPN48 package information (A0B9)

This UFQFPN is a 48-lead, 7 x 7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package.

Figure 49. UFQFPN48 – Outline

D1 EXPOSED PAD

E2 E1
e

PIN 1 idenfier
L
D2
BOTTOM VIEW
A
A3
A1
SEATING PLANE

C
DETAIL A
ddd C
LEADS COPLANARITY
FRONT VIEW

A1 A
SEATING PLANE

ddd C
PIN 1 IDENTIFIER C
LASER MAKER AREA

TOP VIEW

A0B9_UFQFPN48_ME_V4

1. Drawing is not to scale.

2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN48 package. It is recommended to connect
and solder this back-side pad to PCB ground.

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Table 81. UFQFPN48 – Mechanical data

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A 0.500 0.550 0.600 0.0197 0.0217 0.0236

A1 0.000 0.020 0.050 0.0000 0.0008 0.0020
A3 - 0.152 - - 0.0060 -
b 0.200 0.250 0.300 0.0079 0.0098 0.0118
(2)
D 6.900 7.000 7.100 0.2717 0.2756 0.2795
D1 5.400 5.500 5.600 0.2126 0.2165 0.2205
D2(3) 5.500 5.600 5.700 0.2165 0.2205 0.2244
(2)
E 6.900 7.000 7.100 0.2717 0.2756 0.2795
E1 5.400 5.500 5.600 0.2126 0.2165 0.2205
E2(3) 5.500 5.600 5.700 0.2165 0.2205 0.2244
e - 0.500 - - 0.0197 -
L 0.300 0.400 0.500 0.0118 0.0157 0.0197
ddd - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Dimensions D and E do not include mold protrusion, not exceed 0.15 mm.
3. Dimensions D2 and E2 are not in accordance with JEDEC.

Figure 50. UFQFPN48 – Footprint example

7.30

6.20

48 37

1 36

0.20 5.60

7.30
5.80
6.20

5.60
0.30

12 25

13 24

0.50 0.75
0.55
5.80 A0B9_UFQFPN48_FP_V3

1. Dimensions are expressed in millimeters.

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Figure 51. UFQFPN48 marking example (package top view)

Product identification(1)
STM32F

401CDU6

Date code

Y WW

Pin 1
indentifier Revision code
R

MSv36196V1

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.

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7.4 LQFP64 package information (5W)

This LQFP is 64-pin, 10 x 10 mm low-profile quad flat package.
Note: See list of notes in the notes section.

Figure 52. LQFP64 - Outline(15)

BOTTOM VIEW

2 1
(2)
R1

H
R2

B
B-
N
O
TI
C
SE
B GAUGE PLANE
D 1/4

0.25
(6)
S
B
L
4x N/4 TIPS
E 1/4 3
(L1)
aaa C A-B D (1) (11)
bbb H A-B D 4x
SECTION A-A

(13) (N – 4)x e

C
A
0.05
A2 A1 (12)
b
ddd C A-B D ccc C

D (4)

(5) (2) D1 (9) (11)

(10)
D (3) b WITH PLATING
N (4)

1 E 1/4 (11) (11)

2
3 c c1
(3) A (6) B (3) (5)
D 1/4 (2)
E1 E b1 BASE METAL
(11)

A A SECTION B-B
(Section A-A)

TOP VIEW 5W_LQFP64_ME_V1

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Table 82. LQFP64 - Mechanical data

millimeters inches(14)
Symbol
Min Typ Max Min Typ Max
A - - 1.60 - - 0.0630
A1(12) 0.05 - 0.15 0.0020 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0570
(9)(11)
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
(11)
b1 0.17 0.20 0.23 0.0067 0.0079 0.0091
c(11) 0.09 - 0.20 0.0035 - 0.0079
c1(11) 0.09 - 0.16 0.0035 - 0.0063
(4)
D 12.00 BSC 0.4724 BSC
(2)(5)
D1 10.00 BSC 0.3937 BSC
E(4) 12.00 BSC 0.4724 BSC
(2)(5)
E1 10.00 BSC 0.3937 BSC
e 0.50 BSC 0.1970 BSC
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.00 REF 0.0394 REF
N(13) 64
θ 0° 3.5° 7° 0° 3.5° 7°
θ1 0° - - 0° - -
θ2 10° 12° 14° 10° 12° 14°
θ3 10° 12° 14° 10° 12° 14°
R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
(1)
aaa 0.20 0.0079
(1)
bbb 0.20 0.0079
(1)
ccc 0.08 0.0031
ddd(1) 0.08 0.0031

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Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The Top package body size may be smaller than the bottom package size by as much
as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at seating datum plane C.
5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size
dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All Dimensions are in millimeters.
8. No intrusion allowed inwards the leads.
9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. “N” is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to 4 decimal digits.
15. Drawing is not to scale.

Figure 53. LQFP64 - Footprint example

48 33

0.30
49 0.5 32

12.70

10.30

10.30
64 17

1.20
1 16

7.80

12.70
5W_LQFP64_FP_V2

1. Dimensions are expressed in millimeters.

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7.5 LQFP100 package information (1L)

This LQFP is 100 lead, 14 x 14 mm low-profile quad flat package.
Note: See list of notes in the notes section.

Figure 54. LQFP100 - Outline(15)

ș2 ș
(2)
R1

H
R2

B
B-
N
O
(6)

TI
C
SE
D1/4 B GAUGE PLANE

S
E1/4
B ș
4x N/4 TIPS
ș L
4x (L1)
aaa C A-B D
bbb H A-B D (1) (11)

BOTTOM VIEW SECTION A-A

(N-4) x e (13)

C
A (9) (11)
0.05
ccc C b WITH PLATING
A2 A1 b aaa C A-BD
(12)

SIDE VIEW

D (4)
(11) c
(2) (5) D1 c1 (11)

D (3)
(10) (4)
N

b1 BASE METAL
1 (11)
2
3 E1/4 SECTION B-B

D1/4 (6) (2)

A B
(5)

E1 E

SECTION A-A

A A

TOP VIEW 1L_LQFP100_ME_V3

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Table 83. LQFP100 - Mechanical data

millimeters inches(14)
Symbol
Min Typ Max Min Typ Max

A - 1.50 1.60 - 0.0590 0.0630

(12)
A1 0.05 - 0.15 0.0019 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0570
(9)(11)
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
(11)
b1 0.17 0.20 0.23 0.0067 0.0079 0.0090
(11)
c 0.09 - 0.20 0.0035 - 0.0079
c1(11) 0.09 - 0.16 0.0035 - 0.0063
(4)
D 16.00 BSC 0.6299 BSC
(2)(5)
D1 14.00 BSC 0.5512 BSC
E(4) 16.00 BSC 0.6299 BSC
E1(2)(5) 14.00 BSC 0.5512 BSC
e 0.50 BSC 0.0197 BSC
L 0.45 0.60 0.75 0.177 0.0236 0.0295
(1)(11)
L1 1.00 - 0.0394 -
N(13) 100
θ 0° 3.5° 7° 0° 3.5° 7°

θ1 0° - - 0° - -

θ2 10° 12° 14° 10° 12° 14°

θ3 10° 12° 14° 10° 12° 14°

R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
aaa(1) 0.20 0.0079
(1)
bbb 0.20 0.0079
ccc(1) 0.08 0.0031
(1)
ddd 0.08 0.0031

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Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The Top package body size may be smaller than the bottom package size by as much
as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at seating datum plane C.
5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size
dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All Dimensions are in millimeters.
8. No intrusion allowed inwards the leads.
9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. “N” is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to 4 decimal digits.
15. Drawing is not to scale.

Figure 55. LQFP100 - Footprint example

75 51

76 50
0.5

0.3

16.7 14.3

100 26

1.2
1 25

12.3

16.7

1L_LQFP100_FP_V1

1. Dimensions are expressed in millimeters.

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7.6 UFBGA100 package information (A0C2)

This UFBGA is a 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package.
Note: See list of notes in the notes section.

Figure 56. UFBGA100 - Outline(13)

E1

e SE

M
L
K
SD J
H
G
D1
F
E
D
C
e
B
A

A1 ball pad 1 2 3 4 5 6 7 8 9 10 11 12
corner Øb (N balls)
BOTTOM VIEW Ø eee M C A B
Ø fff M C

DETAIL A

Mold resin
A ccc C
SIDE VIEW
C
Substrate

B E
A
A1 ball pad
corner
(9)
Seating plane
(8)

(DATUM A) A1 A2
C
Detail A
D ddd C
Solder balls

(DATUM B)

aaa C
TOP VIEW (4X)
A0C2_UFBGA_ME_V8

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Table 84. UFBGA100 - Mechanical data

millimeters(1) inches(12)
Symbol
Min. Typ. Max. Min. Typ. Max.

A(2)(3) - - 0.60 - - 0.0236

(4)
A1 0.05 - - 0.0020 - -
A2 - 0.43 - - 0.0169 -
(5)
b 0.23 0.28 0.33 0.0090 0.0110 0.0130
(6)
D 7.00 BSC 0.2756 BSC
D1 5.50 BSC 0.2165 BSC
E 7.00 BSC 0.2756 BSC
E1 5.50 BSC 0.2165 BSC
(9)
e 0.50 BSC 0.0197 BSC
N(11) 100
SD(12) 0.25 BSC 0.0098 BSC
SE(12) 0.25 BSC 0.0098 BSC
aaa 0.15 0.0059
ccc 0.20 0.0079
ddd 0.08 0.0031
eee 0.15 0.0059
fff 0.05 0.0020

Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-2009 apart
European projection.
2. UFBGA stands for ulta profile fine pitch ball grid array: 0.50 mm < A ≤ 0.65 mm / fine
pitch e < 1.00 mm.
3. The profile height, A, is the distance from the seating plane to the highest point on the
package. It is measured perpendicular to the seating plane.
4. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
5. Dimension b is measured at the maximum diameter of the terminal (ball) in a plane
parallel to primary datum C.
6. BSC stands for BASIC dimensions. It corresponds to the nominal value and has no
tolerance. For tolerances refer to form and position table. On the drawing these
dimensions are framed.
7. Primary datum C is defined by the plane established by the contact points of three or
more solder balls that support the device when it is placed on top of a planar surface.
8. The terminal (ball) A1 corner must be identified on the top surface of the package by
using a corner chamfer, ink or metalized markings, or other feature of package body or

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STM32F401xD STM32F401xE Package information

integral heat slug. A distinguish feature is allowable on the bottom surface of the
package to identify the terminal A1 corner. Exact shape of each corner is optional.
9. e represents the solder ball grid pitch.
10. N represents the total number of balls on the BGA.
11. Basic dimensions SD and SE are defined with respect to datums A and B. It defines the
position of the centre ball(s) in the outer row or column of a fully populated matrix.
12. Values in inches are converted from mm and rounded to 4 decimal digits.
13. Drawing is not to scale.

Figure 57. UFBGA100 - Footprint example

Dpad

Dsm
BGA_WLCSP_FT_V1

Table 85. UFBGA100 - Example of PCB design rules (0.5 mm pitch BGA)
Dimension Values

Pitch 0.50 mm
Dpad 0.280 mm
0.370 mm typ. (depends on the solder mask
Dsm
registration tolerance)
Stencil opening 0.280 mm
Stencil thickness Between 0.100 mm and 0.125 mm

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7.7 Thermal characteristics

The maximum chip junction temperature (TJmax) must never exceed the values given in
Table 14: General operating conditions on page 60.
The maximum chip-junction temperature, TJ max., in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max x ΘJA)
Where:
• TA max is the maximum ambient temperature in °C,
• ΘJA is the package junction-to-ambient thermal resistance, in ° C/W,
• PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
• PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.

Table 86. Package thermal characteristics

Symbol Parameter Value Unit

Thermal resistance junction-ambient

32
UFQFPN48
Thermal resistance junction-ambient
WLCSP49
Thermal resistance junction-ambient
ΘJA 50 °C/W
LQFP64
Thermal resistance junction-ambient
42
LQFP100
Thermal resistance junction-ambient
UFBGA100

7.7.1 Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.

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STM32F401xD STM32F401xE Ordering information

8 Ordering information

Table 87. Ordering information scheme

Example:STM32F401 C E Y6TR

Device family
STM32 = Arm-based 32-bit microcontroller

Product type
F = General-purpose

Device subfamily
401 = 401 family

Pin count
C = 48/49 pins
R = 64 pins
V = 100 pins

Flash memory size

D = 384 Kbytes of Flash memory
E = 512 Kbytes of Flash memory

Package
H = UFBGA
T = LQFP
U = UFQFPN
Y = WLCSP

Temperature range
6 = Industrial temperature range, –40 to 85 °C

Packing
TR = tape and reel
No character = tray or tube

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Ordering information STM32F401xD STM32F401xE

Table 88. Device order codes

Reference Order codes

STM32F401CDY6, STM32F401RDT6, STM32F401VDT6, STM32F401CDU6,

STM32F401xD
STM32F401VDH6
STM32F401CEY6, STM32F401RET6, STM32F401VET6, STM32F401CEU6,
STM32F401xE
STM32F401VEH6

For a list of available options (memory, package, and so on) or for further information on any
aspect of this device, contact the nearest ST sales office.

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STM32F401xD STM32F401xE Important security notice

9 Important security notice

The STMicroelectronics group of companies (ST) places a high value on product security,
which is why the ST product(s) identified in this documentation may be certified by various
security certification bodies and/or may implement our own security measures as set forth
herein. However, no level of security certification and/or built-in security measures can
guarantee that ST products are resistant to all forms of attacks. As such, it is the
responsibility of each of ST's customers to determine if the level of security provided in an
ST product meets the customer needs both in relation to the ST product alone, as well as
when combined with other components and/or software for the customer end product or
application. In particular, take note that:
• ST products may have been certified by one or more security certification bodies, such
as Platform Security Architecture (www.psacertified.org) and/or Security Evaluation
standard for IoT Platforms (www.trustcb.com). For details concerning whether the ST
product(s) referenced herein have received security certification along with the level
and current status of such certification, either visit the relevant certification standards
website or go to the relevant product page on www.st.com for the most up to date
information. As the status and/or level of security certification for an ST product can
change from time to time, customers should re-check security certification status/level
as needed. If an ST product is not shown to be certified under a particular security
standard, customers should not assume it is certified.
• Certification bodies have the right to evaluate, grant and revoke security certification in
relation to ST products. These certification bodies are therefore independently
responsible for granting or revoking security certification for an ST product, and ST
does not take any responsibility for mistakes, evaluations, assessments, testing, or
other activity carried out by the certification body with respect to any ST product.
• Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open
standard technologies which may be used in conjunction with an ST product are based
on standards which were not developed by ST. ST does not take responsibility for any
flaws in such cryptographic algorithms or open technologies or for any methods which
have been or may be developed to bypass, decrypt or crack such algorithms or
technologies.
• While robust security testing may be done, no level of certification can absolutely
guarantee protections against all attacks, including, for example, against advanced
attacks which have not been tested for, against new or unidentified forms of attack, or
against any form of attack when using an ST product outside of its specification or
intended use, or in conjunction with other components or software which are used by
customer to create their end product or application. ST is not responsible for resistance
against such attacks. As such, regardless of the incorporated security features and/or
any information or support that may be provided by ST, each customer is solely
responsible for determining if the level of attacks tested for meets their needs, both in
relation to the ST product alone and when incorporated into a customer end product or
application.
• All security features of ST products (inclusive of any hardware, software,
documentation, and the like), including but not limited to any enhanced security
features added by ST, are provided on an "AS IS" BASIS. AS SUCH, TO THE EXTENT
PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the
applicable written and signed contract terms specifically provide otherwise.

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Revision history STM32F401xD STM32F401xE

10 Revision history

Table 89. Document revision history

Date Revision Changes

16-Jan-2014 1 Initial release.

Updated Flash memory size in Table 2:
STM32F401xD/xE features and peripheral counts.
24-Feb-2014 2
Added alternate functions mapped on PCx, PDx and
PEx GPIOS in Table 9: Alternate function mapping

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STM32F401xD STM32F401xE Revision history

Table 89. Document revision history (continued)

Date Revision Changes

Updated UFQFPN48 in Table 3: Regulator ON/OFF and

internal power supply supervisor availability.
Updated number of EXTI lines in Section 3.10: External
interrupt/event controller (EXTI).
Updated Table 54: I/O static characteristics
Added WLCSP49 Figure 47: WLCSP49 0.4 mm pitch
wafer level chip size recommended footprint and
Table 80: WLCSP49 recommended PCB design rules
(0.4 mm pitch). Updated Figure 48: Example of
WLCSP49 marking (top view).
22-Jan-2015 3
Updated Figure 51: Example of UFQFPN48 marking
(top view).
Updated Figure 54: Example of LQFP64 marking (top
view).
Updated Figure 57: Example of LQPF100 marking (top
view).
Updated Figure 60: Example of UFBGA100 marking
(top view).
Added notes below all engineering sample marking
schematics.
Updated:
List of features
Section 1: Introduction
Section 3.4: Embedded flash memory
Section 6.2: Absolute maximum ratings
Table 11: Voltage characteristics
Table 19: Embedded reset and power control block
characteristics
Section 6.3.6: Supply current characteristics
Table 39: HSI oscillator characteristics
24-Jan-2025 4 Figure 26: ACCHSI versus temperature
Table 49: EMI characteristics for WLCSP49
Table 50: EMI characteristics for LQFP100
Section 6.3.16: I/O port characteristics
Figure 34: SPI timing diagram - slave mode and CPHA
=0
Figure 35: SPI timing diagram - slave mode and CPHA
= 1(1)
Figure 40: ADC accuracy characteristics
Figure 41: Typical connection diagram when using the
ADC with FT/TT pins featuring analog switch function
Section 9: Important security notice

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IMPORTANT NOTICE – READ CAREFULLY

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138/138 DS10086 Rev 4