3.1.6_CPEN120_Introduction to HDL
3.1.6_CPEN120_Introduction to HDL
have the knowledge and understanding of engineering and management principles as a member and leader in a team, to manage projects and
l / / /
in multidisciplinary environments;
vi have the ability to demonstrate a mark of excellence, a testimony of faith, and a heart of service (SCCGTI Vision); and / / /
vii have the ability to manifest commitment to holistic life education of excellence for the service of God and men (SCCGTI Philosophy and Mission. / / /
COURSE OUTCOME AND RELATIONSHIP TO PROGRAM OUTCOMES
Program Outcomes
SN Course Outcome
i ii iii iv v a b c d e f g h i j k l vi vii
Use Hardware Description Language (HDL) to emulate hardware logic gate operation,
1 E E E / /
establish data flows, and model desired logic behavior.
2 Simulate hardware designs using HDL and verify the results. E E E / /
3 Synthesize and test designs on Programmable Logic Device (PLD) hardware E E E / /
Legend: I (Introductory Course); E (Enabling Course); D (Demonstrating Course)
COURSE CONTENT AND COVERAGE
Mode
Teaching and
Wk No. of Intended Learning Outcome of Resources / Outcome-Based Date of
Topic Learning
No. Hrs. (ILO) Learnin References Assessment (OBA) Submission
Activities (TLA)
g
1 1 At the end of the orientation, the Course Orientation Group Discussion Face-to- Course Syllabus Reflective Essay Week 1
students should be able to: -Class Policies and Face
1. familiarize the policies, guidelines
guidelines, and their -Grading System
obligations as students -Requirements
of SCCGTI; -Course Description
-Relevance of the course
2-3 2 At the end of the chapter, the Introduction to Verilog Interactive Face-to- See References Quiz on Verilog syntax, data Week 3
students should be able to: HDL discussion Face Section types, and module structure.
1. Explain the role of
Verilog HDL in digital Computer Hands-on lab where
design and FPGA Assisted students write and simulate
development. Instruction/ a simple Verilog module
2. Write and simulate Learning (e.g., a 2-input AND gate)
basic Verilog modules. using simulation tools like
ModelSim or Xilinx Vivado.
4-5 At the end of the chapter, the Gate Level Modeling Interactive Face-to- See References Practical assessment where Week 5
students should be able to: discussion Face Section students code and simulate
1. Implement basic logic combinational logic circuits
circuits using Verilog Computer (e.g., half-adder, full-adder,
gate-level modeling. Assisted multiplexer) using gate-level
2. Simulate and verify the Instruction/ modeling.
functionality of Learning
combinational circuits. Troubleshooting exercise
where students debug errors
in gate-level Verilog code.
6-8 At the end of the chapter, the Behavioral Modeling Interactive Face-to- See References coding exercise where Week 8
students should be able to: discussion Face Section students implement a 4-bit
1. Describe digital circuits ALU using behavioral
using behavioral Verilog Computer modeling.
constructs (e.g., always, Assisted
if-else, case). Instruction/ lab session requiring
2. Develop testbenches to Learning students to write and
validate circuit execute testbenches for a
functionality. given Verilog design.
9 MIDTERM WEEK
10-13 18 At the end of the chapter, the Switch Level Modeling Interactive Face-to- See References Simulation task where Week 13
students should be able to: discussion Face Section students model a CMOS
1. Explain the concept of inverter and basic logic
switch-level abstraction Computer gates using switch-level
in Verilog. Assisted Verilog.
2. Design and simulate Instruction/
simple circuits using Learning Comparative analysis
MOS switch-level assignment where students
modeling. evaluate gate-level vs.
switch-level modeling in
terms of abstraction and
efficiency.
13-17 18 At the end of the chapter, the Sequential Circuit Interactive Face-to- See References practical assessment where Week 17
students should be able to: Description discussion Face Section students design and
See College Student Handbook, and Academic Guidelines and Policies for College Departments/Units.
REFERENCES
From the Accessions:
• Digital Design with an Introduction to the Verilog HDL by M. Morris Mano, Michael D. Ciletti
REVISION HISTORY
Revision No. Date of Revision Date of Implementation Highlight/s of Revision
0 - First Semester, AY 2021-2022 -
Prepared by: Reviewed by: Approved by:
Signature
Name RAYMART B. ESGUERRA DANIEL A. VILLANUEVA, CCpE, MEP-CpE ELLA MAE H. GIMAO
Designation Assistant Professor I Department Head and Program Leader Asst. HED Administrator, ACER
Department/Unit Department of Engineering Department of Engineering Higher Education Department
Email Address [email protected] [email protected] [email protected]
Date Signed