Hardware interrupt

• These interrupts occur as signals on the external pins of the microprocessor

• 8086 has two pins to accept hardware interrupts: NMI and INTR
Software interrupt
• These interrupts are caused by writing the software interrupt instruction INT n
• Value ‘n’ can be from 0 to 255 i.e. from (00)H to (FF)H
• 256 interrupts can be invoked by software
Error conditions (Exceptions)
• 8086 is interrupted when some special conditions occur during execution
• For example: An error in division automatically causes the INT 0 interrupt

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• An interrupt is a special condition (asynchronous event) that arises during the
working of a microprocessor
• Microprocessor temporarily suspends the current main program execution
• Microprocessor then branches to a special program to service that interrupt
• This special program is called as Interrupt Service Routine (ISR)
• ISR is executed to service that interrupt
• Once interrupt serviced, microprocessor returns back to the earlier main
program (to the return address)

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 • 8086 has 256 interrupt types (Type-0 to 255)
i.e. (00)H to (FF)H
• IVT reserves four bytes/locations per interrupt
• IVT holds INT vector addresses called as Pointers
• Hence, IVT Size = 256 × 4 = 1024 bytes = 1 KB
• For interrupt type 'N', the pointer in IVT is present at an
address '4N'
• 4 locations for New values of IP & CS:
4N, 4N+1, 4N+2, 4N+3
• This Interrupt Type Pointer (2 words) has:
• New value of IP-register at lower 2 locations
• New value of CS-regsiter at upper 2 locations
• These new values of CS & IP registers define the 20 bit
IVT is mapped in memory physical address of the ISR
from (00000)H to (003FF)H
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Dedicated/Pre-defined interrupts (INT 0 to INT 4)
• Interrupts are dedicated for specific use only
Reserved interrupts (INT 5 to INT 31)
• Interrupts reserved by Intel and are used in higher processors like 80386,
Pentium etc.
• They are not available to the user for servicing interrupt driven devices
Available interrupts (INT 32 to INT 255)
• User defined, software interrupts used for servicing interrupt driven devices
• ISRs for these interrupts are written by the users to service various devices or
conditions
• These interrupts are invoked by writing the instruction INT N
• ISR address is obtained by the Processor from location 4N in the IVT

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INT 0 (Divide Error)
• INT 0 interrupt occurs on division error i.e. when the result of a division is too large to be stored in the
destination accumulator
• Occurs when very large number is divided by very small number (or zero)
• ISR address is stored at location 0 x 4 = (00000)H in the IVT
INT 1 (Single Step)
• INT 1 interrupt occurs after execution of every instruction if TF = 1
• Processor works in single stepping mode i.e. the microprocessor pauses after executing every
instruction
• Used for debugging the code line by line
• ISR generally displays contents of all registers
• ISR address is stored at location 1 x 4 = (00004)H in the IVT
INT 2 (Non mask-able Interrupt)
• INT 2 interrupt is internally generated when Processor receives interrupt on the NMI pin
• ISR address is stored
Monday, September 14, 2020 at location 2 x 4 = (00008)
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INT 3 (Breakpoint Interrupt)
• INT 3 interrupt instruction is used to cause/insert breakpoints in the program
• Breakpoint inserted by writing INT 03H instruction in the program
• Useful in debugging large programs where single stepping is inefficient
• Performs the debugging in block by block manner
• ISR generally displays contents of all registers
• ISR address is stored at location 3 x 4 = (12)10 = (0000C)H in the IVT
INT 4 (Overflow Interrupt)
• INT 4 interrupt occurs if the overflow flag is set (OF = 1)
AND
Processor executes the INTO (Interrupt on Overflow) instruction
• Used to detect overflow error in signed arithmetic operations
• Its ISR address is stored at location 4 x 4 = (16)10 = (00010)H in the IVT
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 1. Interrupt is sensed in MAINLINE PROGRAM
2. Mainline program environment is stored onto the
stack (by PUSH-ing FLAG, CS & IP registers) by
decrementing the stack address twice each time
3. ISR starting address (pointer giving new values of
IP & CS registers) is fetched from the IVT
4. Processor loads new values into IP & CS register
5. Processor now branches to execute ISR
6. ISR executed like normal program (INT serviced)
7. At end of ISR, IRET (Interrupt return) is executed
8. From Top of the Stack, Processor retrieves (POPs)
the earlier mainline program environment into IP,
CS & FLAG registers in reverse order
9. Processor resumes the MAINLINE PROGRAM again

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