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Power diodes are designed for high-voltage and high-current applications, differing from signal diodes primarily in their structural features, such as the presence of a lightly doped n layer that aids in managing breakdown voltage. They exhibit specific characteristics like forward current behavior and reverse recovery time, which are critical for their performance in various applications. Power diodes are classified into types such as general-purpose, fast recovery, and Schottky diodes, each with distinct operational features and applications.
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0% found this document useful (0 votes)
20 viewsunit 1 PE
Power diodes are designed for high-voltage and high-current applications, differing from signal diodes primarily in their structural features, such as the presence of a lightly doped n layer that aids in managing breakdown voltage. They exhibit specific characteristics like forward current behavior and reverse recovery time, which are critical for their performance in various applications. Power diodes are classified into types such as general-purpose, fast recovery, and Schottky diodes, each with distinct operational features and applications.
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S KotpalCopyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
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/ 29
Power diodes differ in structure from signal diodes. A signal diode constitutes a simpie p-n
junction as shown in Fig. 2.1. The intricacies in constructing power diodes arise from the need
to make them suitable for high-voltage and high-current applications.
‘The practical realization and the resulting structure of a power diode is shown in Fig. 22
(a). It consists of heavily doped n* substrate”. On this substrate, a lightly doped n™ layer is
epitexially grown. Now a heavily doped p* layer on
is diffused’ into n™ layer to form the anode-of~ |
power diode, Fig. 2.2 (a). This shows that n™ |
layer is the basic structural feature not found in ae
signal diodes. The function of n™ layer is to = ons POE
absorb the depletion layer of the reverse biased | 77 ! ron
p’n” junction J,. The break-down voltage. , :
needed in a power diode governs the thickness :
of n” layer ; greater the breakdown voltage, - :
more the n° layer thickness. The drawback of ected Lo
n layer is to add significant ohmic resistance to (a (v)
the diode when it is conducting a forward
Current This leads tolarge power dissipation in Fig, 2.2. (a) Structural features of power diode
the diode ; so proper cooling arrangements in ‘and (6) its circuit symbol.
large diode ratings are essential.
‘material on which something grows.
Le = he |
Power Electoncy
diodat® ut #7mbol of a power diode, shown in Fig. 2.2 (6, isthe same as that for signal
2 [are 23)
‘The modifications in the context of diod
of diode, presented above, makes them appropriate for
‘Neh-power applications As diode, or p-n junction, isthe baie building block ofa
semiconductor devices; same basic modifications should be implemented in all low hort,
Semiconductor devices in order to raise their power-handling capabilities,
POWER DIODES
ed before, power diode is a two-terminal, pn semiconductor device. The two
{frminals of diode are called anode and cathode, Fig. 22 (b) and Fig. 2.3 (a). Two important
characteristics of power diodes are now described
2.3.1. Diode i-v Characteristics’
When anode is positive with respect to cathode, diode is said to be forward biased. With
Increase of the source voltage V, from zero value, intially diode current is zero. From V, =0 to
cut-in voltage, the forward-diode current is very small, Cut-in voltage is also known as
threshold voltage or turn-on voltage. Beyond eut-in voltage, the diode current rises rapidly and
the diode is said to conduct. For silicon diode, the cut-n voltage is around 0.7 V. When diode
‘conducts, there isa forward voltage drop of the order of 0.8 to 1 V.
For low-power diodes, current in the forward direction increases first exponentially with
voltage and then becomes almost linear as shown in Fig. 2.3 (b). For power diodes, the forward
current grows almost linearly with voltage, Fig. 2.3 (¢). The high magnitude of current in a
‘Power diode leads to ohmic drops that hide the exponential part of-v curve. The n” region, or
drift region, forms a considerable drop in the ohmic resistance of power diodes.
[reve ene |! I
= ye
@ ® | a |
2 eee
ria of ea fren te the nage
acd fh ee rete un de
Boma autre write 0 caracteritice ransistors (art
Power Semiconductor Diodes and Transistors tA 28)
power diode and Vpgq. For an ideal diode, the characteristics are shown in Fig, 2:3(d) Here,
voltage drop across conducting diode, vp = 0, reverse leakage current = 0, cut-in voltage = 0 and
reverse breakdown voltage Vany is infinite
Diode manufacturers also indicate the value of peak inverse voltage (PIV) of a diode. This
is the largest reverse voltage to which a die may be subjected during its working PIV i the
same a8 Van.
‘The power diodes are now available with forward current ratings of 1Ato several thousand
amperes and with reverse vatage rating of 50 Vt 500 Vo my
Zt Diode Reverse Recovery Characavistix
After the forward diode curent desays iy othe dad continues to cond nthe reverse
rection becaute OF the pressure of sored charges in the depletion region and the
semiconductor layers. The Faerse surren Nowy for «ne called revere recvery Ue
‘The diode regaine its blocking capability until reverse recovery current decays to ze. The
reese ects Hine i nel tine beeen the nan fas ect
8 zero andthe instant reverse recovery current decays to 25% of ta reverse peak valve
Tr 88 shown in Fig. 24 (a. Se eget oe vs
The reverse recovery time is compote of two segments of time f and ts. by = +
‘Time f, is the time between zero crossing of forward current and peak reverse current lye
During the time f, charge stored in depletion ayer i removed. Time fis measured from the
instant of reverse peak vale fy to
the instant when 025 ny ie reached, r
Fig, 24 (a). During ty charg from
the semiconductor layers is removed.
aded area in Fig. 24 (@)
epresents the stored charge, oF
Feveree recovery charge, Qy Which
most be removed during the reverse
eeovery time fy. The Tatio l/s is
Tam .peok tevin
called or S-factor
This meagure of the
voltage transients that occur diving
the time diode recovers. Its usual
‘value is unity and this indicates low
‘acillatory reverse recovery process.
In case S-factor is small, diode has
large oscillatory over voltages. {A
i js S.factor equal to ones
a) variation of forward current ip
(b) forward voltage drop v7 and (c) power loss in diode
ih Sc Toe ot arseoy dite In Fg. 24) is shown the wavtrm
Ssarage drop The product of aT es the power Luan add
eae i ghown/in Fig. 24 (c). The average Yale of gives the total power low ina
diode. Fig. 2.4 (c) reveals that major_ ywer loss in a diode during the period ts-
otced frm Fig, 24 (e) that pak inverse current yy ean be expresso
oni an
InumteSt
4 14 [Art 24)
where 4 isthe rate of change of reverse current, The reverse recovery characteristics of iy
it
24 (a) can be taken to be triangular. Under this assumption, storage charge Qy, from Fig
24 (a), is given by
1
Qn= Flaw br
SS tuo 2a
Ift, =¢,, then from Eq, (2.1),
te 29
From Eqs. (22) and (2.3), we get
a
te
t, 20, 42.4)
* el idi/dt),
From Eq, (2.1), witht, tym We get
di_[2Qn]? ai
Trae e [as dt
on (S 2s)
Ie en rm E24) nd 2 hate wert ty nd po nvers caren
Jy ae dept on mag charg and rate of change caret The rags hae
depends upon the far id crn Ip The she that evra scovery tine ad pork
iene cet doen on fea ode, eet
7 powerlines a pak oer curt In, tre charge Qn
Sar PV in rer to bal oar the at euplnt fone cee ee
parameters are usually specified in the catalogue supplied by the diode manufacturers,
Diodes ae clasiied
power diodes are as under
© General purpose diodes
i) Fast recovery diodes
ib) Schottky diodes
These are now described briefly
2.4.1. General-purpose Diodes
‘These diodes have relatively high reverse recovery time, of the order of about 2
ime, ofthe order of about 25 us. Theit
ratings vary {rom 1 Ato several thousand amperes and the rong ae
from 50 V to about 6 KV: Anpliations of power diodes of this tire manta eae Taine
ra cat, orn wlan oe ee bey car
to their reverse recovery characteristics. The three types of : -Fast-recovery Diodes
‘The diodes with low
peo Feverse recovery time, of about 5 us or less, are classified as
pice erica, These are usd in chopors commutation cuts, avitched mode power
supplies, induction heating ete Thy
supplies, weir current ratings vary from about 1 A to several thousand
pores and voltage ratings from $0V tosh 9800
For voltage rat
These dns ne
For voltage ratings
order to shorten that eee 400 V,difusion technique is used forthe fabrication of diodes. In
Feverse-recovery time, platinum or gold doping is carried out. But this
oping may increase the forward voltage drop in adiode, ne
24.3. Schottky Diod
‘below about 400 V, the epitaxial process is used for diode fabrication
Fecovery time, as low as 50 na,
: icon. Therefor, @
mit inium-ilcon junction, The silicon isn ype
hen Schottky diode is forward biased, free electrons inn material move towards the Al-n
junction and then travel through the metal (aluminium) to constitute the flow of forward
urrent. Since metal doesnot have any hole, this forward current is due ta the movement of
characteristics are not under control. Power transistors, however, possess contralied
characteristics, These are turned on when a current signal is given to base, or control, terminal.
‘The transistor remains in the on-state 0 long as control signal is present. When this control
signal is removed, a power transistor is turned off
Power transistors are of four types as under
(@) Bipolar junction transistors (BJTs)
(ii) Metal-oxide-semiconductor field-effect transistors (MOSFETS)
(iii) Insulated gate bipolar transistors (IGBTs) and
(iv) Static induction transistors (SITs).
‘These four types are now described one ater the other.
2.6.1. Bipolar Junction Transistors
‘A bipolar transistor is a three-layer, two junction npn or pnp semiconductor device. With
‘one p-region sandwiched by two n-regions, Fig. 2.5 (a), npn transistor is obtained. With two
regions sandwiching one 7-region, Fig 2.5 (b), pnp transistor is obtained. The term' bipolar a iii ie
Power Electron
denotes that the current low in the device ix duo to the movement of both hole
‘ABYT has thre terminals named collector (C), miter (5) and base (B). An emir i inden,
by an arrowhead indicating the direction of emitter current, No arrow is associated with byg
or collector, Power transistors of npn type are easy to manufacture and are cheaper ay
Therefore, use of power npn transistors in very wide in high-voltage and high-currow
applications. Hereafter, npn transistors would only be considered
ttt s
;
I i
stor (a) npn type and (D) PnP YP
. Out of the three possible circuit configurations fr
‘transistor, common emitter arrangement is more eummon in switching applications. So, a coramon
tmitter npn circit for obtaining its characteristic is considered us shown in Fig. 26 (a),
Input characteristics, A graph between base current Jp and base-emit age Vee
gives input characteristis, As the base-emitter junction ofa transistor is like a diode, fy versus
Vge graph resembles a diode curve. When cellectoremitter voltage Veg, is more than Vo
sme Ve, decreases as shown in Fig, 26 (b)
base current, for the
Neer fle ag teu> >t
> er ants
@ o
Fig, 28 (npn tantric charac, pt characteristics and (6) ouptchaacteritics. |
‘Output characteristics. A graph botwoon collector current J, and sollectoremitter
oltage Vog eves output characteristics of «transistor. For zero base curret, ce. for fp = 0
inreased, a soa leakage (collector) current exiata as shown in Fg. 26 (0). As the base
inrensed fro fy = 010 I, yy, collector current alo rissa shown in Fy. 26)
Vee
current i Dio
me Teles (art 25) 17
Fig. 2.7 (@) shows
initalpar ort We ety raat creo = 0402 p40 The
cll artcurse 2, harry iw Vor men trate enn
nich Theft part of curv, inated by nresing Veg nd almost
/e region. In this region, transistor acts like an amplifier. Almost
the breakdown region which must be avoided at all costs
constant Jo, is the act
‘Vertically rising curve is
coteetor
tell
ti
salt
c Xe ceiver
o
@ t
Fig. 2:7. (2) Output characteristics and load line for np transistor and
") electron flow ian npn transistor.
Fora seta Re, Fig. 2 (a, the clear ue fis given by
Voo~ Ves
seek!
tins the equation ofa ine. Itt sawn asline AB in Fig. 27() Alea ine he lose
Se enn ato omaioron Venera f= VeeRe Tis
fs poh ere ed on the eral te, When te tron rin he
calecioncrrent ho Frama andthe elect
Se Bon neha x Fr three late oning
Pa ef ind Bis te lod line
i pnd Mt ofthe ens, propria enc itn,
cen aia Fig 270 acho ler cet oun han
rec h cler oy Aaptl wed natch vas ew
ce teed ood crete
on 26)
A yaa cant ad arse oe
cs ae se et wt cet
‘the current gain By C
oh
A sn base current is applied, a transistor dom
en errr eee ere tt
2.5.1.2. BUT Switching Performance. Whe!
not turn on instantly because of the presence of internal
capacitances. Fig. 2.9 shows the various switching
waveforms of an npn power transistor with resistive load
between collector and emitter, Fig. 2.8.
When input voltage vg to base cireuit is made ~ V, at
fy junction EB or EBJ is reverse biased, vge =~ Vz, the
O and veg = Voc, Fig. 2.9. At time
ty, input voltage up is made + V; and ig rises to Ip, a8
shown in Fig. 2.9. After ¢,, base-emitter voltage ge begins
to rise gradually from ~ V, and collector current i, begins _ Fig. 2.8. npn transistor with
to rise from zero (actually a small leakage current [ceo petro
exists as shown in Fig. 2.7 (a)) and collector- emitter voltage ucg starts falling from its initial
value Voc. After some time delay t,, called delay timte, the collector current rises to 0.1
Tes) ee falls from Ver to 0.9 Vec and Upg reaches Vggs = 0.7 V. This delay time is required to
charge the base-emitter capacitance to Vags = 0.7 V. Thus, delay time t, is defined as the time
during which the collector current rises from zero to 0.1 [cs and collector-emitter voltage falls
from Voc t0 0.9 Veo.
After delay time f,, collector current rises from 0.1 Ics to 0.9 Ics and Ugg falls from 09
Vee to 0.1 Veg in time ¢,. This time ¢, is known as rise time which depends upon transistor
junction capacitances. Rise time f, is defined as the time during which collector current rises
from 0.1 Ics to 0.9 Voc and collector-emitter voltage falls from 0.9 Voe to 0.1 Voc. This shows
that total turn-on time ¢,, =t, + ¢,. Value of ¢,, is of the order of 30 to 300 nano seconds. The
transistor remains in the on, or saturated, state so long as input voltage stays at V;, Fig. 29
(a).
In case transistor is to be turned off, then input voltage vy and input base current ig a
reversed. At time f, input voltage vp to base circuit is reversed from V, to ~ V;. At the same
time, base current changes from Jy, to ~ Ip, as shown in Fig. 2.9 (6). Negative base current [s:
removes excess carriers from the base. The time f, required to remove these excess carriers 8 Power Semiconductor Diodes and Transistors
(art 2s) 2
Fig. 29, Switching waveforms for npn power transistor of Fig. 28
called storage time and only after, base current Ip; bogins to decrease towards zero.
‘Transistor comes out of saturation only after f,. Storage time ¢, is usually defined as the time
during which collector current falls from Ics to 0.9 Ics and collectoremitter voltage vcg rises
from Vos to 0.1 Vec, Fig. 2.9 (d) and (e). Negative input voltage enhances the process of
removal of excess carriers from base and hence reduces the storage time and therefore, the
turn-off time,
‘After t,, collector current begins to fall and collector-emitter voltage starts building up.
‘Time ty called fall time, is defined as the time during which collector current drops from
0.9 fog to 0.1 eg and collector-emitter voltage rises from 0.1 Voc 00.9 Veo, Fig. 29d) and).
Sum of storage time and fall time gives the transistor turn-off time fy ie. ty =t, fp The
various waveforms during transistor switching are shown in Fig. 2.9. In this figure, =
conduction period of transistor, ¢, = off period, T'= 1/fis the periodic time and is the switching
1 (S08 ow SOAR) of a power trans A metal-oxide-semiconductor field-effect transistor (MOSFET) is a recent device developed
by combining the areas of field-effect concept and MOS technology: power Semiconductor Diodes sn 1s -asistors
Apower MOSFET has thtee te
‘ge corresponding three terminals
power MOSFET is as shown in Fig. 214 ta),
ABIT is @ current controlled device whereas
rminals called di
collector
' power MOSFET is
{are
iain (D), source (8) and gate (G) in place of
emitter and base for BUT. The cireuit symbol of
lere arrow indicates the direction of electron flow.
volfagecontrolled device
its operation depends upon the ow of waar
sole pees pen 1p epg carer ony, MOSFET is unipolar device
current) req
red
MOSFET is extremely high, of the order of 10"
MOSFET gate to be driven directly from microel
breakdown voltage whereas MOSFET is free fr
finding inereasing applications in low-power high
ial, OF base current in BJT is tm
a This is because
ch larger than the contra signal (or ete
the et Cat gate Ccut impedance in
hm, This large impedance permits the
etenie drei: BI sulfers fom second
mths problem. Power MOSPET. ate now
frequeney converters.
fe
err ae Load
jochas ii
tI"
a 0 gdran souced ys, pate ova
KS
‘eon
8 . ore
oe
pesibarae
sésouce =
® w
Fig. 2.14. Nchannel enhancement power MOSFET
(a) circuit symbol and (its base structure,
Power MO:
-e of two types ; n-channel enhancement MOSFET and p-channel
enhancement MOSFET. Out of these two types, nchannel enhancement MOSFET is more
common because of higher mobility of electrons. As such, only this type of MOSFET is sadied
in what fellows
‘Asimplified structure of n-channel planar MOSFET of low power rating is shown in Fig.
2.16 (6). On p-subatrate (or body), two heavily doped n’ regions are diffused as shown. An
{nnulating layer of silicon dioxide (SiO,) is grown on the surface. Now this insulating layer is
‘etched in order to embed metallic source and drain terminals. Note that n” regions make
‘ontact with source and drain terminals a shown. A layer of metal is also deposited on SiO,
layer so as to form the gate of MOSFET in between source and drain terminal, Fig. 214 (5)
‘Whea gate cireuit ia open, junction between n’ region below drain and p-substrate ia
rover onset By Lip Vatoge Vo, Therefore, 0 cuiTen ows from drain wo source and lead
‘When gate is made positive with respect to source, an electric field is established as shown in
Pig. 2 eee Pallyrinduced negative charges in the psubstrate below SiO, layer are
fred thus easing tu 7 pero ete o Become an ined ayer These ote
‘called ,, form n-channel between two n” regions and current can flow from
Sar sen by Gav asrow I Vg t ade more petive, induced n-channel becotes
rare deep and therefore more current flow from D to S, This shows that drain curently is
‘enhanced by the gradual increase of gate voltage, hence the name enhancement MOSFET. _ —~\y
2 [Art 26) Pome Baca,
of n-channel planar MOSFET of Fig 2.16 () stat
and source gives large on-state resistance, Thisleadsohgeecht
dissipation in n-channel. This shows that planar MOSFET construction of Fig. 2144p"
feasible ony for low power MOSFET :
‘The constructional details of high power MOSFET aeilstrated in Fi2.15. tn this eg
is shown a planar difsed metal-odecomiconduces (DMOS) stroctre fr nchana S65
is quite common or power MOSFET. On °eutrao, igh entity lyer i eptaant
frown. The thicknes af m-layer determines the voltage Backing capability othe Sens
the other side of naubrtrate, a metal layer i depoited to form the drain terminal Now
regions are diffe inthe epitaxy grown n layer Further, n° regions are difued in
Teytns as shown: Aa buf, SiO, lager sade, whichis then etched wo att mea
Source and gata terminals A power MOSFET actually consists of pale comer
thousands baie MOSFET cleo the same singe chino sion
sicon
ig. 215. Basic structure of nchannel DMOS power MOSFET,
‘When gate circuit voltage is zero, and Vp is present ,n”— p” junctions are reverse biased
and no current flows from drain to source. When gate terminalis made positive with respect
to source, an electric feld is established and electrons form n-channél in the p” regions as
shown. So a current from drain to source is established as indicated by arrows. With gate
voltage increased, current Ip also increases as expected, Length of n-channel can be controlled
and therefore on-resistance can be made low if short length is used forthe channel
‘An examination ofthe basic structure of n-channel DMOS power MOSFET (PMOSFET)
reveals that a parasitic npn bipolar junction transistor exists between the source and drain
as shown in Fig. 2.16. The p body acts asthe base, n° layer as the emitter (or source) and n
layer as the collector (or drain) ofthis BJT. Since source is connected to both base and emitter
of parasitic BIT, the source short circuits both base and emitter Asa result, potential difference
between base and emitter of the parasitic BJT is zero and therefore, BIT is alway in the
cutoff state
A mintare ealcon atoms and petavalet stam
A eat race. Ths aerial! epi PIG-2.18. PMOSFET showing parasitic BJT and
rant die
dicated tn
movement of el "Puosre 2
ed daring he art pent
2currtie of 10 sare arable Seg ee
eee PMO erate in a eguoncy rage bl Oe a kw are at
241. PMOSFET Cha
racternin
gram or sche of power MOSFET ace now deed bi: Th tse dea
diagram for n- channel PMOSFET is shown in 2 aieeiie aes :
inated Te eae
ig, 2.17 where voltage and currents ae ae
nal Sis taken as common terminal, os ual beer neces
and output of a MOSFET. ha =
Nex
Pe
6) ®
Pig. 217, Nhannel ower MOSFET (duit diagram and (8) ts typed raster character
(a) Transfer Characters, Tis charters how he anaton
fanction of gate- source voltage Vgs. Fig. 2.17 (b) shows typical transfer characteristics for n-channel
POSPET Thre vatage Vs nn inportant purmeter d MOSPE Van eden
Positive voltage between gate afid source to induce n-channel, Thus, for threshold voltage below
Vasr, device is in the off-state. Magnitude of Vir is of the order of 2 to 3 V.
“pone chen OP mn rm P28
mt van ore yn ca i
scsi gr spn Fin oy Yar
acstincr ths Stine «pant al stom sca naa Vtoie Pe eave
drain current Ip a8 8 os
constant. A load line intersects the output characteristics at A and B. Here A ingens Ma,
‘condition and B fully-off state. PMOSFET operates asa sich either at Aor at B jun gg Se,
When power MOSFET is driven with large gateaource voltage, MOSFET i nn"
Vos on is small. Here, the MOSFET acting as a closed switch, is said to be driven, into ,
region (called saturation region in BJT). When device turns on, MOSFET we
n= Vas characteristics from cut-off, to active region and then to the ohmic
ora
Wes PMOSPE tn tac pny om cee Me
[art 2.61
Me
I\“tran-soace treandown whoge
os
Sate es Nest food
Fig. 2.18. (a) Output charnctoristics of Fig. 2.18; (6) Switching waveforms for
PMOSFET. PMOSFET.
(c) Switching characteristics. The switching characteristics of a power MOSFET are
influenced to a large extent by the internal capa:
impedance ofthe gate drive ciruit. At turn-on, there isan intial delay t,, during which inpat
capacitance charges to gate threshold voltage Vacp Here tg, is called turn-on delay time
‘There is further delay ¢, called rise time, during which gate voltage rises to Vagp a voltage
‘sufficient to drive the MOSFET intoon state, During, drain current rises from zero to fillon
current Ip, Thus, the total turn-on-time is f.,= fy, +. The turn-on time can be reduced by
‘using low-impedance gate-drive source
‘As MOSFET is a majority carrier device, turn-off process is initiated soon after removal
. of gate voltage at time. The turn-off delay time, fy, is the time during which input capacitance
discharges from overdrive gate voltage V; to Vasp. The fall time, ty isthe time during which
input capacitance discharges from Vasp to threshold voltage. During f, drain current falls from
Ip to zero, So when Vos $ Vosr, PMOSFET turn-off is complete. Switching waveforms fer 8
power MOSFET are shown in Fig. 2.18 (b),
2.6.2. PMOBFET Applications
‘The on-resistance of MOSFET increase with voltage rating ; this makes the device Very
eof the device and the ii
Lon ih carat spplatins. Sic thon reotanc ha pei ik
is relatively easy. The positive temperature ecient
reduce the second breakdown effec in PMOSPEty, " Pantve tem
i. 138 Diac
Diac is a device which has di electrode (i.e. two electrodes or two terminals) and as its
name suggests: it works on AC
The cross sectional view of a Diac is shown in figure 1.26(a). The four layers are
PNPN and PNPN’. The two terminal of diac are terminal T; and T>. The symbol of diac
is shown in figure 1.26(b). Diac is bidirectional device. It can be switched on either the
Positive cycle or negative cycle of AC voltage. It is also known as gatcless triac. t 7
¥
Poe
N iON L
?
2 P
TZ
« o
Figure 1.26 Diac (a) Basic structure (b) Symbol
"1.8.1 7 Vel Characteristics Hein x
‘The operation of the diac can be explained by imagining it as two diodes connected in
series. When applied voltage in either polarity is small (less than breakover voltage) a
very small amount of current, called the leakage current, flows through the diac, Leakage
‘current caused due to the drift of electrons and holes in the depletion region. is not
sufficient to cause conduction in the device. The device remains in non-conducting mode,
However, when T is positive with respect t0 Tz, the layers P-N-P-N starts conducting
‘only when applied voltage of T, exceeds breakover voltage Vpo1. Once the conduction
starts, the current through the diac becomes very large and has to be limited by the
‘extemal resistance in the circuit.
1
Figure 1.27 V1 characteristics : ‘When T3 is positive with respect to Ty, the layers P-N-P-N" conduct. This happens when
the applied voltage of T exceeds breakover voltage Vigo. In both the cases the current
‘during blocking regions are small leakage currents. The behavior in both the directions are
's similar because doping level is same inal the layers in two directions, The break over
Yoltage for commonly used dc is about 30V.
‘When T) is positive and voltage is less than Voy only a small Ieakage current flows,
{though the device. When voltage exceeds Vio it starts conducting and current becomes
large. As the current inereases, the voltage drop across diac decreases. Thus it exhibit
‘egative resistance characteristics. The characteristics of diac in reverse direction, when
T's positive ies inthe third quadrant and is exactly similar to that in the first quadrant
‘The breakover voltage Voy and Visoz are exactly equal in magnitude. In both the cases,
the device exhibits negative resistance behavior during conduction region. Diac is mainly
used for triggering triacs.
iy
AS the name suggests, TRIAC is a device which has three electrodes and works on AC.
‘The three terminals of trac are MT! (Main Terminal 1), MT (Main Terminal 2) and
‘sate Its a bidirectional device, means it can conduct in both the directions. The symbol
‘and characteristics of triac are shown in figure 1.28, trac are light dimmers, speed controls for electric fans and other
Some application’ of A poderm computerized contol circuits of many household small
lowing
conduct in following cases:
“when both MT3 and Gate are Positive
a ease, junction PIN and PaNz are forward biased whereas junction NiP2 i
tn this Fased, The gate current flows through P3N2. As the gate current is increased,
iy breaks down. It means when gate current has injected sufficient charge
sats aver, tae starts conducting through PyM\P3Nz layer.
MT,CHe)
Figure 1.29 When MT; and Gare Positive
2. When MT is Positive and Gate is Negative
In this case, gate current flows through P2N; junction. Junction N;P2 is forward biased,
hence the triac starts conduction through PiN\P2N3 layer intially. Since the gate is
negative with respect to the main terminal 1 (MT,) but MT is negative with respect to
MT, therefore, MT; attracts the holes from P2 layer through 2 layer and trac starts
conducting through PiNP2N% layer. 3. When MT; is Negative and Gate is Positive
4m this case, gate current flows through junction P2N;. Electrons are injected fry
‘Nz layer to Player. As a result junction jP), which is reverse biased, breaks down ax
triac starts conducting through P3N\PiN, layer.
MTY-ve)
Figure 1.31 When MT} is Negative and G is Positive
4. When both MT; and Gate are Negative
In this case. Ns works as a remote gate. Gate current flows form layer P;
°» to layer Ny
jenction NP is reverse biased and it breaks down. Hence, the triac stats conducting
through P2N\P\Na layer.
Figure 1.32 When both MT; and G are Negative GTO stands for gate turn-off thyristor. It is four layer PNPN device. It can be triggered
(tum-on) into conduction like a conventional thyristor by a pulse of positive gate current.
GTO can be easily tumed off by a negative gate pulse of appropriate magnitude. The
GTO is a three terminal device with anode, cathode and gate terminals. The basic
structure and symbol of GTO is shown in figure 1.22. The two way arrow convention
‘on the gate lead distinguishes the GTO from an ordinary thyristor. The use of GTO in
poner eketronic circuit eliminates the need of forced commutation circuit because
tumoff is achieved by applying a negative circuit
(a) (b)
Figure 1.22 GTO (a) Structure (b) two different symbol
‘The gate turn-off thyristor has highly doped N spots in the P layer at the anode. The plus
sign indicating high doping level. The gate cathode structure is interdigitated i.e. each
electrode is composed of a large mumber of narrow channels closely located
Functions of GTO, except for turn-off are the same as those of conventional thyristors
therefore, we mainly describe the turn-off operation here. When a GTO is in the on-state,
the central base regions are filed with holes supplied from the anode and electrons supplied
from the cathode. If reverse bias is applied to make the gate nevative in respect to the
‘cathode, part of holes in the p-base layer are extracted through the gate, suppressing the
injection of electrons from the cathode. In response to this suppression, more hole current is
extracted through the gate, further suppressing the electron injection, In the course of this
process, the cathode emitter junction is put into a reverse-bias state entirely, GTO is turned.
off, GTO is analogy of two transistors (PNP and NPN) a8 shown in igure 1.23. Supp tne
GTO thyristor is divided into npn transistor Trl on the cathode side and pnp transistor Ty)
( the anode side, and that they are connected as shown in figure 1.23. In this figure hg
current amplification factor of transistor Trl is called al, and that of transistor Tr2, a? iy
Feverse current log flows through the gate, base current fy at transistor Trl is reduced en
‘kg is increased. The relationship between GTO thyristor anode current (I,) and cathos.
‘current (I) is expressed by the following equations
lem hk + beg
A.GTO thyristor can cary out the tum-off if an adequate magpitude of reverse bias current
4 supplied to the gate. Actually, however shoct resistance exists in the Trl base region
‘making it difficult to tum off the on state current flowing at the emiter junction that is far
from the gate.
‘Anode
Oy
Cathode
Gate e—
poise ae ee
BEERS
When a positive signal is applied, GTO works like an ordinary thyristor in conducting
mode. In GTO, the current gain of PNP transistor is low so that tum off is possible if
significant current is drawn from the gate. When a negative gate signal is applied. the
excess charge carriers are drawn from the base region of NPN transistor and collector
‘current of PNP is diverted to the gate.
‘Thus the base drive of NPN transistor is removed and this in turn removes the base
drive of PNP transistor and tum OFF is achieved Power Semiconouctor Devices
1
Figure 1.24 Static Vl characteristics
The Vil characteristics of a GTO in fonvard bias is same to that of a conventional thyristor
The latching current for large power GTO is much higher (approx. 2ma) as compared
to the latching current for conventional thyristor (approx. 100-500ma) of same rating
1.2.2 Switching Characteristics
‘When a positive signal is applied. GTO starts conducting. Before initiation of conduction
anode current is zero and anode to cathode voltage Vak is the peak reverse voltage.
‘When conduction starts anode current rises from la to full value and the anode to cathode
voltage Vak becomes very small (equal to ON state voltage drop). When a negative gate
signal is applied, the anode current becomes zero and the Vak rises to peak reverse
voltage. The total tum OFF time can be divided in three distinct times: storage time (ts),
fall ime (f) and tal time (tt). The switching characteristic of a GTO is shown in figure 1.25
'T Postive gate
signal
Negative gate
signal
o
v Sint
Figure 1.25 Switching characteristics ‘As soon as negative gate signal is applied, tum OFF process starts immediately. ‘The time
clapsing between applications of negative gate current till this current reach
Deak value known as storage time (Is). Dur
cs ts negative
1) this period, the excess charges are
removed by the negative gate current and GTO gets ready to tum OFF During fall time
4, the anode current decreases rapidly and anode to cathode voltage rises, This time
tin most GTO is about Ips. Atte end oft, the current falls slowly to zero value during
tail time t, At the end of the tail time, the anode
Vax becomes equal to peak reverse voltage
‘There are many advantages and disadvantages of GTO over thyristor, Some advantages,
of GTO are as follows
1
urrent I, becomes zero. and
‘Commutation cireuit is not needed
2. Fast switching speed
3. More didt at tum ON
4. Higher efficieney because losses in commutation ci
3. Circuits using GTO are compact
's eliminated
6 Lesser acoustical and clectromagnetic noise due to climination of choke of
‘comnmutation
Following are some disadvantages of GTO
1. Higher latching and holding current
2. Higher on state voltage drop and power losses
3. Higher gate current
4. Higher gate circuit losses
Lower reverse voltage blocking capacity
Vanable frequency inverter circuits, electric traction and steel mills are some of the
important applications of GTO. It is also suitable for use as a main control device in
inverters and choppers
5 IGBT stands for Insulated Gate Bipolar Transistor. It is having the advantages of both
power MOSFET and BIT. In IGBT, layer P* is used as a substrate. One side is deposited
‘with metal layer to form collector and other side of P* substrate, N~ layer is epitaxially
grown. The other layers are same as power MOSFET. The three terminals of IGBT are
Emitter E, gate G and collector C. Collector
©
Gate,
@
Emiter Emitter
© ©
Nechannel 1GBT P-channel 1GBT
co} ©
Figure 1.18 IGBT (a) Basic structure (b) & (¢) Symbol
‘The IGBT is a four layer N-P-N-P device with an MOS-gated channel connecting the
two Neype regions. It is a new high conductance MOS gate-controlled power switch
In operation of IGBT. the epitaxial region is conductivity modulated (by excess holes and
clectrons) and thereby climinating a major component of the on-resistance, IGBT
‘maintains gate control (docs not latch) over a wide range of anode current and voltage.
‘The basic structure of the IGBT is shown in figure 1.18(a)
In many respects it is similar to a power MOSFET. Main difference is the presence
cof P* as injecting layer. Next is N* layer (buffer layer) There is a P-N junction (J)
between these layers and two more junctions (J and J3) as shown in figure 1.18(a).
IGBTs are widely used in medium power applications such as DC and AC motor drives,
UPS systems, power supplics for solenoids, relays and contactors. Though IGBTs are
meee than BITs, they have lower gate drive requirements, lower switching
esate ese
In the normal mode of operation of an IGBT. a positive voltage is applied to the collector
(C) relative to emitter (E). When the gate (G) is at zero potential with respect to E, no.
collector current Ic flows for collector voltage Vcr below the breakdown level Vi, When
Vc < Vp and the gate voltage exceeds the threshold value Vor, electrons pass into the
‘No-tegion (base of the P-N-P transistor). Vous Vous Vous Vor
Figure 1.19 VA characteristics of IGBT
These electrons lower the potential of the N--region, forward biasing the P'- N
(substrate-cpi-layer) junction, thereby causing holes to be injected from the P* substrate
into the N~epi-layer region. The excess electrons and holes modulate the conductivity of
the high resistivity N’-region, which dramatically reduces the on-resistance of the device.
With zero gate bias, the forward characteristic of IGBT shows very low current (= 1 nA),
where it breaks-up sharply to much larger current levels with only a slight increase in
voltage. The VI characteristic of IGBT is shown in figure 1.19. It shows the relation
between collector current Ic and collector to emitter voltage VCE for diferent values of
gate to emitter voltage VGE.
‘The junction J1 blocks reverse voltage. An IGBT without N+ buffer layer has higher
reverse blocking capability. Therefore an IGBT required for blocking high reverse voltage
does not have N+ buffer layer. The reverse blocking voltage is shown as the VRM on
the V- characteristics. The junction J2 blocks the forward voltage when the IGBT is off 1.6.2 “Transfer Characteristic 4
‘The transfer characteristics of IGBT is shown figure 1.20. Gate-emitter voltage Vor. is
the controllig parameter of IGBT. If Vog is less than the threshold voltage Veirriny then
IGBT is in OFF state, If Vog is greater than the threshold voltage then the IGBT
(ON state, This curve is almost linear except when collector current is very low.
9 Voum oe
Figure 1.20 Transfer characteristic
The switching characteristic of an IGBT during tum on and turn-off time all shown in
figure.1.21. The sum of delay time and rise time gives the total turn-on time (1€. Tog =
tu+), Here delay time is the time during which collector to emitter voltage (Ve) falls
10%, it means from Ver to 90% of Ver, where Vee initial eolletor
