Chapter #5: MOSFET’s

from Microelectronic Circuits Text

by Sedra and Smith
Oxford Publishing

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 Introduction

 IN THIS CHAPTER WE WILL LEARN

 The physical structure of the MOS transistor and how
it works.
 How the voltage between two terminals of the
transistor control the current that flows through the
third terminal, and the equations that describe these
current-voltage characteristics.
 How the transistor can be used to make an amplifier,
and how it can be used as a switch in digital circuits.
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 Introduction

 IN THIS CHAPTER WE WILL LEARN

 How to obtain linear amplification from the
fundamentally nonlinear MOS transistor.
 The three basic ways for connecting a MOSFET to
construct amplifiers with different properties.
 Practical circuits for MOS-transistor amplifiers that
can be constructed using discrete components.

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 Introduction

 We have studied two-terminal semi-conductor devices

(e.g. diode).
 However, now we turn our attention to three-terminal
devices.
 They are more useful because they present multitude of
applications, e.g:
 signal amplification, digital logic, memory, etc…

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 Introduction

 Q: What, in simplest terms, is the

desired operation of a three-terminal
device?
 A: Employ voltage between two
terminals to control current flowing
in to the third.

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 note: MOSFET is more widely used in
Introduction implementation of modern electronic
devices

 Q: What are two major types of  MOSFET technology

three-terminal semiconductor  It allows placement of
devices? approximately 2 billion
 metal-oxide-semiconductor transistors on a single IC
field-effect transistor (MOSFET)  backbone of very large scale
 bipolar junction transistor (BJT) integration (VLSI)
 Q: Why are MOSFET’s more widely  It is considered preferable to
used? BJT technology for many
 size (smaller) applications.
 ease of manufacture
 lesser power utilization

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 5.1. Device Structure
and Operation

 Figure 5.1. shows general structure of the n-channel

enhancement-type MOSFET

Figure 5.1: Physical structure of the enhancement-type NMOS transistor: (a) perspective view, (b) cross-
section. Note that typically L = 0.03um to 1um, W = 0.1um to 100um, and the thickness of the oxide
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layer
Microelectronic Circuits by Adel S. Sedra and Kenneth (tox)(0195323033)
C. Smith is in the range of 1 to 10nm.
 two n-type doped
5.1. Device Structure regions (drain, source)
and Operation
layer of SiO2 separates
source and drain

metal, placed on top of

SiO2, forms gate
electrode

one p-type doped region

Figure 5.1: Physical structure of the enhancement-type NMOS transistor: (a) perspective view, (b) cross-
section. Note that typically L = 0.03um to 1um, W = 0.1um to 100um, and the thickness of the oxide
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layer
Microelectronic Circuits by Adel S. Sedra and Kenneth (tox)(0195323033)
C. Smith is in the range of 1 to 10nm.
 5.1. Device Structure
and Operation

 The name MOSFET is derived  The device is composed of

from its physical structure. two pn-junctions, however
 However, many MOSFET’s do they maintain reverse biasing
not actually use any “metal”, at all times.
polysilicon is used instead.  Drain will always be at
 “This” has no effect on positive voltage with
modeling / operation as respect to source.
described here.  We will not consider
 Another name for MOSFET is conduction of current in this
insulated gate FET, or IGFET. manner.

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 5.1.2. Operation with
Zero Gate Voltage

 With zero voltage applied to

gate, two back-to-back diodes
exist in series between drain
and source.
 “They” prevent current
conduction from drain to
source when a voltage vDS is
applied.
 yielding very high
resistance (1012ohms)

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Figure 5.1: Physical structure…
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 5.1.3. Creating a
Channel for
Current Flow

 Q: What happens if (1) source and

drain are grounded and (2) positive
voltage is applied to gate? Refer to
figure to right.
 step #1: vGS is applied to the
gate terminal, causing a positive
build up of positive charge along
metal electrode.
 step #2: This “build up” causes
free holes to be repelled from
region of p-type substrate under
gate. Figure 5.2: The enhancement-type NMOS transistor
with a positive voltage applied to the gate. An n
channel is induced at the top of the substrate
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 Q: What happens if (1) source
and drain are grounded and (2)
positive voltage is applied to
gate? Refer to figure to right.

 step #3: This “migration”

results in the uncovering of
negative bound charges,
originally neutralized by the
free holes
 step #4: The positive gate
voltage also attracts electrons
from the n+ source and drain
regions into the channel.
Figure 5.2: The enhancement-type NMOS transistor
with a positive voltage applied to the gate. An n
channel is induced at the top of the substrate
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 Q: What happens if (1) source this induced channel is
and drain are grounded and (2) also known as an
positive voltage is applied to inversion layer
gate? Refer to figure to right.

 step #5: Once a sufficient

number of “these” electrons
accumulate, an n-region is
created…
 …connecting the source
and drain regions
 step #6: This provides path for
current flow between D and S.

Figure 5.2: The enhancement-type NMOS transistor

with a positive voltage applied to the gate. An n
channel is induced at the top of the substrate
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 5.1.3. Creating a Vtn is used for n-type
MOSFET, Vtp is used for
Channel for p-channel
Current Flow

 threshold voltage (Vt) – is the  effective / overdrive voltage – is

minimum value of vGS required to the difference between vGS applied
form a conducting channel between and Vt.
drain and source (eq5.1) vOV  vGS  Vt
 typically between 0.3 and 0.6Vdc
 field-effect – when positive vGS is  oxide capacitance (Cox) – is the
applied, an electric field develops capacitance of the parallel plate
between the gate electrode and capacitor per unit gate area (F/m2)
induced n-channel – the
conductivity of this channel is  ox is permittivity of SiO2 3.45E11 F / m 
affected by the strength of field tox is thickness of SiO2 layer
 
 SiO2 layer acts as dielectric  ox
(eq5.3) C ox  in F / m2
t ox
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 5.1.3. Creating a
Channel for
Current Flow

 Q: What is main requirement for n-  Q: How can one express the

channel to form? magnitude of electron charge
 A: The voltage across the contained in the channel?
“oxide” layer must exceed Vt.  A: See below…
 For example, when vDS = 0… W and L represent width and length of channel respectively

 the voltage at every point along (eq5.2) Q  C ox WL vOV in C
channel is zero
 the voltage across the oxide  Q: What is effect of vOV on n-
layer is uniform and equal to vGS channel?
 A: As vOV grows, so does the
depth of the n-channel as well
as its conductivity.
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 5.1.4. Applying a
Small vDS

 Q: For small values of vDS, how does one calculate iDS

(aka. iD)? A: Equation (5.7)…
 Q: What is the origin of this equation?
 A: Current is defined in terms of charge per unit
length of n-channel as well as electron drift velocity.
n represents mobility of electrons at surface of the
n-channel in m2 / Vs

 nvDS 
(eq5.7) iD   C oxWvOV    in A
  L 
charge per unit  
length of electron
n -channel drift velocity
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 5.1.4. Applying
a Small vDS

 Q: How does one calculate charge per unit length of n-

channel (Q/uL)?
 A: For small values of vDS, one can still assume that
voltage between gate and n-channel is constant
(along its length) – and equal to vGS.
 A: Therefore, effective voltage between gate and n-
channel remains equal to vOV.
 A: Therefore, (5.2) from two slides back applies.

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 5.1.4. Applying a
Small vDS

 Q: How does one calculate action: divide both sides by L


charge per unit length of n- (eq5.2) Q  C ox WL  vOV in C
channel (Q/uL)? Q
 A: Use (5.2) to calculate (eq5.4)  C oxWvOV in C / m
L
charge per unit L of channel.
 Q: How does one calculate vDS
electron drift velocity? (eq5.5) E  in V / m
L
 A: Note that vDS establishes
(eq5.6) e-drift velocity  
an electric field E across
length of n-channel, this may V m2 m
  n E in 
calculate e-drift velocity. m Vs s
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 5.1.4. Applying a
Small vDS

 Q: How does one calculate action: divide both sides by L


charge per unit length of n- (eq5.2) Q  C ox WL  vOV in C
channel (Q/uL)? Q
Note that these two (eq5.4)  C oxWvOV in C / m
 A: Use (5.2) to calculate L
values mayper
charge beunit
employed
L of channel.
 toQ:define current
How does in
one calculate vDS
amperes (aka.velocity?
electron drift C/s). (eq5.5) E  in V / m
L
 A: Note that vDS establishes
(eq5.6) e-drift velocity  
an electric field E across
length of n-channel, this may V m2 m
  n E in 
calculate e-drift velocity. m Vs s
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 5.1.4. Applying a
Small vDS

 Q: What is observed from equation (5.7)?

 A: For small values of vDS, the n-channel acts like a
variable resistance whose value is controlled by vOV.

 W 
(eq5.7) iD   nC ox  vOV  vDS in A
 L 
vDS 1
(eq5.8a) rDS   in 
iD W 
nC ox    vOV
   L 
process 
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transconductance aspect
parameter
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ratio
 5.1.4. Applying a Note that this vOV represents
the depth of the n-channel -
Small vDS what if it is not assumed to
be constant? How does this
equation change?
Q: that
Note What thisdo
is we
one note
VERY from equation (5.7)?
IMPORTANT
 A: For equation in of v , the n-channel acts like a
small values DS
Chapter 5.
variable resistance whose value is controlled by vOV.

 W 
(eq5.7) iD   nC ox  vOV  vDS in A
 L 
vDS 1
(eq5.8a) rDS   in 
iD W 
nC ox    vOV
   L 
process 
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transconductance aspect
parameter
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ratio
 5.1.4. Applying a
Small vDS

 Q: What three factors is rDS dependent on?

 A: process transconductance parameter for NMOS
(nCox) – which is determined by the manufacturing
process
 A: aspect ratio (W/L) – which is dependent on size
requirements / allocations
 A: overdrive voltage (vOV) – which is applied by the
user

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 kn is known as NMOS-FET
transconductance parameter
and is defined as nCoxW/L

1/rDS

low resistance, high vOV

high resistance, low vOV

Figure 5.4: The iD-vDS characteristics of the MOSFET in Figure 5.3.
when the voltage
by Adel S. Sedra applied between drain and source VDS is kept small.
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 5.1.5. Operation as
vDS is Increased

 Q: What happens to iD when vDS increases beyond “small values”?

 A: The relationship between them ceases to be linear.
 Q: How can this non-linearity be explained?
 step #1: Assume that vGS is held constant at value greater than
Vt.
 step #2: Also assume that vDS is applied and appears as voltage
drop across n-channel.
 step #3: Note that voltage decreases from vGS at the source
end of channel to vGD at drain end, where…
 vGD = vGS – vDS
 v GD
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= Vt +andvOV – vDS (0195323033)
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by Adel S. Sedra Kenneth C. Smith
 vOV vDS

The voltage differential

between both sides of n-
channel increases with vDS.

Figure 5.5: Operation

S. Sedra and Kenneth of
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C. Smith e-NMOS transistor as vDS is increased.
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 note the average value note that we can define total
charge stored in channel |Q|
as area of this trapezoid

Q   vOV  12 vDS  L

Figure 5.6(a): For a MOSFET with vGS = Vt + vOV application of vDS causes the voltage drop along the
channel to vary linearly, with an average value of vDS at the midpoint. Since vGD > Vt, the channel still
exists at the drain end. (b) The channel shape corresponding to the situation in (a). While the depth of
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the channel
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S. Sedra and the source is still proportional to vOV, the drain end is not.
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 Q: How can this non-
linearity be explained?

 vOV with vOV  12 vDS 

action: replace

 W
 
 step #4: Define iDS (eq5.7) iD   nC ox   vOV  12 vDS   vDS
 L 
in terms of vDS  
and vOV.
 W
   n C ox   v OV  2 vDS  vDS
1
if vDS  vOV
iD is dependent on the L

(eq5.7) iD   W
apparent vOV (not vDS  n ox L OV 2 vDS  vDS otherwise
  C   v  1

inherently) which does not  

 if vDS vOV then vDS vOV
change after vDS > vOV W

 n ox L OV 2 vDS  vDS if vDS  vOV
  C   v  1

(eq5.14) iD   in A
 1 W 2

 nCox  vOV otherwise
2 L
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triode vs. saturation region
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 saturation occurs
once vDS > vOV

 W
 triode:   C
n ox   v OV  2 vDS  vDS
1
if vDS  vOV
(eq5.14) iD   L in A
 saturation: 1  nC ox  W vO2 V otherwise

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2 L
 pinch-off does not mean
5.1.6. Operation for blockage of current
vDS >> vOV

 In section 5.1.5, we assume

that n-channel is tapered but
channel pinch-off does not
occur.
 Trapezoid doesn’t become
triangle for vGD > Vt
 Q: What happens if vDS > vOV?
Figure 5.8: Operation of MOSFET with vGS = Vt +
 A: MOSFET enters vOV as vDS is increased to vOV. At the drain end,
saturation region. Any vGD decreases to Vt and the channel depth at
the drain-end reduces to zero (pinch-off). At
further increase in vDS has this point, the MOSFET enters saturation more
no effect on iD. of operation. Further increasing vDS (beyond
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remains constant.
 Example 5.1: NMOS
MOSFET

 Example 5.1. Problem Statement: Consider an NMOS

process technology for which Lmin = 0.4m, tox = 8nm, n =
450cm2/Vs, Vt = 0.7V.
 Q(a): Find Cox and k’n.
 Q(b): For a MOSFET with W/L = 8m/0.8m, calculate the
values of vOV, vGS, and vDSmin needed to operate the transistor
in the saturation region with dc current ID = 100A.
 Q(c): For the device in (b), find the values of vOV and vGS
required to cause the device to operate as a 1000ohm
resistor for very small vDS.

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 5.1.7. The p-Channel
MOSFET

 Figure 5.9(a) shows cross-

sectional view of a p-channel
enhancement-type MOSFET.
 structure is similar but
“opposite” to n-channel
 complementary devices –
two devices such as the p-
channel and n-channel
MOSFET’s.
Figure 5.9(a): Physical structure of the PMOS transistor. Note that it is similar to the NMOS transistor
shown in Figure 5.1(b), except that all semiconductor regions are reversed in polarity. (b) A negative
voltage vGS of magnitude greater than |Vtp| induces a p-channel, and a negative vDS causes a current iD
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 5.1.7. The p-Channel
MOSFET

 Q: What are main differences

between n-channel and p-channel?
 A: Negative (not positive)
voltage applied to gate “closes”
the channel
 allowing path for current flow
 A: Threshold voltage (previously
represented as Vt) is
represented as Vtp
 |vGS| > |Vtp| to close channel

Figure 5.9(a): Physical structure of the PMOS transistor. Note that it is similar to the NMOS transistor
shown in Figure 5.1(b), except that all semiconductor regions are reversed in polarity. (b) A negative
voltage vGS of magnitude greater than |Vtp| induces a p-channel, and a negative vDS causes a current iD
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 5.1.7. The p-Channel
MOSFET

 Q: What are main differences

between n-channel and p-channel?
 A: Process transconductance
parameters are defined
differently
 k’p = pCox
 kp = pCox(W/L)
 A: The rest, essentially, is the
same, but with reverse
polarity...

Figure 5.9(a): Physical structure of the PMOS transistor. Note that it is similar to the NMOS transistor
shown in Figure 5.1(b), except that all semiconductor regions are reversed in polarity. (b) A negative
voltage vGS of magnitude greater than |Vtp| induces a p-channel, and a negative vDS causes a current iD
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Smith from source to drain.
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 5.1.7. The p-Channel
MOSFET

 PMOS technology originally dominated the MOS field

(over NMOS). However, as manufacturing difficulties
associated with NMOS were solved, “they” took over
 Q: Why is NMOS advantageous over PMOS?
 A: Because electron mobility n is 2 – 4 times greater
than hole mobility p.
 complementary MOS (CMOS) technology – is
technology which allows fabrication of both N and PMOS
transistors on a single chip.
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 5.1.8. Complementary
MOS or CMOS

 CMOS employs MOS transistors of both polarities.

 more difficult to fabricate
 more powerful and flexible
 now more prevalent than NMOS or PMOS

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Figure 5.10: Cross-section of a CMOS integrated circuit. Note that the PMOS transistor is formed in a separate n-
type region, known as an n well. Another arrangement is also possible in which an n-type body is used and the n
device is formed in a p well. Not shown are the connections made to the p-type body and to the n well; the
latter functions as the body terminal for the p-channel device.

p-type semiconductor n-well is added to allow

provides the MOS body generation of p-channel
(and allows generation of
SiO2 is used to isolate
n-channel)
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NMOS from PMOS
 Quick Recap!

 The equation used n represents mobility of electrons at surface of the

n-channel in m2 / Vs

to define iD depends  nvDS 
on relationship btw (eq5.7) iD   C oxWvOV    in A
  L 
charge per unit  
vDS and vOV. length of electron
n -channel drift velocity
 vDS << vOV in C / m in m2 / Vs

 vDS < vOV W

(eq5.14) iD   nC ox   vOV  12 vDS  vDS in A
L
 vDS => vOV 1 W 2
 vDS >> vOV (eq5.17) iD   nC ox  vOV in A
2 L
1 W 2
(eq5.23) i   n been

This Dhas not C ox  vOV 1  vyet!
covered DS  in A
2 L
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 5.2. Current-Voltage
Characteristics

 Figure 5.11. shows an n-

channel enhancement
MOSFET.
 There are four terminals:
 drain (D), gate (G), body
(B), and source (S).
 Although, it is assumed that
body and source are
connected.
Figure 5.11 (a): Circuit symbol for the n-channel enhancement-type MOSFET. (b) Modified circuit symbol with
an arrowhead on the source terminal to distinguish it from the drain and to indicate device polarity (i.e., n
channel). (c) Simplified circuit symbol to be used when the source is connected to the body or when the effect
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 5.2. Current-Voltage
Characteristics

 Although MOSFET is symmetrical

device, one often designates
terminals as source and drain.
 Q: How does one make this the potential at drain (vD) is
designation? always positive with respect to
 A: By polarity of voltage applied. source (vS)
 Arrowheads designate “normal”
direction of current flow
 Note that, in part (b), we
designate current as DS.
 No need to place arrow with B.

Figure 5.11 (a): Circuit symbol for the n-channel enhancement-type MOSFET. (b) Modified circuit symbol with
an arrowhead on the source terminal to distinguish it from the drain and to indicate device polarity (i.e., n
channel). (c) Simplified circuit symbol to be used when the source is connected to the body or when the effect
Oxford University Publishing
Microelectronic Circuits by Adel S. Sedra andof the body
Kenneth C. Smithon device operation is unimportant.
(0195323033)
 5.2.2. The iD-vDS
Characteristics

 Table 5.1. provides a

compilation of the
conditions and formulas
for operation of NMOS
transistor in three
regions.
 cutoff
 triode
 saturation
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Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)
 5.2.2. The iD-vDS
Characteristics

 At top of table, it shows circuit

consisting of NMOS transistor and
two dc supplies (vDS, vGS)
 This circuit is used to demonstrate
iD-vDS characteristic
 1st set vGS to desired constant
 2nd vary vDS
 Two curves are shown…
 vGS < Vtn
 vGS = Vtn + vOV

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Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)
 Oxford University Publishing
Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)
Figure 5.12: The relative levels of the terminal voltages of the enhancement NMOS
transistor forS. Sedra
operation
and Kenneth C.in
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Microelectronic Circuits by Adel the
Smith triode region and in the saturation region.
(0195323033)
equation (5.14) as vGS increases, so do the (1) saturation current
and (2) beginning of the saturation region

Figure 5.13: Oxford

The University
iD – vPublishing
DS characteristics for an enhancement-type NMOS transistor
Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)
 5.2.2. The iD-vGS
Characteristic

 Q: When MOSFET’s are employed to

design amplifier, in what range will
they be operated?
 A: saturation
 In saturation, the drain current (iD)
is…
 dependent on vGS
 independent of vDS
 In effect, it becomes a voltage-
controlled current source.
 This is key for amplification. Figure 5.13: The iD – vDS characteristics
for an enhancement-type NMOS
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transistor
Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)
  Q: What is one problem with (5.21)?
5.2.2. The iD-vGS  A: It is nonlinear w/ respect to
Characteristic vOV … however, this is not of
concern now.

 In effect, it becomes a voltage-

controlled current source.
 This is key for amplification.
 Refer to (5.21).
2
vOV

1 W 
(eq5.21) iD  kn    vGS  Vtn 
2

 2 L
 
this relationship provides
basis for application of
MOSFET as amplifier

Figure 5.14: The iD-vGS characteristic of an NMOS transistor operating in the saturation region. The iD-vOV
characteristic can be obtained by simply re-labeling the horizontal axis, that is, shifting the origin to the point
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vGS = Vtn.
Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)
 5.2.2. The iD-vGS
Characteristic

 The view of transistor as CVCS is

exemplified in figure 5.15.
 This circuit is known as the
large-signal equivalent circuit.
 Current source is ideal.
 Infinite output resistance
represents independent, in
saturation, of iD from vDS..

note that, in this circuit, iD is Figure 5.15: Large-signal equivalent-circuit model

of an n-channel MOSFET operating in the
completely independent of vDS saturation
(because no shunt resistor
exists)
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Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)
 Example 5.2: NMOS
Transistor

 Example 5.2. Problem Statement: Consider an NMOS transistor

fabricated in an 0.18-m process with L = 0.18m and W = 2m.
The process technology is specified to have Cox = 8.6fF/m2, n =
450cm2/Vs, and Vtn = 0.5V.
 Q(a): Find VGS and VDS that result in the MOSFET operating at the
edge of saturation with ID = 100A.
 Q(b): If VGS is kept constant, find VDS that results in ID = 50A.
 Q(c): To investigate the use of the MOSFET as a linear amplifier,
let it be operating in saturation with VDS = 0.3V. Find the change
in iD resulting from vGS changing from 0.7V by +0.01V and -0.01V.
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Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)
 5.2.4. Finite Output
Resistance in
Saturation

 In previous section, we assume (in saturation) iD is

independent of vDS.
 Therefore, a change vDS causes no change in iD.
 This implies that the incremental resistance RS is
infinite.
 It is based on the idealization that, once the n-channel
is pinched off, changes in vDS will have no effect on iD.
 The problem is that, in practice, this is not completely
true.
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Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)
 5.2.4. Finite Output
Resistance in
Saturation

 Q: What effect will increased vDS have on n-channel

once pinch-off has occurred?
 A: It will cause the pinch-off point to move slightly
away from the drain & create new depletion region.
 A: Voltage across the (now shorter) channel will
remain at (vOV).
 A: However, the additional voltage applied at vDS will
be seen across the “new” depletion region.

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Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)
 5.2.4. Finite Output this is the most important
Resistance in point here
Saturation

 Q: What effect will increased vDS have on n-channel

once pinch-off has occurred?
 A: This voltage accelerates electrons as they reach
the drain end, and sweep them across the “new”
depletion region.
 A: However, at the same time, the length of the n-
channel will decrease.
 Known as channel length modulation.

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Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)
 5.2.4. Finite Output
Resistance in
Saturation

 Q: How do we account for “this

Figure 5.16: Increasing vDS beyond vDSsat causes the
effect” in iD? channel pinch-off point to move slightly away from
 A: Refer to (5.23). the drain, thus reducing the effective channel
length by L
valid when vDS vOV
  
1 W 2
(eq5.17) iD   nC ox  vOV in A
2 L
1 W 2
(eq5.23) iD   nC ox  vOV 1  vDS  in A
2
 L 

valid when vDS vOV

 A: Addition of finite output Figure 5.18: Large-Signal Equivalent Model of the

resistance (ro). n-channel MOSFET in saturation, incorporating the
output resistance ro. The output resistance
models the linear dependence of iD on vDS and is
Oxford University Publishing given by (5.23)
Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)
 5.2.4. Finite Output
Resistance in
Saturation  iD 
(eq5.24) ro   
1

 vDS  vGS constant


 Q: How is ro defined?  (5.23)  
 step #1: Note that ro is the iD  1 W 2 
(eq5.23)    n ox 
 C v OV  1   v DS  
1/slope of iD-vDS vDS vDS  2 L 
characteristic.  
 step #2: Define relationship  (5.23)  
iD  1 W 2 
between iD and vDS using (eq5.23)     C
n ox  v OV  1   v 
DS 
vDS vDS  2 L 
(5.23).  
 step #3: Take derivative of iD 1 W 2
this function. (eq5.23)   nC ox  vOV 
vDS 2 L
 step #4: Use above to define 
ro.
1
 Note that ro may be defined in 1 W 2 
(eq5.25) ro    nC ox  vOV 
terms of iD, where iD does not  2 L  vGS constant
take in to account channel (eq5.24) ro 
1 VA

length modulation…
Oxford University Publishing  iD iD
Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)
 5.2.4. Finite Output
Resistance in
Saturation

 Q: What is ?
 A: A device parameter with the
units of V -1, the value of which
depends on manufacturer’s
design and manufacturing
process.
 much larger for newer tech’s
 Figure 5.17 demonstrates the effect
of channel length modulation on Figure 5.17: Effect of vDS on iD in the
vDS-iD curves saturation region. The MOSFET
parameter VA depends on the process
 In short, we can draw a straight
technology and, for a given process, is
line between VA and saturation.
proportional to the channel length L.
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 5.2.5. Characteristics of
the p-channel MOSFET

 Characteristics of the p-
channel MOSFET are
similar to the n-channel,
however with many signs
reversed.
 Please review section
5.2.5 from the text, with
focus on table 5.2.

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Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)
 5.3. MOSFET Circuits at
DC

 We move on to discuss how

MOSFET’s behave in dc
circuits.
 We will neglect the effects of
channel length modulation
(assuming  = 0).
 We will work in terms of
overdrive voltage (vOV), which
reduces need to distinguish
between PMOS and NMOS.

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Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)
 Example 5.3: NMOS
Transistor

 Problem Statement: Design

the circuit of Figure 5.21, that
is, determine the values of RD
and RS – so that the transistor
operates at ID = 0.4mA and VD
= +0.5V. The NMOS transistor
has Vt = 0.7V, nCox =
100A/V2, L = 1m, and W =
32m. Neglect the channel-
length modulation effect (i. e.
assume that  = 0). Figure 5.21: Circuit for Example
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Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)
5.3.
 Example 5.4:

 Refer to textbook…

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Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)
 Example 5.5: MOSFET

 Problem Statement:
Design the circuit in Figure
5.23 to establish a drain
voltage of 0.1V. What is
the effective resistance
between drain and source
at this operating point?
Let Vtn = 1V and k’n(W/L) =
1mA/V2.
Figure 5.23: Circuit for Example
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5.5.
Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)
 Example 5.6: MOSFET

 Problem Statement: Analyze the circuit shown in Figure 5.24(a) to

determine the voltages at all nodes and the current through all
branches. Let Vtn = 1V and k’n(W/L) = 1mA/V2. Neglect the
channel-length modulation effect (i.e. assume  = 0).
Figure 5.24: (a) Circuit for

circuit with some of the

analysis details shown.
Example 5.6. (b) The

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Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)
 Example 5.7: PMOS
Transistor

 Problem Statement: Design the circuit

of Figure 5.25 so that transistor
operates in saturation with ID = 0.5mA
and VD = +3V. Let the enhancement-
type PMOS transistor have Vtp = -1V
and k’p(W/L) = 1mA/V2. Assume  = 0.
 Q: What is the largest value that RD
can have while maintaining
saturation-region operation?

Figure 5.25: Circuit for

Oxford University Publishing
Example 5.7.
Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)
 Exercise 5.8: CMOS
Transistor

 Problem Statement: The

NMOS and PMOS transistors in
the circuit of Figure 5.26(a) are
matched, with k’n(Wn/Ln) =
k’p(Wp/Lp) = 1mA/V2 and Vtn = -
Vtp = 1V. Assuming  = 0 for
both devices.
 Q: Find the drain currents iDN
and iDP, as well as voltage vO
for vI = 0V, +2.5V, and -2.5V.
Figure 5.26: Circuits for Example
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Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)
5.8.
 5.4.1. Obtaining a example of transconductance
amplifier
Voltage Amplifier

 In section 1.5 of text, we learned that

voltage controlled current source (VCCS)
can serve as transconductance amplifier.
 the following slides (with blue tint) are
a review
 Q: How can we translate current output to
voltage?
 A: Measure voltage drop across load
resistor. function
of input
vout supply vG
   Figure 5.27: (a) simple MOSFET
(eq5.30) Oxford  vDD
vDSUniversity  iD RD
Publishing
Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033) amplifier with input vGS and output vDS
  voltage transfer characteristics
5.4.2. Voltage Transfer (VTC) – plot of out voltage vs. input
Characteristic  three regions exist in VTC
 vGS < Vt  cut off FET
 vOV = vGS – Vt < 0
 ID = 0
 vDS ??? vOV
 vout = vDD
 Vt < vGS < vDS + Vt  saturation
 vOV = vGS – Vt > 0
 ID = ½ kn(vGS – Vt)2
 vDS >> vOV
 vout = VDD – IDRD
 vDS + Vt < vGS < VDD  triode
 vOV = vGS – Vt > 0
Figure 5.27: (b) the voltage transfer  ID = kn(vGS – Vt – vDS)vDS
characteristic (VTC) of the amplifier  vDS > vOV
from previous slideC. Smith (0195323033)
Oxford University Publishing
Microelectronic Circuits by Adel S. Sedra and Kenneth  vout = VDD – IDRD
cutoff FET cutoff AMP
5.4.2. Voltage Transfer
Characteristic  Q: What observations may be
drawn?
 A: Cutoff FET represents
transistor blocking, cutoff
AMP represents vout = 0
 A: As vGS increases…
 vDS (effectively)
decreases
 iD increases
 vout decreases
nonlinearly
 gain (G) decreases
Figure 5.27: (b) the voltage transfer  A: Once vDS > vDD, all power
characteristic (VTC) of the amplifier
from previous slideC. Smith (0195323033)
Oxford University Publishing is dissipated by resistor RD
Microelectronic Circuits by Adel S. Sedra and Kenneth
 5.4.2. Voltage Transfer
Characteristic
Q: How do we define vDS in terms of
vGS for saturation?

this is equation is simply ohm's law / KVL

 
1 2
(eq5.32) vDS  VDD   kn  vGS  Vt   RD
2
 
iD

2kn RDVDD  1  1
(eq5.33) VGS B  Vt 
kn RD

Q: How do we define point B –

boundary between saturation and
Figure 5.27: (b) the voltage transfer triode regions?
characteristic (VTC) of the amplifier
from previous slideC. Smith (0195323033)
Oxford University Publishing
Microelectronic Circuits by Adel S. Sedra and Kenneth
 This equation differs from (5.32) because
5.4.3. Biasing the MOSFET
to Obtain Linear it considers dc component only.
Amplification this equation is simply ohm's law
 
1 2
(eq5.34) VDS  VDD   kn VGS  Vt   RD
  2  
 Q: How can we linearize VTC? Vsource ID RD

 A: Appropriate biasing
technique
 A: Dc voltage vGS is
selected to obtain
operation at point Q on
segment AB
 Q: How do we choose vGS?
 A: Will discuss shortly…
Figure 5.28: biasing the MOSFET
Oxford University Publishing amplifier at point Q located on
Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)
segment AB of VTC
 5.4.3. Biasing the MOSFET
to Obtain Linear
Amplification this equation is simply ohm's law

1 2
(eq5.34) VDS  VDD   kn VGS  Vt   RD
  2  
 bias point / dc operating pt. Vsource ID RD

(Q) – point of linearization for

MOSFET
 Also known as quiescent
point.
 Q: How will Q help us?
 A: Because VTC is linear
near Q, we may perform
linear amplification of
signal << Q
Figure 5.28: biasing the MOSFET
Oxford University Publishing amplifier at point Q located on
Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)
segment AB of VTC
 5.4.3: Biasing the MOSFET
to Obtain Linear
Amplification

 bias point / dc operating pt. (Q) =

linear amplification
point of linearization for MOSFET around Q in
 also known as quiescent point saturation region
 Q: how will Q help us?
 because VTC is linear near Q, we
may perform linear
amplification of signal << Q

Figure 5.28: biasing the MOSFET amplifier at

Oxford University Publishing point Q located on segment AB of VTC
Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)