Lecture-5 RAM Architecture
Lecture-5 RAM Architecture
Question: Draw the internal organization of a 64x4 RAM and discuss data
read write operation in it.
Answer:
Write Operation: To write any data in a location of memory, at first the input
buffer is enabled (E) by CS=1 and R/W=0. Then, the address of the specified
location is determined by decoding the address lines (A0 to A5). Finally, a
group of 4 bits data is sent through input data lines (I0 to I3) and written in the
specified memory location via input buffer.
Read Operation: To read any data in a location of memory, at first the output
buffer is enabled (E) by CS=1 and R/W=1. Then, the address of the specified
location is determined by decoding the address lines (A0 to A5). Finally, a
group of 4 bits data is sent from the specified memory location to the output
data lines (O0 to O3) via output buffer.
Answer:
SRAM DRAM
1. Faster RAM. 1. Slower RAM.
2. Each SRAM cell contains 2. Each DRAM cell contains 1
6 transistors. transistor and 1 capacitor.
3. Data density is low. 3. Data density is high.
4. No refreshing is needed. 4. Refreshing is needed.
5. More Expensive. 5. Less expensive.
DRAM Cell
BIOS: The full meaning of BIOS is Basic Input Output System. A BIOS is stored inside MROM.
The instructions of a BIOS are executed by the processor and a POST (Power On Self Test)
procedure is taken place for checking whether the input-output devices are in active status or not.
Types of ROM
MROM: This ROM maintains the basic characteristics of ROM. It is non-programmable (non-
writeable) ROM.
PROM: It is a one-time writeable (Programmable) but many-times readable ROM.
EPROM: It is a many-times writeable (Programmable) and many-times readable ROM. The
programming and erasing is done using UV light.
EEPROM: It is a many-times writeable (Programmable) and many-times readable ROM. The
programming is done using electricity.