324 IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 32, NO.

4, APRIL 2022

A 0.4-V High-Gain Low-Noise Amplifier Using a

Variable-Frequency Image-Rejection Technology
Jian-Yu Hsieh and Hsueh-Chien Kuo

Abstract— A 0.4-V high-gain low-noise amplifier (LNA) using

a variable-frequency image-rejection technology in Taiwan Semi-
conductor Manufacturing Company (TSMC) 0.18-µm CMOS
process has been proposed. By using forward body biasing and
folded topology, the supply voltage and power consumption can
be reduced. For achieving low power consumption and small
chip area, a feedback capacitor is used to shrink the size of the
inductors of the input impedance matching. Moreover, a gain-
enhancement-and-image-rejection (GEIR) circuit including an
inductor and a variable capacitor is proposed for achieving GEIR
simultaneously. The image-rejection frequency can be altered for
avoiding strong image signals by the variable capacitor. The pro-
posed LNA shows the measured results including a 15-dB power
gain, a 2.6-dB noise figure, and a −13-dBm input third-order
intercept point at 2.4 GHz, respectively. And the measured
variable image rejection ratio ranges from 14 to 39 dBc around
3–3.6 GHz for avoiding strong image signals. The measured Pdc
is 0.8 mW.
Fig. 1. Schematic of the proposed LNA.
Index Terms— CMOS, gain enhancement, image rejection, low-
noise amplifier (LNA), low power consumption.
The quadrature downconversion using several mixers and
I. I NTRODUCTION phase shifters increases Pdc . The amplitude and phase mis-
matches lower the accuracy of the image-rejection elimination.
L OW-POWER circuit design is an important topic because
radio frequency (RF) circuits generally cost major power
consumption (Pdc ). For reducing Pdc of a low-noise amplifier
The proposed GEIR circuit can achieve a variable-frequency
image rejection for avoiding strong image signals. The pro-
(LNA), forward body biasing [1] has been developed. A supply posed LNA is suitable for low-power applications.
voltage (VDD) is limited by threshold voltage (VT ) of a
II. C IRCUIT A RCHITECTURE AND D ESIGN
MOSFET transistor. VT can be reduced by the forward body
C ONSIDERATION
biasing, which is utilized in this letter.
Generally, gain performance of LNAs might degrade under The proposed LNA designed in Taiwan Semiconductor
low Pdc . Hence, several gain-boosted techniques including Manufacturing Company (TSMC) 0.18-μm CMOS technology
inverting amplifier feedforward [2] and transformer cou- has shown in Fig. 1. The input impedance matching network
pling [3] are developed. The inverting amplifier consumes in the first stage is formed by a resistor RG , capacitors (C G
extra power. The transformers require huge chip area. and C F ), inductors (L G and L S ), and an nMOS transistor M1 .
Hence, the gain-enhancement-and-image-rejection (GEIR) cir- The input impedance Z IN can be expressed as follows [6]:
cuit, which can enhance power gain (G LNA ) under smaller chip gmn L S 1
area and low Pdc , has been proposed in this letter. Z IN = s(L G + L S ) + +  
Cgsn + C F s Cgsn + C F
Generally, high-intermediate-frequency (IF) and low-IF  
gmn L S 1
receivers suffer from image problems. For suppressing = + j ω LG + LS − (1)
image signals, an image-rejection filter [4] and a quadrature Cgsn + C F Cgsn + C F
downconversion [5] are proposed. The image-rejection filter where gm1 and Cgs1 are transconductance and gate-to-source
results in gain reduction and noise figure (NF) increasing. capacitance of M1 , respectively. C G is large and neglected
for deriving the equations. Cgs1 , gm1 , and L G can be reduced
Manuscript received June 27, 2021; accepted July 13, 2021. Date of
publication July 19, 2021; date of current version April 8, 2022. This while using a larger C F . The chip area and Pdc can be reduced.
work was supported by the Ministry of Science and Technology of However, G LNA will degrade, while C F increases. Hence, there
Taiwan under Contract MOST 108-2221-E-197-028. (Corresponding author: exists a tradeoff between G LNA and chip area. The output
Jian-Yu Hsieh.)
The authors are with the Department of Electronic Engineering, impedance matching network in the second stage is composed
National Ilan University, Yilan 260, Taiwan (e-mail: [email protected]; of an inductor L O , a capacitor C O , and a pMOS transistor M2 .
[email protected]). An inductor L D is utilized for achieving a low-VDD folded
Color versions of one or more figures in this letter are available at
https://doi.org/10.1109/LMWC.2021.3098249. topology. L D can resonate with the parasitic capacitances at
Digital Object Identifier 10.1109/LMWC.2021.3098249 node X and provides a high impedance for an RF signal
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HSIEH AND KUO: 0.4-V HIGH-GAIN LNA USING VARIABLE-FREQUENCY IMAGE-REJECTION TECHNOLOGY 325

Fig. 2. High-frequency equivalent circuit of the second stage in the proposed

LNA.
Fig. 3. Chip micrograph of the proposed LNA.
but a low impedance for an IF signal leakage from the
following mixers. Hence, the RF signal stays but the IF signal
leakages can be eliminated. The simulated IF leakage from
the following mixers ranges from −130 to −106 dB, while
the downconverted signal operates from 300 to 600 MHz.
The GEIR circuit includes resistors (R1 , R2 , and R3 ),
an inductor L B , capacitors (C B1 , C B2 , and C B3 ), and nMOS
transistors (M3 , M4 , and M5 ) for realizing the gain enhance-
ment and variable-frequency image rejection. L B can enlarge
the gain of the second stage. C B1 , C B2 , C B3 , M3 , M4 , and
Fig. 4. Measured input return loss of the proposed LNA while V A , V B , and
M5 form a variable capacitor, which are controlled by V A , VC are biased at different voltages.
VB , and VC , for achieving image rejection at eight variable
frequencies. Fig. 2 shows the high-frequency equivalent circuit
of the second stage. The variable capacitor in the GEIR circuit
is expressed by C B . The voltage gain G LNAS of the second
stage can be expressed as follows:
  2
ω
gm2 R L s 2 ωgain
IR
+ ωgain
2

G LNAS = (2)
s 2 + ωgain
2

where ωgain and ωIR are the peak (G LNA ) and deep (image
Fig. 5. Measured isolation of the proposed LNA while V A , V B , and VC are
rejection) frequencies. ωgain can be expressed as follows: biased at different voltages.

1
ωgain = . (3)
L B (Cgsp + C B )
And ωIR can be expressed as follows:

1
ωIR = . (4)
L B CB
R L represents the output impedances of the second stage.
gm2 is the transconductance of M2 . Cgs2 is the gate-to-source
parasitic capacitance of M2 . ωIR can be altered, while C B is Fig. 6. Measured output return loss of the proposed LNA while V A , V B ,
varied under a fixed L B and ωgain . and VC are biased at different voltages.
The forward body biasing is applied to reduce VT of M1 ,
M2 , M3 , M4 , and M5 , which can realize low VDD and Pdc . 0.8 mm × 0.6 mm without bypass capacitors and pads. The
VT of an nMOS transistor can be expressed as follows [7]: process–voltage–temperature (PVT) variation will affect V A ,
VB , and VC , which are 0.4 and 0 V, slightly. The measured
VT = VT 0 + γ 2ϕ f + VSB − 2ϕ f (5) input return loss ranges from −9 to −11.9 dB at 2.4 GHz,
as shown in Fig. 4. The measured isolation ranges from
where VT 0 is the threshold voltage with zero-body-source −26 to −30 dB at 2.4 GHz, as shown in Fig. 5. The measured
voltage, i.e., VSB = 0 V. γ is the body effect coefficient, and output return loss ranges from −19 to −23 dB at 2.4 GHz,
ϕ f is the bulk Fermi potential. In this letter, the body voltages as shown in Fig. 6. The measured G LNA , which varies slightly,
of nMOS and pMOS transistors are connected to VDD and a ranges from 14.3 to 15 dB at 2.4 GHz, while ωIR varies, as
ground, respectively. shown in Fig. 7. The measured image rejection ratio (IRR)
ranges from 14 to 39 dBc, while ωIR varies from 3 to 3.6 GHz.
III. M EASUREMENT R ESULTS OF THE LNA The measured K factor is larger than 1.8 around 2.4 GHz. The
The proposed low-power LNA chip is fabricated by using measured and simulated results of NF are shown in Fig. 8,
TSMC 0.18-μm CMOS technology under VDD of 0.4 V. The while V A , VB , and VC are biased at 0.4 V. The measured NF
chip micrograph is shown in Fig. 3. The chip area occupies is 2.6 dB at 2.4 GHz. The measured input third-order intercept

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326 IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 32, NO. 4, APRIL 2022

TABLE I
P ERFORMANCE C OMPARISON OF S TATE - OF - THE -A RT LNA

The proposed LNA can achieve great FOM under

low Pdc .

IV. C ONCLUSION
A 0.4-V low-power LNA in TSMC 0.18-μm CMOS process
has been proposed in this letter. For achieving low Pdc ,
high G LNA , variable-frequency image rejection and chip area
reduction, the folded topology, feedback capacitor forward
body biasing, and GEIR circuit have been proposed. The
Fig. 7. Measured G LNA of the proposed LNA while V A , V B , and VC are proposed LNA is suitable for low-power applications.
biased at different voltages.
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