Quickly access every chapter of Fundamentals of Logic Design 7th Edition Roth Solutions Manual via PDF download.
Quickly access every chapter of Fundamentals of Logic Design 7th Edition Roth Solutions Manual via PDF download.
https://testbankfan.com/product/logic-and-computer-design-
fundamentals-5th-edition-mano-solutions-manual/
https://testbankfan.com/product/programming-logic-and-design-
comprehensive-7th-edition-joyce-farrell-solutions-manual/
https://testbankfan.com/product/digital-systems-design-using-vhdl-3rd-
edition-roth-solutions-manual/
https://testbankfan.com/product/digital-systems-design-using-
verilog-1st-edition-roth-solutions-manual/
Fundamentals of Digital Logic and Microcontrollers 6th
Edition Rafiquzzaman Solutions Manual
https://testbankfan.com/product/fundamentals-of-digital-logic-and-
microcontrollers-6th-edition-rafiquzzaman-solutions-manual/
https://testbankfan.com/product/programming-logic-and-design-
comprehensive-7th-edition-joyce-farrell-test-bank/
https://testbankfan.com/product/fundamentals-of-machine-component-
design-5th-edition-juvinall-solutions-manual/
https://testbankfan.com/product/digital-logic-and-microprocessor-
design-with-interfacing-2nd-edition-hwang-solutions-manual/
https://testbankfan.com/product/starting-out-with-programming-logic-
and-design-3rd-edition-tony-gaddis-solutions-manual/
Unit 8 Design Solutions
III. SOLUTIONS TO DESIGN, SIMULATION,
AND LAB EXERCISES
Solutions to Unit 8 Design Problems
Problems 8.A through 8.S are combinational logic design problems using NAND and NOR gates.
Problems 8.A through 8.R are of approximately equal difficulty so that different students in the
class can be assigned different problems. We ask our students to use the following procedure:
(1) Derive a truth table for the assigned problem.
(2) Use Karnaugh maps to derive logic equations in sum-of-products or product-of-sums form
depending on whether NAND gates or NOR gates are required.
(3) Enter the truth table into LogicAid, derive the logic equations, and check the answers
against the results of step (2).
(4) Draw a circuit of AND and OR gates, trying to minimize the number of gates required by
using common gates where appropriate. Factoring or multiplying out is required in some
cases.
(5) Convert to NAND or NOR gates as specified.
(6) Simulate your answer to (5) using SimUaid, and verify that the circuit works correctly.
Use switches as inputs and probes or a 7-segment indicator as outputs.
In Unit 10, we ask our students to implement the same design problem using VHDL, synthesize it
and download it to a CPLD or FPGA on a hardware board that has switches, LEDs, and 7-segment
indicators.
For each design problem, the solutions that follow show a SimUaid circuit that meets the problem
specifications, but the solution does not necessarily use the minimum number of gates. Each solution
shows the truth table and the equations derived using LogicAid, and in several cases the Karnaugh
maps are shown to help identify common terms.
263
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 8 Design Solutions
8.A X1 X2 X3
(cont.) A B A B A B
C D 00 01 11 10 C D 00 01 11 10 C D 00 01 11 10
00 1 X 1 00 1 1 X 1 00 1 1 X 1
01 1 X 1 01 1 X 1 01 1 1 X 1
11 1 1 X X 11 1 1 X X 11 1 1 X X
10 1 X X 10 1 X X 10 1 X X
X4 X5 X6
A B A B A B
C D 00 01 11 10 C D 00 01 11 10 C D 00 01 11 10
00 1 X 1 00 1 X 1 00 1 1 X 1
01 1 X 01 X 01 1 X 1
11 1 X X 11 X X 11 X X
10 1 1 X X 10 1 1 X X 10 1 X X
X7
A B
C D 00 01 11 10
00 1 X 1
01 1 X 1
11 1 X X
10 1 1 X X
X1
B'
D'
1 A
0
0 B
C'
A' D
1 B
0 B
0 X2
C'
B' D'
1
B' 2
X3
1 C 3
0 C D' 4
0
5
6
C' 7
C
1 D' X4
0
0 D
D' B'
C
X5
B
C'
X6
B
D'
X7
264
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 8 Design Solutions
8.B ABCD X1 X2 X3 X4 X5 X6 X7 X1 = B' + C'D + C D' + A
X2 = C+B
0000 X X X X X X X
X3 = D' + C + A (used in circuit)
0001 X X X X X X X X3 = D' + C + B'
0010 X X X X X X X X4 = C'D + B'D + B C D' + A C' (used in circuit)
0011 1 1 1 1 1 1 0 X4 = C'D + A'C D' + B'D + A C'
0100 0 1 1 0 0 0 0 X5 = C'D + B'D
0101 1 1 0 1 1 0 1 X6 = C D + A C'
0110 1 1 1 1 0 0 1 X7 = A D + B C + C'D + A C' (used in circuit)
0111 0 1 1 0 0 1 1 X7 = A D + B C + A C' + B D
1000 1 0 1 1 0 1 1
1001 1 0 1 1 1 1 1 This solution uses 15 gates and 38 gate inputs.
1010 1 1 1 0 0 0 0
1011 1 1 1 1 1 1 1 Students are allowed to use a maximum of 16 gates.
1100 1 1 1 1 0 1 1
B X1
C'
D
C
D'
1
0 A
0 B' X2
C'
A'
C' X3
1
0 B D
0
1
B' 2
C'
3
X4
4
B 5
1 C C
1 6
0 D' 7
C'
X5
B'
D
1 D
1
0
X6
C
D' D
X7
D
B
C
265
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 8 Design Solutions
8.C ABCDE W X Y Z W = A(C + D) (B + C) (C + E) = A(C + BDE) (used in circuit)
W = A(C + D) (B + C) (D' + E)
00000 0 0 0 0
W = A(C + D) (C + E) (B + D')
00001 0 0 0 0 W = A(C + D) (B + D') (D' + E)
00010 0 0 0 0 X = (C + D) (B' + C + E') (A + C) (B + C') =
00011 0 0 0 0 (B + C') (C + AD(B' + E')) (used in circuit)
00100 0 0 0 0 X = (C + D) (B' + C + E') (B + C') (A + D')
00101 0 0 0 0 X = (C + D) (B + C') (A + D') (B' + D' + E')
00110 X X X X X = (C + D) (B' + C + E') (B + D) (A + D')
00111 X X X X X = (C + D) (B + D) (A + D') (B' + D' + E')
01000 0 0 0 0 X = (C + D) (A + C) (B + C') (B' + D' + E')
01001 0 0 0 1 X = (C + D) (B' + C + E') (A + C) (B + D)
01010 0 0 1 0 X = (C + D) (A + C) (B + D) (B' + D' + E')
01011 0 0 1 1 Y = (A + B) (A + D) (B + E) (D + E) (A' + B' + D' + E') = (A + BD) (E + BD)
(A' + B' + D' + E') = (AE + BD)(A' + B' + D' + E')
01100 0 1 0 0
Z = BE
01101 0 1 0 1
01110 X X X X This solution uses 14 gates and 32 gate inputs.
01111 X X X X
10000 0 0 0 0 Student are allowed to use a maximum of 15 gates.
10001 0 0 1 0
10010 0 1 0 0
10011 0 1 1 0
B'
10100 1 0 0 0 D'
W
E'
10101 1 0 1 0 1
0 A 0
0 C
10110 X X X X
10111 X X X X A' B'
11000 0 0 0 0 E'
11001 0 0 1 1
1 B D' X
11010 0 1 1 0 0
0
C
0
11011 1 0 0 1
11100 1 1 0 0 B'
B
11101 1 1 1 1 C'
1 C
0
0
E'
C' Y
B' 0
D'
1 D
0
0
B'
D'
D' E'
Z
0
1 B'
0 E
0 E'
E'
266
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 8 Design Solutions
8.D ABCDE W X Y Z W = AC+ABDE
X = B C + A B'D + A D E'
00000 0 0 0 0
Y = A'B D + A B'E + A D'E + B D E'
00001 0 0 0 0 Z = BE
00010 0 0 0 0 This solution uses 14 gates and 38 gate inputs.
00011 0 0 0 0 Students are allowed to use a maximum of 14 gates.
00100 0 0 0 0
00101 0 0 0 0 W X
B C B C
00110 X X X X D E 00 01 11 10 D E 00 01 11 10
00111 X X X X 00
1 1
00
1
01000 0 0 0 0 1
01001 0 0 0 1 1 1 1
A 01 A 01
01010 0 0 1 0 1 1
1
01011 0 0 1 1 0
11
X X 1 0
11
1 X X
X X X X
01100 0 1 0 0
X X 1 X X 1
01101 0 1 0 1 10 10
X X X X
01110 X X X X
01111 X X X X W = AC+ABDE X = B C + A B'D + A D E'
10000 0 0 0 0 Y Z
B C B C
10001 0 0 1 0 D E 00 01 11 10 D E 00 01 11 10
10010 0 1 0 0 00
00
10011 0 1 1 0
10100 1 0 0 0 1 1 1 1 1 1
A 01 A 01
10101 1 0 1 0 1 1
1 1
0 X X 1
10110 X X X X 0
11
1 X X
11
X X 1
10111 X X X X X X 1
X X 1 X X
11000 0 0 0 0 10 10
X X 1 X X
11001 0 0 1 1
11010 0 1 1 0 Y = A'B D + A B'E + A D'E + B D E' Z = BE
11011 1 0 0 1 1
0
0 A W
0
11100 1 1 0 0 A'
C
11101 1 1 1 1
B
D
E
1 B
0
0
B
C X
B'
0
B'
1 D
0
0 C
D
C' E'
1 D
0
0
B'
E
D' Y
D' 0
E
1
0
0 E B
D
B
E' D
E'
Z
0
B
E
267
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 8 Design Solutions
8.E ABCD X1 X2 X3 X4 X5 X6 X7 X1 = A B + A'C + B'D +
0000 1 1 1 1 1 1 0 C'D' (used in circuit)
0001 1 1 1 1 1 1 0 X1 = A C' + B C + B'D + A'D'
0010 1 1 1 1 1 1 0 X1 = A D + B C + C'D' + A'B'
0011 1 1 1 1 1 1 0 X1 = A C' + B D' + C D + A'B'
0100 1 1 1 1 1 1 0 X1 = A B + C D + A'D' + B'C'
0101 0 1 1 0 0 0 0 X1 = A D + B D' + A'C + B'C'
0110 1 1 0 1 1 0 1 X2 = A' + C' + B'D' + B D
0111 1 1 1 1 0 0 1 X3 = A C + B D + C'D' +
1000 1 1 1 1 1 1 0 A'B' (used in circuit)
1001 1 1 0 1 1 0 1 X3 = A B + B'C + A'D + C'D'
1010 0 1 1 0 0 1 1 X3 = A B + C D + A'C' + B'D'
1011 1 0 1 1 1 1 1 X3 = A D' + B D + B'C + A'C'
1100 1 1 1 1 1 1 0 X3 = A D' + B C' + C D + A'B'
1101 1 1 1 1 0 0 1 X3 = A C + B C' + A'D + B'D'
1110 1 0 1 1 1 1 1 X4 = A B + A'C + B'D +
1111 1 1 1 1 0 1 1 C'D' (used in circuit)
X4 = X1
X5 = B'D + B D' + C'D' +
A'B' (used in circuit)
X5 = B'D + B D' + C'D' + A'D'
X5 = B'D + B D' + A'D' + B'C'
C
X5 = B'D + B D' + A'B' + B'C'
X6 = A'B' + C'D' + A C
B'
D
X1 X7 = B C + A D + A C
C'
1
0
0 A
D'
This solution uses 17 gates and 44 gate
inputs.
A' B
Students are allowed to use a maximum of
1
18 gates.
0
0 B
B' C X2
D'
B'
B
D
1
0 0 C
1
B' 2
X3
3
C' 4
C 5
6
7
1
0 D X4
0
D'
X5
B
D'
X6
D X7
B
C
268
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 8 Design Solutions
8.F ABCD X1 X2 X3 X4 X5 X6 X7 X1 = A + B'C + B'D' (used in circuit)
X1 = A + B'C + C'D'
0000 1 1 1 1 1 1 0
X1 = A + B'D' + C D
0001 0 1 1 0 0 0 0 X2 = A' + C' + D
0010 1 1 1 1 0 0 1 X3 = C' + D' + A
0011 1 1 0 1 1 0 1 X4 = A C' + B'D' + A B + A'C D (used in circuit)
0100 X X X X X X X X4 = A C' + A'B'C + A D' + C'D'
0101 X X X X X X X X4 = A C' + A'B'C + B'D' + A D'
0110 0 1 1 0 0 1 1 X4 = A C' + A'B'C + B'D' + A B
0111 X X X X X X X X4 = A C' + B'D' + A D' + A'C D
1000 1 1 1 1 0 1 1 X5 = A'C'D' + A'C D + A C'D + A B'C D'
1001 1 1 1 1 1 1 1 X6 = C'D' + B + A C' + A D'
1010 1 0 1 1 1 1 1 X7 = A'C + A C' + A D' (used in circuit)
1011 1 1 1 0 0 0 0 X7 = A'C + A C' + C D'
1100 X X X X X X X
This solution uses 18 gates and 51 gate inputs.
1101 X X X X X X X
1110 1 0 1 1 0 1 1 Students are allowed to use a maximum of 20 gates.
1111 X X X X X X X
B' X1
D'
1 A
0
0 B'
C
A' X2
C
D'
C X3
1 D
0
0 B
C
D
B' X4
B
1
2
C' 3
4
1 C 5
0
0 6
C' 7
C' D'
X5
C'
D
1 B'
0 D
0 C
D'
D'
B'
C'
X6
D'
C'
X7
D'
269
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 8 Design Solutions
8.G K N3 N2 N1 N0 M3 M2 M1 M0 M3 = N2 N1 N0 + N3 + K N2 N1 = N3 + N2 N1(K + N0)
M2 = N2 N1' + K'N2 N0' + N2'N1 N0 + K N2' N1
0 0 0 0 0 0 0 0 1
= N2 N1' + K' N2 N0' + N2' N1(K + N0)
0 0 0 0 1 0 0 1 0 M1 = K'N1 N0' + K N1' + N1'N0
0 0 0 1 0 0 0 1 1 = K' N1 N0' + N1'(K + N0)
0 0 0 1 1 0 1 0 0 M0 = K' N0' + K N0
0 0 1 0 0 0 1 0 1
0 0 1 0 1 0 1 1 0 This solution uses 13 gates and 31 gate inputs.
0 0 1 1 0 0 1 1 1
0 0 1 1 1 1 0 0 0 Students are allowed to use a maximum of 13 gates.
0 1 0 0 0 1 0 0 1
M3
0 1 0 0 1 1 0 1 0 0
0 1 0 1 0 1 0 1 1 1 K
N2 N3'
0 N0'
0 1 0 1 1 1 1 0 0 0 N1
0 1 1 0 0 1 1 0 1 K'
0 1 1 0 1 1 1 1 0 N2'
0 1 1 1 0 1 1 1 1 1
0 N3
N1 M2
0
0
0 1 1 1 1 X X X X N2
N1'
1 0 0 0 0 0 0 1 0 N3'
1 0 0 0 1 0 0 1 1
N2
1 0 0 1 0 0 1 0 0 1
0 N2
N0'
1 0 0 1 1 0 1 0 1 0
1 0 1 0 0 0 1 1 0 N2' M1
0
1 0 1 0 1 0 1 1 1 N1'
1 0 1 1 0 1 0 0 0
1 N1 N1
1 0 1 1 1 1 0 0 1 0
0
N0'
1 1 0 0 0 1 0 1 0 N1'
1 1 0 0 1 1 0 1 1
M0
1 1 0 1 0 1 1 0 0 N0' 1
1 1 0 1 1 1 1 0 1 1
0 N0
0
1 1 1 0 0 1 1 1 0 N0
1 1 1 0 1 1 1 1 1 N0'
1 1 1 1 0 X X X X
1 1 1 1 1 X X X X
270
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 8 Design Solutions
8.H
C'
(cont.) B'
D'
X1
1 C
0 A
0
A' B'
C'
X2
B
C
1
0 B
0
B X3
B'
C'
B' 1
C 2
1 C
0 3
0 X5 X4
4
D' 5
C' B 6
7
1
X5
0 D B
0 C'
D'
B' X6
D'
C'
X7
D'
8.I ABCD X1 X2 X3 X4 X5 X6 X7 1
0
0 A
B' C X1
D'
0000 X X X X X X X A'
B
0001 X X X X X X X D
0010 1 1 1 1 1 1 0 1 B
B'
C
0
0011 0 1 1 0 0 0 0 0
C' X2
B'
0100 1 1 0 1 1 0 1 D
0101 1 1 1 1 0 0 1 B
D'
0110 0 1 1 0 0 1 1 1
B
C' X3
C
0111 1 0 1 1 0 1 1
1 D'
0
1
1000 1 0 1 1 1 1 1 C'
X4
2
3
4
1001 1 1 1 0 0 0 0 5
6
1010 1 1 1 1 1 1 1 1
0 D
7
0
1011 1 1 1 1 0 1 1 D' X5
C'
D'
X1 = B'D' + C' + B D + A
X2 = B'C + C'D + B D' (used in circuit) B X6
C
X2 = B'C + A'D' + C'D
X2 = B'D + C D' + B C'
X2 = B'D + A'C' + C D' C
X7
X3 = D+C+A
X4 = B'D' + B D + A C + C'D' (used in circuit)
X4 = B'D' + B D + A C + B C'
X4 = B'D' + B D + A C + A'C'
X5 = B'D' + C'D'
X6 = B C + A C + B'D'
X7 = B + A C + C'D' (used in circuit) This solution uses 15 gates and 38 gate inputs.
X7 = B + A C + A D' Students are allowed to use a maximum of 17 gates.
271
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 8 Design Solutions
8.J ABCDE W X Y Z W = (A + B + C) (C + D) (B' + C + E) (used in circuit)
W = (A + B + C) (C + D) (A + C + E)
00000 0 0 0 0
X = (A + B + D) (B' + C + E') (A' + C + E) (B' + C + D) (used in circuit)
00001 0 0 1 0
X = (A + B + D) (B' + C + E') (A' + C + E) (C + D + E)
00010 0 1 0 0 X = (A + B + D) (B' + C + E') (A' + C + E) (A + C + D)
00011 0 1 1 0 Y = (A + B + E) (B' + C + D' + E') (A' + C + D) (A + D + E) (used in circuit)
00100 1 0 0 0 Y = (A + B + E) (B' + C + D' + E') (A' + C + D) (B' + D + E)
00101 1 0 1 0 Z = (A + B) (C + E) (A + D + E) (used in circuit)
00110 1 1 0 0 Z = (A + B) (C + E) (B' + D + E)
00111 1 1 1 0
01000 0 0 0 0 This solution uses 17 gates and 51 gate inputs.
01001 0 0 1 1
01010 0 1 1 0 Students are allowed to use a maximum of 19 gates.
01011 1 0 0 1
01100 1 1 0 0 B
01101 1 1 1 1 C W
1
01110 1 1 1 1 0
0 A 0
01111 1 1 1 1 B'
C
10000 0 0 0 0 A' E
10001 0 1 0 1
10010 1 0 1 0 C
10011 1 1 1 1 D
1 B
10100 1 1 1 1 0
0
10101 1 1 1 1
10110 1 1 1 1 B'
C
10111 1 1 1 1 E
X
1 B 0
0 C
0 D
B'
C' C
D
B'
C
1 D E'
0
0
D' B'
C
D'
E'
Y
1 C 0
0 E
0 D
E' B
E
D
E
Z
0
C
E
272
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 8 Design Solutions
8.K ABCDE W X Y Z W =AB
X = B C + A B'
00000 0 0 0 0
Y = B'C D + A'B C' + A B'D + A C
00001 0 0 0 0
Z = A'C'D E + B D E + A'B'C D' + A B'C'D' + A'B C'D + A'B C'E + A C D + A C E
00010 0 0 0 0 = DE(B + A'C') + B'D'(A'C + AC') + A'BC'(D + E) + AC(D + E)
00011 0 0 0 1 = DE(B + A'C') + B'D'(A + C)(A' + C') + A'BC' (D + E) + AC(D + E)
00100 0 0 0 1
00101 0 0 0 1 This solution uses 19 gates and 47 gate inputs.
00110 0 0 1 0
00111 0 0 1 0 Students are allowed to use a maximum of 22 gates.
01000 0 0 1 0
01001 0 0 1 1
01010 0 0 1 1 W
0
01011 0 0 1 1
B
01100 0 1 0 0
01101 0 1 0 0 1
0 A X
0
01110 0 1 0 0 B'
0
A'
01111 0 1 0 1 B
10000 0 1 0 1 1
0 B
C
0
10001 0 1 0 1
B'
10010 0 1 1 0 C
10011 0 1 1 0 1 B
Y
0
0 C
10100 0 1 1 0 0 C'
11000 1 0 0 0 D'
11001 1 0 0 0
Z
11010 1 0 0 0 D' C 0
11011 1 0 0 1 1
0
0 E E'
E'
C
B'
D'
C'
D
E
B'
273
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 8 Design Solutions
8.L A B A B A B
(cont.) C D 00 01 11 10 C D 00 01 11 10 C D 00 01 11 10
00 0 00 0 0 00 0
01 X 01 0 X 0 01 0 0 X
11 0 X 11 X 11 X
10 X 10 0 X 10 0 X
A B A B A B
C D 00 01 11 10 C D 00 01 11 10 C D 00 01 11 10
00 0 00 0 0 0 00 0
01 X 01 X 01 0 X
11 0 X 11 0 X 11 X
10 X 0 10 0 X 0 10 0 X 0
X4 = (A'+ C'+ D) (B'+ C'+ D') (A + B'+ C + D) X5 = (B' + D) (B' + C' + D') (A' + D) X6 = (A'+ C'+ D) (A + B'+ C) (A + B'+ D)
A B
C D 00 01 11 10
00 0
01 X
11 0 X B'
C
D
10 X 0 X1
B'
1 A C'
0
0
X7 = (A'+ C'+ D) (A + B'+ C + D) (A + B + C'+ D') D'
A'
B
C
X2
B
D
1 B
0
0
X3
B'
C
D' 1
2
X4 3
4
C' 5
D 6
1 7
0 C
0
C' D
B' X5
C'
B'
1 D D
0
0
D'
B'
D X6
B'
C
X7
B
C'
D'
274
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 8 Design Solutions
8.M WXYZ X1 X2 X3 X4 X5 X6 X7 X1 = W'(X + Z) (Y + Z)
X2 = (X' + Y + Z') (W' + Z') (W + Y' + Z ) (W + X + Y') (used in circuit)
0000 X X X X X X X
X2 = (X' + Y + Z') (W' + Z') (W + X + Y') (X' + Y' + Z)
0001 1 1 1 0 1 1 1 X2 = (X' + Y + Z') (W' + Z') (W + Y' + Z) (X + Y' + Z')
0010 0 0 1 1 1 1 1 X3 = (X + Y' + Z') (X' + Y + Z') (X' + Y' + Z) (W' + Z')
0011 1 0 0 1 1 1 0 X4 = (X + Y) (X' + Y' + Z)
0100 0 1 1 1 1 0 1 X5 = (X' + Y' + Z')
0101 1 0 0 1 1 1 1 X6 = (W' + Y') (W + Y + Z) (used in circuit)
0110 1 0 0 0 1 1 1 X6 = (W' + Y') (X' + Y + Z)
0111 1 1 1 1 0 1 1 X7 = (X + Y' + Z') (W' + Z') (W' + Y')
1000 0 1 1 0 1 1 1
1001 0 0 0 0 1 1 0 This solution uses 19 gates and 50 gate inputs.
1010 0 1 1 1 1 0 0
Students are allowed to use a maximum of 22 gates.
X
Z
Y
Z
X1
1
0 W
0
W' X
Y'
Y'
1
0 X Z X2
0
X'
X' Y
Z'
Z'
1
0 Y
0 X'
Y
Y' Z'
X' X3
Y'
Z
X
1
1 Z Y' 1
0
Z' 2
Z' X4 3
X 4
Y 5
6
7
X'
Y' X5
Z'
Y'
X6
Y
Z
X7
275
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 8 Design Solutions
8.N ABCDE X Y Z X = A'BC(D + E) (D' + E')
Y = ABE(C + D) (C' + D')
00000 0 0 0
Z = (A + B) (A + C' + D' + E) (A' + B' + C + D' + E') (B' + C' + D + E')
00001 0 0 0
= (A + B) (A + C' + D' + E) [B' + E'+ (A' + C + D') (C' + D)]
00010 0 0 0
00011 0 0 0 This solution uses 17 gates and 41 gate inputs.
00100 0 0 0
00101 0 0 0 Students are allowed to use a maximum of 19 gates.
00110 0 0 0
00111 0 0 0
1 A
01000 0 0 1 0
0
B'
01001 0 0 1 A' C' X
0
01010 0 0 1
D
01011 0 0 1 1
E
B
01100 0 0 1 0
0
10101 0 0 1
10110 0 0 1 1 E
10111 0 0 1 0
0 B Z
11000 0 0 1 E' 0
C'
11001 0 0 1 D'
E
11010 0 0 1 C'
B'
11011 0 1 0 D
E'
11100 0 0 1
C
11101 0 1 0 D'
11110 0 0 1
11111 0 0 1
276
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 8 Design Solutions
8.O AB AB AB AB
CD 00 01 11 10
(cont.) CD 00 01 11 10 CD 00 01 11 10 CD 00 01 11 10
00 0 X 00 X 00 X 00 0 X
01 0 X 01 0 X 01 X 01 0 X 0
11 X X 11 X X 11 X X 11 0 X X
10 0 X X
10 0 X X 10 0 X X 10 X X
X1 = (A + B + C + D)(B'+ C + D)(B'+ C' + D)
X2 = (B'+ C + D')(B'+ C'+ D) X3 = (B + C'+ D ) X4 = (B'+ C'+ D')(B'+ C + D)(B + C + D')
AB AB AB
CD 00 01 11 10 CD 00 01 11 10 CD 00 01 11 10
00 0 X 00 X 00 0 X
01 0 0 X 0 01 0 X 01 0 X
11 0 0 X X 11 0 0 X X 11 0 X X
10 X X 10 0 X X 10 X X
1 A
0
0
B
C
A' D'
B'
C' X1
1 B D
0
0
B'
B' C
D
1 C B'
0
0 X2
C
C' D'
1
0
D B X3
0 C'
D
D'
1
B 2
C
3
D' X4
4
B' 5
C' 6
D' 7
X5
D
B
D'
B X6
C'
C'
D'
X7
B
C
277
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 8 Design Solutions
8.P ABCD X1 X2 X3 X4 X5 X6 X7 X1 = (A + C + D') (A + B')
X2 = (A' + C' + D)
0000 1 1 1 1 1 1 0
X3 = (A + C' + D')
0001 0 1 1 0 0 0 0 X4 = (A + C + D') (A + B') (A' + C' + D')
0010 1 1 1 1 0 0 1 X5 = B'(A + C + D') (A + C' + D) (A' + C + D) (A' + C' + D')
0011 1 1 0 1 1 0 1 = B' (A + (C + D') (C' + D)) (A' + C + D) (A' + C' + D')
0100 X X X X X X X X6 = (A + D') (A + B + C') (C' + D')
0101 X X X X X X X X7 = (A + C) (A' + C' + D')
0110 0 1 1 0 0 1 1
0111 X X X X X X X This solution uses 21 gates and 50 gate inputs.
1000 1 1 1 1 0 1 1
1001 1 1 1 1 1 1 1 Students are allowed to use a maximum of 21 gates.
1010 1 0 1 1 1 1 1 1
0
0 A
1011 1 1 1 0 0 0 0 A'
B'
X1
1100 X X X X X X X
C
1101 X X X X X X X 1
D'
B
1110 1 0 1 1 0 1 1
0
0
X2
C'
B'
1111 X X X X X X X D
1 C
0 X3
0 C'
D'
C'
1
2
3
X4 4
1 D C' 5
0
0 D' 6
7
D'
C'
D
X5
C
B
D'
C
D
D'
C' X6
D'
B
C'
X7
C
278
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 8 Design Solutions
8.Q X1 X2 X3 X4
A B
(cont.) C D
A B
00 01 11 10 C D
A B
00 01 11 10 C D
A B
00 01 11 10 C D 00 01 11 10
00 0 00 0 00 0 00 0
01 X X X 01 X X X 01 X X X 01 X X X
11 X X X 11 X X X 11 X X X 11 X X X
10 0 10 0 10 10 0 0
X 1 = (A'+ B + C ) (A + B + C'+ D ) X 2 = (A'+ B'+ C ) (A'+ B + C') X3 = (A + B'+ C ) X4 = (A'+ B'+ C') (A'+ B + C ) (A + B + C'+ D )
X5 X7
A B A B A B
C D 00 01 11 10 C D 00 01 11 10 C D 00 01 11 10
00 0 00 0 00 0
01 X X X 01 X X X 01 X X X
11 0 X X X 11 X X X 11 X X X
10 0 0 0 0 10 0 0 0 10 0 0
X5 = (C') (A'+ B + C ) X 6 = (A + B'+ C ) (A'+ B'+ C') (A + C'+ D ) X7 = (A'+ B'+ C') (A + B + D )
1
0 A
0
A'
B X1
C
1 B
0
0 B
C'
D
B'
B
1 C C' X2
0
0
B'
C' C
B' X3
1
0 D C
0 1
2
3
X4
D' 4
B' 5
C' 6
7
X5
C
C'
D
X6
B'
B'
C'
X7
B
D
279
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 8 Design Solutions
8.R ABCD X1 X2 X3 X4 X5 X6 X7 X1 = (A + B + D') (B' + C' + D)
X2 = (B' + C' + D') (B + C + D) (used in circuit)
0000 X X X X X X X
X2 = (B' + C' + D') (A' + C + D)
0001 X X X X X X X X3 = (B' + C + D) (used in circuit)
0010 1 1 1 1 1 1 0 X3 = (A + C + D)
0011 0 1 1 0 0 0 0 X4 = (A + B + D') (B' + C' + D) (B + C + D') (used in circuit)
0100 1 1 0 1 1 0 1 X4 = (A + B + D') (B' + C' + D) (A' + C + D')
0101 1 1 1 1 0 0 1 X5 = (D') (B' + C') = D'(B' + C' + D)
0110 0 1 1 0 0 1 1 X6 = (B + C + D') (A + B + D') (A + C) (used in circuit)
0111 1 0 1 1 0 1 1 X6 = (A + B + D') (C + D') (A + C)
1000 1 0 1 1 1 1 1 X6 = (A + B + D') (C + D') (B' + C)
1001 1 1 1 0 0 0 0 X7 = (A + B) (B + C + D') (used in circuit)
1010 1 1 1 1 1 1 1 X7 = (A + B) (A' + C + D')
1011 1 1 1 1 0 1 1
This solution uses 15 gates and 37 gate inputs.
Students are allowed to use a maximum of 16 gates.
AB AB AB AB
CD 00 01 11 10 CD 00 01 11 10 CD 00 01 11 10 CD 00 01 11 10
00 X X 00 X X 0 00 X 0 X 00 X X
01 X X 01 X X 01 X X 01 X X 0
11 0 X 11 0 X 11 X 11 0 X
10 0 X 10 X 10 X 10 0 X
X1 = (B'+ C'+ D ) (A + B + D') X2 = (B'+ C'+ D') (B + C + D) X4 = (B'+ C'+ D ) (A + B + D') (B + C + D')
X3 = (B'+ C + D )
AB AB AB
CD 00 01 11 10 CD 00 01 11 10 CD 00 01 11 10
00 X X 00 X 0 X 00 X X
01 X 0 X 0 01 X 0 X 0 01 X X 0
11 0 0 X 0 11 0 X 11 0 X
10 0 X 10 0 X
10 X
1 A
0
0
B
A' D'
X1
B'
C'
D
1 B'
0 B C'
0
D' X2
B' B
C
D
1 C
1
0 B'
C X3
C' D
1
2
1 3
0 D B X4 4
0
C 5
D' 6
D' 7
X5
D
C X6
D'
X7
B
280
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 8 Design Solutions
8.S A1A2 A3 X1 X2 X3 X4 X5 X6 X7 X1 = (A1 + A2 + A3) (A1' + A3')
X2 = (A2 + A3') (A1' + A3')
0 0 0 0 1 0 0 0 1 1
X3 = 0
0 0 1 1 0 0 0 0 1 1 X4 = 0
0 1 0 1 1 0 0 0 1 0 X5 = 0
0 1 1 1 1 0 0 0 0 1 X6 = (A2' + A3') (A1' + A3')
1 0 0 1 1 0 0 0 1 1 X7 = (A1 + A2' + A3) (A1' + A3')
1 0 1 0 0 0 0 0 0 0
1 1 0 1 1 0 0 0 1 1 This solution uses 9 gates and 20 gate inputs.
1 1 1 0 0 0 0 0 0 0
Students are allowed to use a maximum of 11 gates.
1
0 A1
0
A1'
A3'
X1
A2
A3
1 A2
0
0
X2
A2'
A2 1
A3' 2
3
4
5
1 6
0 A3 X6
0 7
A2'
A3' A3'
X7
A2'
A3
281
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 8 Design Solutions
282
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Exploring the Variety of Random
Documents with Different Content
to any Camera. Lenses from the best Makers. Waxed and Iodized
Papers, &c.
65. CHEAPSIDE.
Trustees.
W. Whateley, Esq., Q.C.;
L. C. Humfrey, Esq., Q.C.;
George Drew, Esq.
VALUABLE PRIVILEGE.
Age £ s. d. Age £ s. d.
1 14 4 2 10 8
17 32
1 18 8 2 18 6
22 37
2 4 5 3 8 2
27 42
Now ready, price 10s. 6d., Second Edition, with material additions,
INDUSTRIAL INVESTMENT and EMIGRATION: being a TREATISE on
BENEFIT BUILDING SOCIETIES, and on the General Principles of
Land Investment, exemplified in the Cases of Freehold Land
Societies, Building Companies, &c. With a Mathematical Appendix on
Compound Interest and Life Assurance. By ARTHUR SCRATCHLEY,
M.A., Actuary to the Western Life Assurance Society, 3. Parliament
Street, London.
BY
Library Edition (Eighth), 14 vols. demy 8vo., with Portraits, 10l. 10s.
[This edition contains 100 pages of additional matter, and the price
has been reduced from 18s. to 15s.]
The Proceedings, Vol. V., Part II., are also ready, price 2s. 6d.
BOOKS ON SALE BY
1.D. The copyright laws of the place where you are located also
govern what you can do with this work. Copyright laws in most
countries are in a constant state of change. If you are outside
the United States, check the laws of your country in addition to
the terms of this agreement before downloading, copying,
displaying, performing, distributing or creating derivative works
based on this work or any other Project Gutenberg™ work. The
Foundation makes no representations concerning the copyright
status of any work in any country other than the United States.
1.E.6. You may convert to and distribute this work in any binary,
compressed, marked up, nonproprietary or proprietary form,
including any word processing or hypertext form. However, if
you provide access to or distribute copies of a Project
Gutenberg™ work in a format other than “Plain Vanilla ASCII” or
other format used in the official version posted on the official
Project Gutenberg™ website (www.gutenberg.org), you must,
at no additional cost, fee or expense to the user, provide a copy,
a means of exporting a copy, or a means of obtaining a copy
upon request, of the work in its original “Plain Vanilla ASCII” or
other form. Any alternate format must include the full Project
Gutenberg™ License as specified in paragraph 1.E.1.
• You pay a royalty fee of 20% of the gross profits you derive
from the use of Project Gutenberg™ works calculated using the
method you already use to calculate your applicable taxes. The
fee is owed to the owner of the Project Gutenberg™ trademark,
but he has agreed to donate royalties under this paragraph to
the Project Gutenberg Literary Archive Foundation. Royalty
payments must be paid within 60 days following each date on
which you prepare (or are legally required to prepare) your
periodic tax returns. Royalty payments should be clearly marked
as such and sent to the Project Gutenberg Literary Archive
Foundation at the address specified in Section 4, “Information
about donations to the Project Gutenberg Literary Archive
Foundation.”
• You comply with all other terms of this agreement for free
distribution of Project Gutenberg™ works.
1.F.
Most people start at our website which has the main PG search
facility: www.gutenberg.org.