TSC2003

TSC
2003 TSC2
003

SBAS162G – NOVEMBER 2000 – REVISED JUNE 2007

I2C TOUCH SCREEN CONTROLLER

FEATURES DESCRIPTION
● 2.5V TO 5.25V OPERATION The TSC2003 is a 4-wire resistive touch screen controller. It
● INTERNAL 2.5V REFERENCE also features direct measurement of two batteries, two aux-
● DIRECT BATTERY MEASUREMENT iliary analog inputs, temperature measurement, and touch-
(0.5V TO 6V) pressure measurement.
● ON-CHIP TEMPERATURE MEASUREMENT
● TOUCH-PRESSURE MEASUREMENT The TSC2003 has an on-chip 2.5V reference that can be
● I2C INTERFACE SUPPORTS: utilized for the auxiliary inputs, battery monitors, and tem-
Standard, Fast, and High-Speed Modes perature-measurement modes. The reference can also be
● AUTO POWER DOWN powered down when not used to conserve power. The
● TSSOP-16 AND VFBGA-48 PACKAGES internal reference will operate down to 2.7V supply voltage
while monitoring the battery voltage from 0.5V to 6V.
The TSC2003 is available in the small TSSOP-16 and
APPLICATIONS VFBGA-48 packages and is specified over the –40°C to
● PERSONAL DIGITAL ASSISTANTS +85°C temperature range.
● PORTABLE INSTRUMENTS
● POINT-OF-SALES TERMINALS
● PAGERS
● TOUCH SCREEN MONITORS
● CELLULAR PHONES
VDD

PENIRQ
TEMP0
X+
X– TEMP1
SCL

VDD
SAR

SDA
Y+ I2C
Y– Interface
Comparator and
Control
MUX CDAC Logic

A0
IN1 Internal
IN2 Clock
VBAT1 Channel Select

A1

VBAT2

Internal
VREF +2.5VREF

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Copyright © 2000-2007, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

www.ti.com
PACKAGE/ORDERING INFORMATION(1)
MAXIMUM MAXIMUM SPECIFIED
RELATIVE ACCURACY GAIN ERROR PACKAGE TEMPERATURE PACKAGE ORDERING
PRODUCT (LSB) (LSB) PACKAGE-LEAD DESIGNATOR RANGE MARKING NUMBER
TSC2003 ±2 ±4 TSSOP-16 PW –40°C to +85°C TSC2003I TSC2003IPW
TSC2003 ±2 ±4 TSSOP-16 PW –40°C to +85°C TSC2003I TSC2003IPWT
TSC2003 ±2 ±4 TSSOP-16 PW –40°C to +85°C TSC2003I TSC2003IPWR
TSC2003 ±2 ±4 TSSOP-16 PW –40°C to +85°C TSC2003I TSC2003IPWRG4
TSC2003 ±2 ±4 VFBGA-48 ZQC –40°C to +85°C BC2003 TSC2003IZQCT
TSC2003 ±2 ±4 VFBGA-48 ZQC –40°C to +85°C BC2003 TSC2003IZQCR

NOTE: (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or refer to our web
site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS(1)

ELECTROSTATIC
+VDD to GND ........................................................................ –0.3V to +6V
DISCHARGE SENSITIVITY Digital Input Voltage to GND ................................. –0.3V to +VDD + 0.3V
Analog Input Voltage to GND. All Pins Except 7, 8 ...... –0.3V to +VDD + 0.3V
This integrated circuit can be damaged by ESD. Texas Instru-
Analog Input Voltage Pins 7, 8 to GND ........................... –0.3V to +6.0V
ments recommends that all integrated circuits be handled with
Operating Temperature Range ........................................ –40°C to +85°C
appropriate precautions. Failure to observe proper handling Storage Temperature Range ......................................... –65°C to +150°C
and installation procedures can cause damage. Power Dissipation .......................................................... (TJ Max – TA)/θJA
ESD damage can range from subtle performance degrada- TSSOP Package
tion to complete device failure. Precision integrated circuits Junction Temperature (TJ Max) .............................................. +150°C

may be more susceptible to damage because very small θJA Thermal Impedance ................................................... +115.2°C/W
Lead Temperature, Soldering
parametric changes could cause the device not to meet its
Vapor Phase (60s) ............................................................ +215°C
published specifications.
Infrared (15s) ..................................................................... +220°C
VFBGA Package
PIN CONFIGURATION Junction Temperature (TJ Max) .............................................. +125°C

Top View TSSOP θJA Thermal Impedance ........................................................ +50°C/W

Lead Temperature, Soldering
+VDD 1 16 IN1 Vapor Phase (60s) ............................................................ +215°C
Infrared (15s) ..................................................................... +220°C
X+ 2 15 IN2

Y+ 3 14 A0 NOTE: (1) Stresses above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to absolute maximum
X– 4 13 A1
conditions for extended periods may affect device reliability.
TSC2003
Y– 5 12 SCL

GND 6 11 SDA
PIN DESCRIPTIONS
VBAT1 7 10 PENIRQ

VBAT2 8 9 VREF TSSOP VFBGA

PIN # PIN # NAME DESCRIPTION

1 C1, D1 +VDD Power Supply

Top View VFBGA
2 E1 X+ X+ Position Input
A0 A1 SCL SDA PENIRQ
3 F1 Y+ Y+ Position Input

4 G1 X– X– Position Input
1 2 3 4 5 6 7
A NC 5 G2 Y– Y– Position Input
IN2
6 G3, G4 GND Ground
B NC NC NC NC NC
IN1 VREF 7 G5 VBAT1 Battery Monitor Input

C NC NC NC NC NC 8 G6 VBAT2 Battery Monitor Input

+VDD
9 B7 VREF Voltage Reference Input/Output
D NC NC NC NC NC NC
+VDD 10 A7 PENIRQ Pen Interrupt. Open Drain Output (Requires
30kΩ to 100kΩ pull-up resistor externally).
E NC NC NC NC NC NC
X+ 11 A6 SDA Serial Data
F NC NC NC NC NC NC
12 A4 SCL Serial Clock
Y+

G NC
13 A3 A1 I2C Bus Address Input A1
14 A2 A0 I2C Bus Address Input A0

15 A1 IN2 Auxiliary A/D Converter Input

X− Y− GND GND VBAT1 VBAT2 16 B1 IN1 Auxiliary A/D Converter Input

NC = No Connection

2 TSC2003
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ELECTRICAL CHARACTERISTICS
At TA = –40°C to +85°C, +VDD = +2.7V, VREF = 2.5V external voltage, I2C bus frequency = 3.4MHz, 12-bit mode and digital inputs = GND or +VDD, unless
otherwise noted.

TSC2003I
PARAMETER CONDITIONS MIN TYP MAX UNITS
ANALOG INPUT
Full-Scale Input Span 0 VREF V
Absolute Input Range –0.2 +VDD +0.2 V
Capacitance 25 pF
Leakage Current 0.1 µA
SYSTEM PERFORMANCE
Resolution 12 Bits
No Missing Codes Standard and Fast Mode 11 Bits
High-Speed Mode 10 Bits
Integral Linearity Error Standard and Fast Mode ±2 LSB(1)
High-Speed Mode ±4 LSB
Offset Error ±6 LSB
Gain Error ±4 LSB
Noise Including Internal VREF 70 µVrms
Power-Supply Rejection Ratio 70 dB
SAMPLING DYNAMICS
Throughput Rate 50 ksps
Channel-to-Channel Isolation VIN = 2.5Vp-p at 50kHz 100 dB
SWITCH DRIVERS
On-Resistance
Y+, X+ 5.5 Ω
Y–, X– 7.3 Ω
Drive Current(2) Duration 100ms 50 mA
REFERENCE OUTPUT
Internal Reference Voltage 2.45 2.50 2.55 V
Internal Reference Drift 25 ppm/°C
Output Impedance Internal Reference ON 300 Ω
Internal Reference OFF 1 GΩ
Quiescent Current PD1 = 1, PD0 = 0, SDA, SCL High 750 µA
REFERENCE INPUT
Range 2.0 VDD V
Resistance PD1 = PD0 = 0 1 GΩ
BATTERY MONITOR
Input Voltage Range 0.5 6.0 V
Input Impedance Sampling Battery 10 kΩ
Battery Monitor OFF 1 GΩ
Accuracy External VREF = 2.5V –2 +2 %
Internal Reference –3 +3 %
TEMPERATURE MEASUREMENT
Temperature Range –40 +85 °C
Resolution Differential Method(3) 1.6 °C
TEMP0(4) 0.3 °C
Accuracy Differential Method(3) ±2 °C
TEMP0(4) ±3 °C
DIGITAL INPUT/OUTPUT
Logic Family CMOS
Logic Levels, Except PENIRQ
VIH | IIH | ≤ +5µA +VDD • 0.7 +VDD + 0.3 V
VIL | IIL | ≤ +5µA –0.3 +VDD • 0.3 V
VOH IOH = –250µA +VDD • 0.8 V
VOL IOL = 250µA 0.4 V
PENIRQ VOL 30kΩ Pull-Up 0.4 V
Data Format Straight
Binary
Input Capacitance SDA, SCL Lines 10 pF

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ELECTRICAL CHARACTERISTICS (Cont.)
At TA = –40°C to +85°C, +VDD = +2.7V, VREF = 2.5V external voltage, I2C bus frequency = 3.4MHz, 12-bit mode and digital inputs = GND or +VDD, unless
otherwise noted.

TSC2003I
PARAMETER CONDITIONS MIN TYP MAX UNITS

POWER-SUPPLY REQUIREMENTS
+VDD Specified Performance 2.7 3.6 V
Operating Range 2.5 5.25 V
Quiescent Current Internal Reference OFF,
PD1 = PD0 = 0
High-Speed Mode: SCL = 3.4MHz 254 650 µA
Fast Mode: SCL = 400kHz 95 µA
Standard Mode: SCL = 100kHz 63 µA
Internal Reference ON, PD0 = 0 1005 µA
Power-Down Current when Part is Internal Reference OFF,
Not Addressed PD1 = PD0 = 0
High-Speed Mode: SCL = 3.4MHz 90 µA
Fast Mode: SCL = 400kHz 21 µA
Standard Mode: SCL = 100kHz 4 µA
PD1 = PD0 = 0, SDA = SCL = +VDD 3 µA
Power Dissipation +VDD = +2.7V 1.8 mW
TEMPERATURE RANGE
Specified Performance –40 +85 °C

NOTES: (1) LSB means Least Significant Bit. With VREF equal to +2.5V, one LSB is 610µV. (2) Ensured by design, but not tested. Exceeding 50mA source current may
result in device degradation. (3) Difference between TEMP0 and TEMP1 measurement. No calibration necessary. (4) Temperature drift is –2.1mV/°C.

TIMING DIAGRAM

trDA
tfDA

SDA
tBUF

tLOW
trCL tfCL tHD; STA tSP

SCL

tHD; STA

tHD; DAT tSU; DAT

tSU; STA trCL1 tSU; STO
tHIGH

STOP START REPEATED

START

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TIMING CHARACTERISTICS
At TA = –40°C to +85°C, +VDD = +2.7V, unless otherwise noted. All values referred to VIHMIN and VILMAX levels.

PARAMETER SYMBOL CONDITIONS MIN MAX UNITS

SCL Clock Frequency fSCL Standard Mode 0 100 kHz
Fast Mode 0 400 kHz
High-Speed Mode, Cb = 100pF max 0 3.4 MHz
High-Speed Mode, Cb = 400pF max 0 1.7 MHz
Bus Free Time Between a STOP and tBUF Standard Mode 4.7 µs
Start Condition Fast Mode 1.3 µs
Hold Time (Repeated) START tHD; STA Standard Mode 4.0 µs
Condition Fast Mode 600 ns
High-Speed Mode 160 ns
LOW Period of the SCL Clock tLOW Standard Mode 4.7 µs
Fast Mode 1.3 µs
High-Speed Mode, Cb = 100pF max 160 ns
High-Speed Mode, Cb = 400pF max 320 ns
HIGH Period of the SCL Clock tHIGH Standard Mode 4.0 µs
Fast Mode 600 ns
High-Speed Mode, Cb = 100pF max 60 ns
High-Speed Mode, Cb = 400pF max 120 ns
Setup Time for a Repeated START tSU; STA Standard Mode 4.7 µs
Condition Fast Mode 600 ns
High-Speed Mode 160 ns
Data Setup Time tSU; DAT Standard Mode 250 ns
Fast Mode 100 ns
High-Speed Mode 10 ns
Data Hold Time tHD; DAT Standard Mode 0 3.45 µs
Fast Mode 0 0.9 µs
High-Speed Mode, Cb = 100pF max 0 70 ns
High-Speed Mode, Cb = 400pF max 0 150 ns
Rise Time of SCL Signal trCL Standard Mode 1000 ns
Fast Mode 20 + 0.1Cb 300 ns
High-Speed Mode, Cb = 100pF max 10 40 ns
High-Speed Mode, Cb = 400pF max 20 80 ns
Rise Time of SCL Signal After a trCL1 Standard Mode 1000 ns
Repeated START Condition and Fast Mode 20 + 0.1Cb 300 ns
After an Acknowledge Bit High-Speed Mode, Cb = 100pF max 10 80 ns
High-Speed Mode, Cb = 400pF max 20 160 ns
Fall Time of SCL Signal tfCL Standard Mode 300 ns
Fast Mode 20 + 0.1Cb 300 ns
High-Speed Mode, Cb = 100pF max 10 40 ns
High-Speed Mode, Cb = 400pF max 20 80 ns
Rise Time of SDA Signal trDA Standard Mode 1000 ns
Fast Mode 20 + 0.1Cb 300 ns
High-Speed Mode, Cb = 100pF max 10 80 ns
High-Speed Mode, Cb = 400pF max 20 160 ns
Fall Time of SDA Signal tfDA Standard Mode 300 ns
Fast Mode 20 + 0.1Cb 300 ns
High-Speed Mode, Cb = 100pF max 10 80 ns
High-Speed Mode, Cb = 400pF max 20 160 ns
Setup Time for STOP Condition tSU; STO Standard Mode 4.0 µs
Fast Mode 600 ns
High-Speed Mode 160 ns
Capacitive Load for SDA or SCL Cb Standard Mode 400 pF
Line Fast Mode 400 pF
High-Speed Mode, SCL = 1.7MHz 400 pF
High-Speed Mode, SCL = 3.4MHz 100 pF
Pulse Width of Spike Suppressed tSP Fast Mode 0 50 ns
High-Speed Mode 0 10 ns
Noise Margin at the HIGH Level for Standard Mode
Each Connected Device (Including VnH Fast Mode 0.2VDD V
Hysteresis) High-Speed Mode
Noise Margin at LOW Level for Each VnL Standard Mode
Connected Device (Including Fast Mode 0.1VDD V
Hysteresis) High-Speed Mode

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POWER-ON SEQUENCE TIMING
During TSC2003 power-up, the I2C bus should be idle. In supply pin will cause the TSC supply to ramp up more slowly
other words, the SDA and SCL lines must be high before the (refer to the Power-On Sequence timing diagram). If the TSC
TSC supply (+VDD) ramps up greater than 0.9V. If the TSC supply (+VDD) is different than the supply to the I2C bus pull-
uses the same supply as the the I2C bus pull-up resistors up resistors (VI2C), then VI2C should be turned on before the
(VI2C), then a 1µF capacitor placed very close to the TSC TSC supply (+VDD) is powered up.

POWER-ON SEQUENCE TIMING DIAGRAM

t1 ≥ 0
100% VDD
TSC Supply
+VDD ~ 0.9V
0V
SCL High
100% VI2C
SCL ~ 0.9V I2C Bus Activity
0V

100% VI2C
SDA ~ 0.9V SDA Low I2C Bus Activity
0V

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TYPICAL CHARACTERISTICS: +2.7V
At TA = +25°C, +VDD = +2.7V, VREF = External +2.5V, I2C bus frequency = 3.4MHz, PD1 = PD0 =0, unless otherwise noted.

SUPPLY CURRENT vs TEMPERATURE SUPPLY CURRENT vs VDD

300 1200
High-Speed Mode = 3.4MHz 1100
250 1000
High-Speed Mode = 3.4MHz
900

Supply Current (µA)

Supply Current (µA)

200 800
700
150 600
Fast Mode = 400kHz Fast Mode = 400kHz
500
100 400
Standard Mode = 100kHz
300
50 200
Standard Mode = 100kHz 100
0 0
–40 –20 0 20 40 60 80 100 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Temperature (°C) VDD (V)

SUPPLY CURRENT vs I2C BUS FREQUENCY SUPPLY CURRENT (Part Not Addressed) vs VDD
300 1000
900
High-Speed Mode = 3.4MHz
250 800
High-Speed Mode
Supply Current (µA)

Supply Current (µA)

700
200 600
500
150 400 Fast
Mode = 400kHz
300
100 200 Standard
Mode = 100kHz
100
Fast/Standard Mode
50 0
10 100 1000 10000 2.5 3.0 3.5 4.0 4.5 5.0 5.5
I2C Bus Frequency (kHz) VDD (V)

SUPPLY CURRENT (Part Not Addressed)

vs TEMPERATURE CHANGE IN GAIN vs TEMPERATURE
100 4.0
90
3.0
80
Gain Delta from +25˚C (LSB)

High-Speed Mode = 3.4MHz

2.0
Supply Current (µA)

70
60 1.0
50 0.0
Fast Mode = 400kHz
40
–1.0
30
–2.0
20
Standard Mode = 100kHz
10 –3.0
0 –4.0
–40 –20 0 20 40 60 80 100 –40 –20 0 20 40 60 80 100
Temperature (°C) Temperature (°C)

TSC2003 7
SBAS162G www.ti.com
TYPICAL CHARACTERISTICS: +2.7V (Cont.)
At TA = +25°C, +VDD = +2.7V, VREF = External +2.5V, I2C bus frequency = 3.4MHz, PD1 = PD0 =0, unless otherwise noted.

EXTERNAL REFERENCE CURRENT

CHANGE IN OFFSET vs TEMPERATURE vs TEMPERATURE
6.0 10
5.0 9

External Reference Current (µA)

Offset Delta from +25°C (LSB)

4.0
8
3.0 High-Speed Mode = 3.4MHz
7
2.0
1.0 6
0.0 5
–1.0 4
–2.0 Fast Mode = 400kHz
3
–3.0 Standard Mode = 100kHz
2
–4.0
–5.0 1
–6.0 0
–40 –20 0 20 40 60 80 100 –40 –20 0 20 40 60 80 100
Temperature (°C) Temperature (°C)

SWITCH-ON RESISTANCE vs VDD SWITCH-ON RESISTANCE vs TEMPERATURE

(X+, Y+: +VDD to Pin; X–, Y–: Pin to GND) (X+, Y+: +VDD to Pin; X–, Y–: Pin to GND)
9 9
X–
8 8
X–
7 7
Y–
6 6
Y–
RON (Ω)
RON (Ω)

5 5
Y+
4 4
X+ Y+ X+
3 3

2 2

1 1

0 0
2.5 3 3.5 4 4.5 5 5.5 –40 –20 0 20 40 60 80 100
VDD (V) Temperature (°C)

INTERNAL VREF vs TEMPERATURE INTERNAL VREF vs VDD

2.55 2.55
2.54 2.54
2.53 2.53
2.52 2.52
Internal VREF (V)
Internal VREF (V)

2.51 2.51
2.50 2.50
2.49 2.49
2.48 2.48
2.47 2.47
2.46 2.46
2.45 2.45
–40
–35
–30
–25
–20
–15
–10
–05
0
05
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85

2.5 3 3.5 4 4.5 5 5.5

Temperature (°C) VDD (V)

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TYPICAL CHARACTERISTICS: +2.7V (Cont.)
At TA = +25°C, +VDD = +2.7V, VREF = External +2.5V, I2C bus frequency = 3.4MHz, PD1 = PD0 =0, unless otherwise noted.

TEMP DIODE VOLTAGE vs TEMPERATURE TEMP0 DIODE VOLTAGE vs VDD (25°C)

850 614
800
TEMP1
Temp Diode Voltage (mV)

TEMP0 Diode Voltage (mV)

750 613
700

650
612
600
TEMP0
550
611
500

450
610
–40
–35
–30
–25
–20
–15
–10
–05
0
05
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
2.5 3.0 3.5 4.0 4.5 5.0 5.5
Temperature (°C)
VDD (V)

TEMP1 DIODE VOLTAGE vs VDD (25°C)

738

736
TEMP1 Diode Voltage (mV)

734

732
730

728

726

724
722

720
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

TSC2003 9
SBAS162G www.ti.com
THEORY OF OPERATION a differential input to the converter, and a differential refer-
ence architecture, it is possible to negate the switch’s on-
The TSC2003 is a classic Successive Approximation resistance error (should this be a source of error for the
Register (SAR) Analog-to-Digital (A/D) converter. The archi- particular measurement).
tecture is based on capacitive redistribution which inherently
includes a sample-and-hold function. The converter is fabri-
ANALOG INPUT
cated on a 0.6µ CMOS process.
See Figure 2 for a block diagram of the input multiplexer on
The basic operation of the TSC2003 is shown in Figure 1.
the TSC2003, the differential input of the A/D converter, and
The device features an internal 2.5V reference and an
the converter's differential reference.
internal clock. Operation is maintained from a single supply
of 2.7V to 5.25V. The internal reference can be overdriven When the converter enters the Hold mode, the voltage
with an external, low-impedance source between 2V and difference between the +IN and –IN inputs (see Figure 2) is
+VDD. The value of the reference voltage directly sets the captured on the internal capacitor array. The input current on
input range of the converter. the analog inputs depends on the conversion rate of the
device. During the sample period, the source must charge
The analog input (X, Y, and Z parallel coordinates, auxiliary
the internal sampling capacitor (typically 25pF). After the
inputs, battery voltage, and chip temperature) to the con-
capacitor has been fully charged, there is no further input
verter is provided via a multiplexer. A unique configuration of
current. The amount of charge transfer from the analog
low on-resistance switches allows an unselected A/D con-
source to the converter is a function of conversion rate.
verter input channel to provide power, and an accompanying
pin to provide ground for an external device. By maintaining

Voltage +2.7V to +5V

Regulator

1.2kΩ 1.2kΩ 50kΩ

1µF TSC2003
to +
0.1µF
10µF
(Optional) 1 +VDD IN1 16 Auxiliary Input

2 X+ IN2 15 Auxiliary Input

3 Y+ A0 14

Touch 4 X– A1 13
Screen
5 Y– SCL 12 Serial Clock

6 GND SDA 11 Serial Data

7 VBAT1 PENIRQ 10 Pen Interrupt

8 VBAT2 VREF 9
1µF
+ to
0.1µF 10µF
(Optional)

Main Secondary
Battery Battery

FIGURE 1. Basic Operation of the TSC2003.

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 PENIRQ +VDD VREF

TEMP1 TEMP0

C2-C0 C3
(Shown 101B) (Shown HIGH)

X+

X–

Ref ON/OFF

Y+ +REF
+IN
Y–
Converter
–IN
2.5V –REF
Reference

7.5kΩ
VBAT1

7.5kΩ
VBAT2
2.5kΩ 2.5kΩ

Battery Battery
On On
IN1
IN2
GND

FIGURE 2. Simplified Diagram of the Analog Input.

INTERNAL REFERENCE
Reference
The TSC2003 has an internal 2.5V voltage reference that Power Down
can be turned ON or OFF with the power-down control bits,
PD0 and PD1 (see Table II and Figure 3). The internal
reference is powered down when power is first applied to the
device.
The internal reference voltage is only used in the
VREF
single-ended reference mode for battery monitoring, tem- Band
Gap Buffer
perature measurement, and for measuring the auxiliary in-
put. Optimal touch screen performance is achieved when
Optional
using a ratiometric conversion; thus, all touch screen mea- To
CDAC
surements are done automatically in the differential mode.
FIGURE 3. Simplified Diagram of the Internal Reference.

TSC2003 11
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REFERENCE INPUT REFERENCE MODE
The voltage difference between +REF and –REF (see There is a critical item regarding the reference when making
Figure 2) sets the analog input range. The TSC2003 will measurements while the switch drivers are ON. For this
operate with a reference in the range of 2V to +VDD. There are discussion, it is useful to consider the basic operation of the
several critical items concerning the reference input and its TSC2003 (see Figure 1). This particular application shows
wide-voltage range. As the reference voltage is reduced, the the device being used to digitize a resistive touch screen. A
analog voltage weight of each digital output code is also measurement of the current Y position of the pointing device
reduced. This is often referred to as the LSB (Least Significant is made by connecting the X+ input to the A/D converter,
Bit) size, and is equal to the reference voltage divided by 4096 turning on the Y+ and Y– drivers, and digitizing the voltage
(256 if in 8-bit mode). Any Offset or Gain error inherent in the on X+, as shown in Figure 4. For this measurement, the
A/D converter will appear to increase, in terms of LSB size, as resistance in the X+ lead does not affect the conversion; it
the reference voltage is reduced. For example, if the offset of does, however, affect the settling time, but the resistance is
a given converter is 2LSBs with a 2.5V reference, it will usually small enough that this is not a concern. However,
typically be 2.5LSBs with a 2V reference. In each case, the since the resistance between Y+ and Y– is fairly low, the
actual offset of the device is the same, 1.22mV. With a lower on-resistance of the Y drivers does make a small difference.
reference voltage, more care must be taken to provide a clean Under the situation outlined so far, it would not be possible
layout including adequate bypassing, a clean (low-noise, low- to achieve a 0V input or a full-scale input regardless of where
ripple) power supply, a low-noise reference (if an external the pointing device is on the touch screen because some
reference is used), and a low-noise input signal. voltage is lost across the internal switches. In addition, the
The voltage into the VREF input is not buffered, and directly internal switch resistance is unlikely to track the resistance of
drives the Capacitor Digital-to-Analog Converter (CDAC) the touch screen, providing an additional source of error.
portion of the TSC2003. Therefore, the input current is very This situation is remedied, as shown in Figure 5, by using the
low, typically < 6µA. differential mode: the +REF and –REF inputs are connected
directly to Y+ and Y–, respectively. This makes the A/D
converter ratiometric. The result of the conversion is always a
percentage of the external reference, regardless of how it
+VDD VREF
changes in relation to the on-resistance of the internal switches.

+VDD

Y+

+REF
+IN
X+ Y+
Converter
–IN
–REF

+REF
+IN
Y– X+
Converter
–IN
–REF
GND

Y–

FIGURE 4. Simplified Diagram of Single-Ended Reference.

GND

FIGURE 5. Simplified Diagram of Differential Reference (Y

Switches Enabled, X+ is Analog Input).

12 TSC2003
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Differential reference mode always uses the supply voltage, the Temperature Coefficient (TC) of this voltage is very
through the drivers, as the reference voltage for the A/D consistent at –2.1mV/°C. During the final test of the end
converter. VREF cannot be used as the reference voltage in product, the diode voltage would be stored at a known room
differential mode. temperature, in memory, for calibration purposes by the user.
It is possible to use a high-precision reference on VREF in The result is an equivalent temperature measurement reso-
single-ended reference mode for measurements which do lution of 0.3°C/LSB.
not need to be ratiometric (i.e., battery voltage, temperature
measurement, etc.). In some cases, it could be possible to
power the converter directly from a precision reference. Most
references can provide enough power for the TSC2003, but
they might not be able to supply enough current for the X+
external load, such as a resistive touch screen.
MUX A/D
Converter
TOUCH SCREEN SETTLING
In some applications, external capacitors may be required
across the touch screen for filtering noise picked up by the
touch screen (i.e., noise generated by the LCD panel or
backlight circuitry). These capacitors will provide a low-pass Temperature Select
filter to reduce the noise, but they will also cause a settling
TEMP0 TEMP1
time requirement when the panel is touched. The settling
time will typically show up as a gain error. The problem is that
the input and/or reference has not settled to its final steady-
FIGURE 6. Functional Block Diagram of Temperature Mea-
state value prior to the A/D converter sampling the input(s),
surement Mode.
and providing the digital output. Additionally, the reference
voltage may still be changing during the measurement cycle.
The second mode does not require a test temperature
To resolve these settling time problems, the TSC2003 can be
calibration, but uses a two-measurement method to eliminate
commanded to turn on the drivers only without performing a
the need for absolute temperature calibration and for achiev-
conversion (see Table I). Time can then be allowed before
ing 2°C/LSB accuracy. This mode requires a second conver-
the command is issued to perform a conversion. Generally,
sion with an address of C3 = 0, C2 = 1, C1 = 0, and C0 = 0,
the time it takes to communicate the conversion command
with an 91 times larger current. The voltage difference
over the I2C bus is adequate for the touch screen to settle.
between the first and second conversion using 91 times the
bias current will be represented by kT/q • 1n (N), where N is
TEMPERATURE MEASUREMENT the current ratio = 91, k = Boltzmann's constant (1.38054 •
In some applications, such as battery recharging, a measure- 10–23 electrons volts/degrees Kelvin), q = the electron charge
ment of ambient temperature is required. The temperature (1.602189 • 10–19 C), and T = the temperature in degrees
measurement technique used in the TSC2003 relies on the Kelvin. This mode can provide improved absolute tempera-
characteristics of a semiconductor junction operating at a ture measurement over the first mode, but at the cost of less
fixed current level to provide a measurement of the tempera- resolution (1.6°C/LSB). The equation to solve for °K is:
ture of the TSC2003 chip. The forward diode voltage (VBE) q • ∆V
has a well-defined characteristic versus temperature. The °K = (1)
k • 1n(N)
temperature can be predicted in applications by knowing the
25°C value of the VBE voltage and then monitoring the delta where:
of that voltage as the temperature changes. The TSC2003
∆V = V(I91) – V(I1) (in mV)
offers two modes of temperature measurement.
∴ oK = 2.573∆VoK/mV
The first mode requires calibrations at a known temperature,
o
but only requires a single reading to predict the ambient C = 2.573 • ∆V(mV) – 273o K
temperature. A diode is used during this measurement cycle.
NOTE: The bias current for each diode temperature mea-
The voltage across the diode is connected through the MUX
surement is only turned ON during the acquisition mode,
for digitizing the diode forward bias voltage by the A/D
and, therefore, does not add any noticeable increase in
converter with an address of C3 = 0, C2 = 0, C1 = 0, and
power, especially if the temperature measurement only oc-
C0 = 0 (see Table I and Figure 6 for details). This voltage is
curs occasionally.
typically 600mV at +25°C, with a 20µA current through it. The
absolute value of this diode voltage can vary a few millivolts;

TSC2003 13
SBAS162G www.ti.com
BATTERY MEASUREMENT The second method requires knowing both the X-Plate and
An added feature of the TSC2003 is the ability to monitor the Y-Plate resistance, measurement of X-Position and Y-Posi-
battery voltage on the other side of the voltage regulator tion, and Z1. Equation 3 calculates the touch resistance using
(DC/DC converter), as shown in Figure 7. The battery voltage the second method:
can vary from 0.5V to 6V, while the voltage regulator main-
R X −Plate • X − Position  4096 
tains the voltage to the TSC2003 at 2.7V, 3.3V, etc. The input R TOUCH =  – 1
voltage (VBAT1 or VBAT2) is divided down by 4 so that a 6.0V 4096  1Z 
battery voltage is represented as 1.5V to the A/D converter.  Y − Position  (3)
–R Y −Plate • 1– 
The simplifies the multiplexer and control logic. In order to  4096 
minimize the power consumption, the divider is only ON
during the sample period which occurs after control bits C3
= 0, C2 = 0, C1 = 0, and C0 = 1 (VBAT1) or C3 = 0, C2 = 1,
C1 = 0, and C0 = 1 (VBAT2) are received. See Tables I and
II for the relationship between the control bits and configura-
Measure X-Position
tion of the TSC2003.
X+ Y+

Touch
DC/DC 2.7V
Converter
Battery
X-Position
0.5V +
to
X– Y–
6.0V VDD

Measure Z1-Position
X+ Y+
0.125V to 1.5V
VBAT A/D Touch
Converter
7.5kΩ

Z1-Position
2.5kΩ
X– Y–

X+ Y+
FIGURE 7. Battery Measurement Functional Block Diagram.
Touch
PRESSURE MEASUREMENT
Measuring touch pressure can also be done with the TSC2003. Z2-Position
To determine pen or finger touch, the pressure of the “touch”
X– Y–
needs to be determined. Generally, it is not necessary to Measure Z2-Position
have high accuracy for this test, therefore, the 8-bit resolution
mode is recommended. However, calculations will be shown
with the 12-bit resolution mode. There are several different
ways of performing this measurement—the TSC2003 sup-
FIGURE 8. Pressure Measurement Block Diagrams.
ports two methods.
The first method requires knowing the X-Plate resistance,
DIGITAL INTERFACE
measurement of the X-Position, and two additional
cross-panel measurements (Z2 and Z1) of the touch screen, The TSC2003 supports the I2C serial bus and data transmis-
as shown in Figure 8. Using Equation 2 will calculate the sion protocol in all three defined modes: standard, fast, and
touch resistance: high-speed. A device that sends data onto the bus is defined
as a transmitter, and a device receiving data as a receiver.
X − Position  Z2  The device that controls the message is called a master. The
RTOUCH = RX −Plate •  – 1
4096  Z1  (2) devices that are controlled by the master are slaves. The bus
 
must be controlled by a master device which generates the

14 TSC2003
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serial clock (SCL), controls the bus access, and generates stable LOW during the HIGH period of the acknowledge clock
the START and STOP conditions. The TSC2003 operates as pulse. Of course, setup and hold times must be taken into account.
a slave on the I2C bus. Connections to the bus are made via A master must signal an end of data to the slave by not generating
the open-drain I/O lines SDA and SDL. an acknowledge bit on the last byte that has been clocked out of
The following bus protocol has been defined, as shown in the slave. In this case, the slave must leave the data line HIGH to
Figure 9: enable the master to generate the STOP condition.
• Data transfer may be initiated only when the bus is not busy. Figure 9 details how data transfer is accomplished on the I2C
bus. Depending upon the state of the R/W bit, two types of
• During data transfer, the data line must remain stable
data transfer are possible:
whenever the clock line is HIGH. Changes in the data line
while the clock line is HIGH will be interpreted as control • Data transfer from a master transmitter to a slave
signals. receiver. The first byte transmitted by the master is the
slave address. Next follows a number of data bytes. The
Accordingly, the following bus conditions have been defined:
slave returns an acknowledge bit after the slave address
Bus Not Busy: Both data and clock lines remain HIGH. and each received byte.
Start Data Transfer: A change in the state of the data line, • Data transfer from a slave transmitter to a master
from HIGH to LOW, while the clock is HIGH defines a START receiver. The first byte (the slave address) is transmitted
condition. by the master. The slave then returns an acknowledge bit.
Stop Data Transfer: A change in the state of the data line, Next, a number of data bytes are transmitted by the slave
from LOW to HIGH, while the clock line is HIGH defines a to the master. The master returns an acknowledge bit
STOP condition. after all received bytes other than the last one. At the end
Data Valid: The state of the data line represents valid data of the last received byte, a ‘not acknowledge’ is returned.
when, after a START condition, the data line is stable for the The master device generates all of the serial clock pulses
duration of the HIGH period of the clock signal. There is one and the START and STOP conditions. A transfer is ended
clock pulse per bit of data. with a STOP condition or a repeated START condition. Since
Each data transfer is initiated with a START condition and a repeated START condition is also the beginning of the next
terminated with a STOP condition. The number of data bytes serial transfer, the bus will not be released.
transferred between START and STOP conditions is not The TSC2003 may operate in the following two modes:
limited, and is determined by the master device. The informa- • Slave Receiver Mode: Serial data and clock are received
tion is transferred byte-wise, and each receiver acknowl- through SDA and SCL. After each byte is received, an
edges with a ninth-bit. acknowledge bit is transmitted. START and STOP condi-
Within the I2C bus specifications, a standard mode (100kHz tions are recognized as the beginning and end of a serial
clock rate), a fast mode (400kHz clock rate), and a transfer. Address recognition is performed by hardware
high-speed mode (3.4MHz clock rate) are defined. The after reception of the slave address and direction bit.
TSC2003 works in all three modes. • Slave Transmitter Mode: The first byte (the slave ad-
Acknowledge: Each receiving device, when accessed, is dress) is received and handled as in the slave receiver
obliged to generate an acknowledge after the reception of mode. However, in this mode the direction bit will indicate
each byte. The master device must generate an extra clock that the transfer direction is reversed. Serial data is
pulse, which is associated with this acknowledge bit. transmitted on SDA by the TSC2003 while the serial clock
A device that acknowledges must pull down the SDA line during is input on SCL. START and STOP conditions are recog-
the acknowledge clock pulse in such a way that the SDA line is nized as the beginning and end of a serial transfer.

SDA

Slave Address R/W

Acknowledgement
Direction
Signal from
Bit
Receiver

Acknowledgement
Signal from
Receiver

SCL 1 2 6 7 8 9 1 2 3-7 8 9
ACK ACK
START STOP Condition
Condition Repeated If More Bytes Are Transferred or Repeated
START Condition

FIGURE 9. I2C Bus Protocol.

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SBAS162G www.ti.com
Address Byte The internal reference voltage can be turned ON or OFF
The address byte, as shown in Figure 10, is the first byte independently of the A/D converter. This can allow extra time
received following the START condition from the master for the internal reference voltage to settle to its final value prior
device. The first five bits (MSBs) of the slave address are to making a conversion. Make sure to allow this extra wake-
factory preset to 10010. The next two bits of the address byte up time if the internal reference was powered down. Also note
are the device select bits: A1 and A0. Input pins (A1-A0) on that the status of the internal reference power down is latched
the TSC2003 determine these two bits of the device address into the part (internally) when a STOP or repeated START
for a particular TSC2003. Therefore, a maximum of four occurs at the end of a command byte (see Figures 12 and 14).
devices with the same preset code can be connected on the Therefore, in order to turn the internal reference OFF, an
same bus at one time. additional write to the TSC2003, with PD1 = 0, is required after
the channel has been converted.
It is recommended to set PD0 = 0 in each command byte to get
MSB LSB
the lowest power consumption possible. If multiple X-, Y-, and
1 0 0 1 0 A1 A0 R/W
Z-position measurements will be done one right after another,
such as when averaging, PD0 =1 will leave the touch screen
FIGURE 10. Address Byte. drivers on at the end of each conversion cycle.
• M: Mode bit. If M is 0, the TSC2003 is in 12-bit mode. If
The A1-A0 Address Inputs can be connected to VDD or digital M is 1, 8-bit mode is selected.
ground. The last bit of the address byte (R/W) defines the
• X: Don’t care.
operation to be performed. When set to a “1”, a read
operation is selected; when set to a “0”, a write operation is PD1 PD0 PENIRQ DESCRIPTION
selected. Following the START condition, the TSC2003
0 0 Enabled Power-Down Between Conversions
monitors the SDA bus and checks the device type identifier 0 1 Disabled Internal reference OFF, ADC(1) ON
being transmitted. Upon receiving the 10010 code, the ap- 1 0 Enabled Internal reference ON, ADC(1) OFF
1 1 Disabled Internal reference ON, ADC(1) ON
propriate device select bits, and the R/W bit, the slave device
outputs an acknowledge signal on the SDA line. NOTE: (1) ADC = Analog-to Digital Converter.

Command Byte TABLE II. Power-Down Bit Functions.

The TSC2003’s operating mode is determined by a com-
mand byte, which is shown in Figure 11. When the TSC2003 powers up, the power-down mode bits
need to be written to ensure that the part is placed into the
desired mode to achieve lowest power. Therefore, immedi-
MSB LSB
ately after power-up, a command byte should be sent which
C3 C2 C1 C0 PD1 PD0 M X sets PD1 = PD0 = 0, so that the device will be in the lowest
power mode, powering down between conversions.
FIGURE 11. Command Byte. Start A Conversion/Write Cycle
The bits in the device command byte are defined as follows: A Conversion/Write Cycle begins when the master issues the
address byte containing the slave address of the TSC2003,
• C3-C0: Configuration bits. These bits set the input multi-
with the eighth bit equal to a 0 (R/W = 0), as shown in Figure
plexer address and functions that the TSC2003 will per-
10. Once the eighth bit has been received, and the address
form, as shown in Table I.
matches the A1-A0 address input pin setting, the TSC2003
• PD1-PD0: Power-down bits. These two bits select the issues an acknowledge.
power-down mode that the TSC2003 will be in after the
current command completes, as shown in Table II.

C3 C2 C1 C0 FUNCTION INPUT to ADC X-DRIVERS Y-DRIVERS REFERENCE MODE

0 0 0 0 Measure TEMP0 TEMP0 OFF OFF Single-Ended
0 0 0 1 Measure VBAT1 VBAT1 OFF OFF Single-Ended
0 0 1 0 Measure IN1 IN1 OFF OFF Single-Ended
0 0 1 1 Reserved – – – Single-Ended
0 1 0 0 Measure TEMP1 TEMP1 OFF OFF Single-Ended
0 1 0 1 Measure VBAT2 VBAT2 OFF OFF Single-Ended
0 1 1 0 Measure IN2 IN2 OFF OFF Single-Ended
0 1 1 1 Reserved – – – Single-Ended
1 0 0 0 Activate X– Drivers – ON OFF Differential
1 0 0 1 Activate Y– Drivers – OFF ON Differential
1 0 1 0 Activate Y+, X– Drivers – X– ON Y+ ON Differential
1 0 1 1 Reserved – – – Differential
1 1 0 0 Measure X Position Y+ ON OFF Differential
1 1 0 1 Measure Y Position X+ OFF ON Differential
1 1 1 0 Measure Z1 Position X+ X– ON Y+ ON Differential
1 1 1 1 Measure Z2 Position Y– X– ON Y+ ON Differential

TABLE I. Possible Input Configurations.

16 TSC2003
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Once the master receives the acknowledge bit from the Read A Conversion/Read Cycle
TSC2003, the master writes the command byte to the slave For best performance, the I2C bus should remain in an idle
(see Figure 11). After the command byte is received by the state while an A/D conversion is taking place. This prevents
slave, the slave issues another acknowledge bit. The master digital clock noise from affecting the bit decisions being made
then ends the Write Cycle by issuing a repeated START or by the TSC2003. The master should wait for at least 10µs
a STOP condition, as shown in Figure 12. before attempting to read data from the TSC2003 to realize
If the master sends additional command bytes after the initial this best performance. However, the master does not need
byte, before sending a STOP or repeated START condition, to wait for a completed conversion before beginning a read
the TSC2003 will not acknowledge those bytes. from the slave, if full 12-bit performance is not necessary.
The input multiplexer for the A/D converter has its channel Data access begins with the master issuing a START condition
selected when bits C3 through C0 are clocked in. If the followed by the address byte (see Figure 10) with R/W = 1.
selected channel is an X-,Y-, or Z-position measurement, the Once the eighth bit has been received, and the address
appropriate drivers will turn on once the acquisition period matches, the slave issues an acknowledge. The first byte of
begins. serial data will follow (D11-D4, MSB first).
When R/W = 0, the input sample acquisition period starts on After the first byte has been sent by the slave, it releases the
the falling edge of SCL once the C0 bit of the command byte SDA line for the master to issue an acknowledge. The slave
has been latched, and ends when a STOP or repeated responds with the second byte of serial data upon receiving
START condition has been issued. A/D conversion starts the acknowledge from the master (D3-D0, followed by four 0
immediately after the acquisition period. The multiplexer bits). The second byte is followed by a NOT acknowledge bit
inputs to the A/D converter are disabled once the conversion (ACK = 1) from the master to indicate that the last data byte
period starts. However, if an X-, Y-, or Z-position is being has been received. If the master acknowledges the second
measured, the respective touch screen drivers remain on data byte, then the data will repeat on subsequent reads with
during the conversion period. A complete Write Cycle is ACKs between bytes. This is true in both 12-bit and 8-bit
shown in Figure 12. mode. The master will then issue a STOP condition, which
ends the Read Cycle, as shown in Figure 13.

SCL

Address Byte Command Byte

R/W
SDA 1 0 0 1 0 A1 A0 0 0 C3 C2 C1 C0 PD1 PD0 M X 0

TSC2003 TSC2003
ACK ACK

START Acquisition Conversion

STOP or
REPEATED START

FIGURE 12. Complete I2C Serial Write Transmission.

SCL

Address Byte Date Byte 1 Date Byte 2

SDA 1 0 0 1 0 A1 A0 R/W 0 D11 D10 D9 D8 D7 D6 D5 D4 0 D3 D2 D1 D0 0 0 0 0 1

1

TSC2003 MASTER MASTER

START ACK ACK NACK
STOP or
REPEATED START

FIGURE 13. Complete I2C Serial Read Transmission.

TSC2003 17
SBAS162G www.ti.com
I2C High-Speed Operation
The TSC2003 can operate with high-speed I2C masters. To FS = Full-Scale Voltage = VREF(1)
1LSB = VREF(1)/4096
do so, the simple resistor pull-up on SCL must be changed
to the active pull-up, as recommended in the I2C specification. 1LSB
11...111
The I2C bus will be operating in standard or fast mode
11...110
initially. Following a START condition, the master will send
the code 00001xxx, which the slave will not acknowledge. At 11...101

Output Code
this point, the bus is now operating in high-speed mode. The
bus will remain in high-speed mode until a STOP condition
occurs. Therefore, to maximize throughput only repeated 00...010

STARTs should be used to separate transactions. 00...001

Since the TSC2003 may not have completed a conversion 00...000

before a read to the part can be requested, the TSC2003 is

capable of stretching the clock until the converted data is 0V FS – 1LSB
Input Voltage(2) (V)
stored in its internal shift register. Once the data is latched,
the TSC2003 will release the clock line so that the master NOTES: (1) Reference voltage at converter: +REF – (–REF). See Figure 2.
can receive the converted data. A complete high-speed (2) Input voltage at converter, after multiplexer: +IN – (–IN). See Figure 2

Conversion Cycle is shown in Figure 14.

Data Format
FIGURE 15. Ideal Input Voltages and Output Codes.
The TSC2003 output data is in Straight Binary format, as
shown in Figure 15. This shows the ideal output code for the
given input voltage, and does not include the effects of LAYOUT
offset, gain, or noise.
The following layout suggestions should provide optimum
8-Bit Conversion performance from the TSC2003. However, many portable
The TSC2003 provides an 8-bit conversion mode (M = 1) applications have conflicting requirements concerning power,
that can be used when faster throughput is needed, and the cost, size, and weight. In general, most portable devices
digital result is not as critical (for example, measuring pres- have fairly “clean” power and grounds because most of the
sure). By switching to the 8-bit mode, a conversion result can internal components are very low power. This situation would
be read by transferring only one data byte. mean less bypassing for the converter's power, and less
This shortens each conversion by four bits and reduces data concern regarding grounding. Still, each situation is unique,
transfer time which results in fewer clock cycles and provides and the following suggestions should be reviewed carefully.
lower power consumption.

F/S Mode HS-Mode Enabled

S 0 0 0 0 1 X X X N

A/D Converter Power-Down Mode A/D Converter Powers Up and Begins Sampling
Sr 1 0 0 1 0 A1 A0 W A C3 C2 C1 C0 PD1 PD0 M X A

Fixed Address Part Programmable

A/D Converter Stops Sampling and Begins Conversion Using Internal Clock

Sr 1 0 0 1 0 A1 A0 R A SCLH is stretched LOW until A/D Converter is finished converting data.

A/D Converter Goes Into Power-Down Mode After Finishing Conversion (If PD0 = 0) Exit HS-Mode and Enter F/S Mode

D11 D10 D9 D8 D7 D6 D5 D4 A D3 D2 D1 D0 0 0 0 0 N P

16 Bits + Ack

S = START = Master Controls Bus

Sr = REPEATED START
P = STOP = Slave Controls Bus

FIGURE 14. High-Speed I2C Mode Conversion Cycle.

18 TSC2003
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For optimum performance, care should be taken with the PENIRQ output is HIGH. While in the power-down mode, with
physical layout of the TSC2003 circuitry. The basic SAR archi- PD0 = 0, the Y– driver is ON and connected to GND, and the
tecture is sensitive to glitches or sudden changes on the power PENIRQ output is connected to the X+ input. When the panel
supply, reference, ground connections, and digital inputs that is touched, the X+ input is pulled to ground through the touch
occur just prior to latching the output of the analog comparator. screen, and PENIRQ output goes LOW due to the current path
Therefore, during any single conversion for an n-bit SAR through the panel to GND, initiating an interrupt to the processor.
converter, there are n “windows” in which large external tran- During the measurement cycle for X-, Y-, and Z-Position, the X+
sient voltages can easily affect the conversion result. Such input will be disconnected from the PENIRQ pull-down transis-
glitches might originate from switching power supplies, nearby tor to eliminate any leakage current from the pull-up resistor to
digital logic, and high-power devices. The degree of error in the flow through the touch screen, thus causing no errors.
digital output depends on the reference voltage, layout, and the In addition to the measurement cycles for X-, Y-, and Z-
exact timing of the external event. The error can change if the position, commands which activate the X-drivers, Y-drivers, Y+
external event changes in time with respect to the SCL input. and X-drivers without performing a measurement also discon-
With this in mind, power to the TSC2003 should be clean and nect the X+ input from the PENIRQ pull-down transistor and
well bypassed. A 0.1µF ceramic bypass capacitor should be disable the pen-interrupt output function regardless of the value
placed as close to the device as possible. In addition, a 1µF of the PD0 bit. Under these conditions, the PENIRQ output will
to 10µF capacitor may also be needed if the impedance of be forced LOW. Furthermore, if the last command byte written
the connection between +VDD and the power supply is high. to the TSC2003 contains PD0 = 1, the pen-interrupt output
A bypass capacitor is generally not needed on the VREF pin function will be disabled and will not be able to detect when the
because the internal reference is buffered by an internal op panel is touched. In order to re-enable the pen-interrupt output
amp. If an external reference voltage originates from an op function under these circumstances, a command byte needs to
amp, make sure that it can drive any bypass capacitor that be written to the TSC2003 with PD0 = 0.
is used without oscillation. Once the bus master sends the address byte with R/W = 0
The TSC2003 architecture offers no inherent rejection of noise (see Figure 10) and the TSC2003 sends an acknowledge,
or voltage variation in regards to using an external reference the pen-interrupt function is disabled. If the command which
input. This is of particular concern when the reference input is follows the address byte has PD0 = 0, then the pen-interrupt
tied to the power supply. Any noise and ripple from the supply function will be enabled at the end of a conversion. This is
will appear directly in the digital results. While high-frequency approximately 10µs (12-bit mode) or 7µs (8-bit mode) after
noise can be filtered out, voltage variation due to line fre- the TSC2003 receives a STOP/START condition following
quency (50Hz or 60Hz) can be difficult to remove. the reception of a command byte (see Figures 12 and 14 for
further details of when the conversion cycle begins).
The GND pin should be connected to a clean ground point. In
many cases, this will be the “analog” ground. Avoid connec- In both cases listed above, it is recommended that the
tions which are too near the grounding point of a microcontroller master processor mask the interrupt which the PENIRQ is
or digital signal processor. If needed, run a ground trace associated with whenever the host writes to the TSC2003.
directly from the converter to the power-supply entry point. The This will prevent false triggering of interrupts when the
ideal layout will include an analog ground plane dedicated to PENIRQ line is disabled in the cases listed above.
the converter and associated analog circuitry.
VDD
In the specific case of use with a resistive touch screen, care
should be taken with the connection between the converter
and the touch screen. Since resistive touch screens have 30kΩ to 100kΩ

fairly low resistance, the interconnection should be as short VDD

PENIRQ
and robust as possible. Longer connections will be a source
of error, much like the on-resistance of the internal switches. VDD
10kΩ
Likewise, loose connections can be a source of error when TEMP0 TEMP1
the contact resistance changes with flexing or vibrations.
Y+
As indicated previously, noise can be a major source of error in HIGH except
when TEMP0,
touch screen applications (e.g., applications that require a backlit TEMP1 activated TEMP
DIODE
LCD panel). This EMI noise can be coupled through the LCD panel
to the touch screen and cause “flickering” of the converted data. X+

Several things can be done to reduce this error, such as utilizing a

touch screen with a bottom-side metal layer connected to ground.
This will couple the majority of noise to ground. Additionally, filtering Y–
ON
capacitors from Y+, Y–, X+, and X– to ground can also help.
Y+ or X+ drivers on,
or TEMP0, TEMP1
PENIRQ OUTPUT measurements activated

The pen-interrupt output function is shown in Figure 16. By FIGURE 16. PENIRQ Functional Block Diagram.
connecting a pull-up resistor to VDD (typically 100kΩ), the

TSC2003 19
SBAS162G www.ti.com
 Revision History

DATE REVISION PAGE SECTION DESCRIPTION

6/07 G 6 Timing Added Power-On Sequence Timing section.

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

20 TSC2003
www.ti.com SBAS162G
 PACKAGE OPTION ADDENDUM

www.ti.com 13-Jul-2022

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TSC2003IPW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TSC Samples
2003I
TSC2003IPWG4 ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TSC Samples
2003I
TSC2003IPWR ACTIVE TSSOP PW 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TSC Samples
2003I

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 13-Jul-2022

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TSC2003 :

• Automotive : TSC2003-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Dec-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TSC2003IPWR TSSOP PW 16 2500 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Dec-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TSC2003IPWR TSSOP PW 16 2500 350.0 350.0 43.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Dec-2023

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
TSC2003IPW PW TSSOP 16 90 530 10.2 3600 3.5
TSC2003IPWG4 PW TSSOP 16 90 530 10.2 3600 3.5

Pack Materials-Page 3
 PACKAGE OUTLINE
PW0016A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1

2X
5.1 4.55
4.9
NOTE 3

8
9
0.30
4.5 16X 1.2 MAX
B 0.19
4.3
NOTE 4 0.1 C A B

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE
0.15
0.05

0.75
0.50
0 -8
DETAIL A
A 20

TYPICAL

4220204/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

www.ti.com
 EXAMPLE BOARD LAYOUT
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000

4220204/A 02/2017
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220204/A 02/2017
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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