ECSE6967-RFIC Design Fall2005

Tutorial

Voltage Controlled Oscillators

Prepared By: Burak Catli
([email protected])

1
1. Introduction
Accurate modeling of spiral inductors on-chip is a key factor in realizing oscillators with
oscillation frequency and amplitude that agree with the required specifications. Figure 1
shows a typical design flow-chart that involves modeling and optimization of the spiral
inductors on-chip at a given frequency.

Inductor Optimization
(Electro-magnetic
Simulations)

S-Parameter
Simulations

Conversion of S-param
file into equivalent
circuit model (Curve
Fitting)

LC VCO Design based

on accurate estimation
of passive elements

Figure 1: LC-Based VCO Design Flow Chart

Although the currently-existing inductor models provided by many companies, including

IBM, Jazz and UMC have high accuracy within a certain frequency range, the accuracy
of the model is a function of the type of performed analysis (AC, transient, PSS, etc), and
the location of the inductor in the circuit [1,5]

A typical spiral inductor model is shown in figure 2 [2]. This model can be used with
acceptable accuracy while performing ac analysis on an LC oscillator circuit. However,
the results will be deviated from their actual values when performing transient and PSS
analysis. This is due to 1) there is a dc path from port 1 to ground through the R-C
modeling the substrate, which is shown in the dotted line. This dc path will affect the dc
analysis of the LC Oscillator circuit. 2) While this problem can be alleviated by using the

2
model in figure 2b, the differential nature of the LC oscillator will create an ac ground
between the two used inductors that will change the nature of the model and remove the
effect of the second R-C branch representing the substrate as shown in figure 3 [1].

(a) (b)

Figure 2: (a) Symmetric spiral inductor model. (b) Modified model to maintain the
accuracy of dc-analysis [2]

L1
M L2

Figure 3: Effect of differential operation in typical LC oscillators on the accuracy

of the inductor models [1].

In order to ensure the accuracy of the models provided in the design kit and guarantee
measurement results that would agree with simulation results, we will start with either
EM simulations or directly using an inductor from the design kit with the maximum
quality factor close to the operating frequency. EM simulators are available from
different vendors (ADS, AWR, Ansoft, Sonnet, etc) and you can even find free software

3
on the web (ASITIC). Use either to perform parametric analysis using the inductor
dimensions while sweeping the frequency within the required frequency range. Choose
the inductor value that will produce the maximum quality factor at the operating
frequency. The EM simulator will provide an s-parameter file that can be used to obtain
the elements in the models shown in figure 2. You can also get the same file by
performing s-param simulations on the inductor you have chosen from the kit.

We need to convert the model in figure 2 to a distributed structure that can be used for
accurate estimation of circuit performance. This distributed model is obtained by
cascading unit cells of the compact model with scaled values as shown in figure 4.

L1

28.2fF

2.71nH
56.4fF 3.05

56.4fF

5.2K
5.2K

R /10 (a)
Cx10

CSD CSD

LD RSD
LD RSD
…….
CPD CPD

L/10
RPD
RPD

1 2 3 10
Fitting parameters
(b)
Figure 4: Conversion of compact inductor model in a cascaded model. The fitting
parameters are obtained by modifying RPD and CPD such that S parameter
simulations of models (a) and (b) match.

Based on the above discussion, the parameters of the distributed model are
RSD=320mΩ
RPD=250 Ω
LD=270pH
CSD=200fF
CPD=10fF

The equivalent resistance/conductance can be roughly calculated by using the equivalent

model in figure 5.
.

4
 1 Rs
gL = +
RP (ωL) 2
1 3.05
gL = +
5.3K (2.7nHx2 xπx 2.4GHz) 2
g L = 2.02mS
RL = 495Ω

Figure 5: Finding the equivalent losses (GL,

RL)

Perform the following AC analysis to verify the results of the previous calculations.
You can do this using the compact model in figure 4(a) and the distributed model in
figure 4(b). Scan the frequency logarithmically from 1GHz to 5GHz with 1000 points per
decade. The test schematic is shown in figure 6. Compare the performance of both
models. The results should closely agree with an equivalent RL=495 Ω -500Ω.
Select a proper value of capacitance that
resonates with L(2.7nH) at
2.4GHz(C=1.6pF)
Or use the proper values from the design
Iac=1 kit

28.2fF

C 2.71nH

L 3.05Ω

56fF
56fF
5.3KΩ 5.3KΩ

RL

Figure 6: Test schematic to measure the value of Q-factor for the LC-tank, and
estimate the losses (RL)

5
Active Device Sizing

Consider the equivalent circuit model discussed in lecture 13 and proposed by Ham and
Hajimiri in [2, 3]. The total tank loss (GL=1/RL) is given as follows

2 g tan k = g on + g op + g v + g L
Where gon is the output conductance of the NMOS, gop is the output conductance of the
PMOS transistors and gv represents the loss in the varactor, while gL represents the loss in
the inductor. Assuming that gL is the dominant factor
2 g tan k ≈ g L
, and the effective conductance is
2 g active = g mn + g mp
Where gmn, and gmp are the transconductance of the N, and P transistors and should be
equal to reduce the contribution of 1/f noise to the phase noise [4].

To guarantee oscillations, the following condition should be satisfied;

g active ≥ α min g tan k

g mn + g mp
≥ (2 − 3) g tan k
2
gL
g mn = g mp , and g tan k =
2
Thus, g mn = g mp ≥ 3mS
W
gmn = 2μ n C ox ID
L
Knowing the values of gmn, and gmp, we can determine the dimensions of the devices
knowing the value of the drain current (ID).
ID is determined by the output voltage swing requirements, using the illustrative
schematic in Figure 7,

I tan k ,max ≅ I tail

I tail
V AB ≅
gL / 2
For a peak to peak amplitude of 1V from a single - ended signal at node (A) or (B)
1V = I tail * (2 * 495Ω)
(node B not shown in Figure 7)
We can use the square-law formula to find the gm of the different transistors. However,
for deep sub-micron technologies transistors, the accuracy of the square law model is
very low, and it is better to rely on dc analysis performed on a real transistor from the
library as shown in Figure 8.

6
 A
RL RL

Itail

Figure 7: LC oscillator at the resonance point (To calculate the output voltage swing).

Figure 8: Estimation of the transistor dimension using DC simulations knowing gm.

7
Select the minimum length “L” for both transistors to reduce the effective capacitance,
change Wp, and Wn to obtain the required gm.

The transistors sizes should be equal to

Wn 10.4um
= [ g m = 3.059mS ] [20 fingers ]
Ln 0.24um
Wp 26um
= [ g m = 3.005mS ] [20 fingers ]
Lp 0.24um

Now, we have all circuit parameters to start simulating the oscillator. Choose the value of
the tank capacitance to be slightly lower than the estimated 1.6pF since we have to
include the effective capacitance of the cross-coupled transistors. The tank capacitance
that would give you the required oscillating frequency of 2.4GHz is approximately 1.5pF.

Perform transient analysis on the circuit shown in figure 9. Use the transient simulation
results to view the output voltage swing and the total current flowing in the tank. Notice
that the maximum value of Itank is slightly higher than Itail due to the capacitive
components of Idn, and Idp. This results in a higher value for the output swing than the
estimated 1V

From transient simulation results,

I tan k = I dn + I dp ≈ 1.138mA > I tail (1mA)

Where Idn, and Idp are the drain current in the n and p transistors respectively.

Varactor Design

Figure 9: Schematic of a PMOS transistor with source and drain connected together
to act as an inversion made capacitance.

8
Varactors (variable reactors or voltage controlled capacitors) are used to tune the
oscillation frequency [7]. Because of practical reasons, we will use “inversion mode”
varactor in this tutorial. Note that this varactor is a custom design. You can also use the
varactors in the IBM Design Kit Library.

Note that the minimum and the maximum value of the capacitance of the varactor
determine the oscillation frequency range. Although we can determine the input
capacitance of a varactor for an operating point, we can not use this value to determine
the exact value of oscillation frequency. Because the node X is exposed to large signal
swing during the oscillation, the capacitance seen by the tank deviates as a function of
swing (or time) [6,8]. Now we will first consider the DC characteristic of a varactor, then
we will calculate the effective capacitance of the varactor, which is approximately the
average capacitance seen by the tank depending on swing.

Figure 10: The typical DC characteristic of the inversion mode varactor.

The dc characteristic of the inversion-mode varactor, shown in figure 10, can be

simulated using the two following techniques.

I- AC analysis

Figure 11: AC analysis to estimate the dc characteristic of the used varactor.

9
To reduce the gate resistance, use multi-finger structure!
To reduce channel resistance, select minimum length “L” for the transistors.

After performing an ac analysis, plot the imaginary of the ac current as shown in figure
11.

Figure 11: The imaginary part of the ac current equals=2πfCvar.

II- DC and Parametric Analysis (preferred method)

Figure 12: Simulation of the DC characteristic.

10
We will use both DC and parametric analysis. Assign a variable to DC source as a DC
voltage value. Set an operating point simulation. Open parametric analysis window. Enter
the DC value variable. Define a region (start and stop value, step size) for the variable, as
in the case of DC sweep. Run the simulation, once simulations are done, use “calculator”,
and select op button (operating point) and select the transistor. A little window is opened,
select “cgg” term in the list. Then click OK and plot. This will results in the characteristic
similar to that shown in figure 12.

Figure 12: Use DC-parametric analysis to obtain the C-V characteristic of the
inversion-mode varactor.

Finding the dimensions of the varactor:

woscmin < wosc < woscmax

1 1
< w osc <
LC var,max LC var,min

Select wvar, such that, when VBG is changed over a meaningful range, the varactor is able
to satisfy both Cvar,min and Cvar,max.

To start the optimization one approach may be to bias the varactor in the vicinity of its
MOS transistor’s threshold voltage and change the channel width to obtain the nominal
value.

Figure 13: Test setup for the varactor

Now we can characterize the varactor.
Select Wvar [channel width of varactor], such that, when VBG is changed over a
meaningful range, the varactor is able to satisfy both Cvar,min and Cvar,max.

11
To start the optimization, one approach may be to bias the varactor in the vicinity of its
MOS transistor’s threshold voltage and change the channel width to obtain the nominal
value.

SIMULATION SETUP, STEADY STATE RESPONSE, PSS:

Figure 14: Simulation results of the inversion-mode capacitance

Figure 15: A complete schematic for the LC-Oscillator

12
 Figure 16: Setting the requirements on the output voltage swing

Use the schematic in figure 15 to perform Periodic Steady State analysis to find the
oscillation frequency and the waveform. Set VTUNE=2.2V, thus the average value of
VBG= 2.2-1.67≅0.5V and average capacitance seen from the tank is 1.5pF. (Remember
that the common mode level of differential swing is in the vicinity of 1.7 V as shown in
Figure 16)
To perform this analysis, in the analog design environment window,

1- Analysis → Choose → PSS

2- In the beat frequency field, enter 2.4G (you should enter an expected frequency
value)
3- Number of harmonics → 10
4- Accuracy defaults → conservative
5- Check the “oscillator”

13
 Figure 17: An example for the converting the differential output to a single-ended
signal.

You can use a VCVS instance from analogLib as shown in figure 17, to define a unique
output node. In the oscillator section, select “vout” as oscillator node, and select ground
“/gnd!” as reference node. Be sure the enabled box is checked. Click OK and run the
simulation.

Select

Results → Direct Plot→ Main Form

Select PSS (analysis)
Select Voltage (Function)
Select time (sweep)
Select the net “Vout” on the schematic.

You will see just one period of the differential swing of oscillator. You can check at the
end of the output log file to find the oscillation frequency [2.357 GHz]. This is very close
to the frequency value that we obtained by using linear 1.5pF capacitors [2.34 GHz].

By changing the VTUNE and running the simulation again you can find another oscillation
frequency. If you repeat this process, you can obtain the frequency tuning characteristic
of the oscillator. Thus VTUNE versus fosc characteristic and the gain of the oscillator can be
found. To do this, fill the table and draw the given tuning curve characteristic as shown in
figure 18.

14
 VTUNE [V] fosc[Hz]
1.5
1.6
1.7
1.8
1.9
2
2.1
2.2 2.357G
2.3
2.4

Figure 18: The tuning characteristics of the simulated VCO.

PHASE NOISE SIMULATION:

In addition to the already described PSS simulation, use PNOISE to estimate the phase
noise of the oscillator.

1- Analysis → Choose → pnoise

2- Sweep type → Relative!!! [very important, with respect to fundamental
component]
3- Relative harmonic → enter 1
4- Start-stop (frequency sweep range)

15
 Start → 1k
Stop → 100M
5- Sweep Type → select logarithmic then highlight “number of steps”, enter 201
6- Maximum sideband → enter 7 (you can increase this number, until the output
noise stops changing)
7- In the output cyclic field, choose voltage
8- Output → select → voltage and select positive output node → “Vout”
Select → negative output node → “/gnd!”
Input source → select →none
9- Verify that pnoise analysis is enabled
10- Click OK then run the simulation

To see the pnoise simulation results

Select Results→ Direct plot → Main form

Select –>Pnoise
Function → Output Noise
Modifier →dB20
Signal level→ A/sqrt(Hz)
Click Plot

This will plot the frequency offset versus phase noise characteristic.

Note:

Please note that, for the sake of simplicity, we ignored several issues that are related to
a commercial LC oscillators design, such as the output buffer implementation, layout
techniques, current source design etc. These issues will affect the performance of the
oscillator considerably.

References:
[1] B. Razavi, Design of Integrated Circuits for Optical Communication
Systems, McGraw-Hill, 2003.

[2] D. Ham and A. Hajimiri, "Concepts and Methods in Optimization of

Integrated LC VCOs," IEEE Journal of Solid-State Circuits, vol. 36, no.
6, pp. 896-909, June 2001.

[3] D. Ham and A Hajimiri, "Design and Optimization of a Low Noise 2.4GHz
CMOS VCO with Integrated LC Tank and MOSCAP Tuning," Proc. of IEEE
International Symposium on Circuits and Systems, pp. 331-334, May 2000.

[4] A. Hajimiri and T. H. Lee, The Design of Low Noise Oscillators,

Kluwer Academic, 1999.

[5] A. Zolfaghari, A. Y. Chan, and B. Razavi, "Stacked Inductors and

1-to-2 Transformers in CMOS Technology," IEEE Journal of Solid-State
Circuits, vol. 36, pp. 620-628, April 2001.

16
[6] Marc Tiebout, "Low-Power Low-Phase-Noise Differentially Tuned
Quadrature VCO Design in Standard CMOS", IEEE Journal of Solid-State
Circuits, Vol. 36, No. 7, pp. 1018-1024, July 2001.

[7] Andreani, P.; Mattisson, "On the use of MOS varactors in RF VCOs",
IEEE Journal of Solid-State Circuits, Volume 35, Issue 6, June 2000
Page(s):905 – 910.

[8] Bunch, R.L.; Raman, S, " Large-signal analysis of MOS varactors in

CMOS -G/sub m/ LC VCOs", IEEE Journal of Solid-State Circuits, Volume 38,
Issue 8, Aug. 2003 Page(s):1325 – 1332.

17