COA Lab Assignment-2

Assignment 1 8 X 0.5= 4
1. Write an instruction, which moves number 7 to register R01.

MOV #7 R01

2. Execute the above instruction

3. Create an instruction, which moves number 8 to register R02.

MOV #8 R02

4. Create an instruction, which adds the contents of R01 and R02.

ADD R01, R02

(NOTE: Have added my BITS ID in red colour on the screenshots I have added, have kept
screenshot from the question paper itself and haven’t added any ID)

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 COA Lab Assignment-2
5. Execute it and show the register that holds the result

6. Create an instruction, which pushes the above result to the top of the hardware
stack, and then execute it.
PSH R02

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 COA Lab Assignment-2
7. Create an instruction to push number -2 on top of the stack and execute it. Show the
value in Program Stack
PSH #-2

8. Create an instruction to pop the value on top of the Program Stack into register
R03.Execute it and observe the value in SP register

POP R03

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 COA Lab Assignment-2
2. Assignment [ 12 X 0.5 = 6]
1. Enter the following source code,
2. One can open the copiler as shown below

3. 1st compile it and then load in simulator’s memory: As shown

To reach the following window

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 COA Lab Assignment-2

program Ex1
for n = 1 to 20
p = p + 1 next
end

Added program to compiler screenshot

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 COA Lab Assignment-2
Screenshot before running the program

4. Open the CPU pipeline window and list the names of stages here.

Pipeline Stages Screenshot

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 COA Lab Assignment-2
5. Check the box titled Stay on top and make sure No instruction pipeline check box is
selected. And run the program. Run the program and observe the pipeline. Wait for the
program to complete. Now make a note of the following values

CPI 5.04

SF .99

Inst counts 166

Clks 836

Verify that clks= CPI X instruction count

6. Next, uncheck the No instruction pipeline checkbox, reset and run the above
program again and wait for it to complete.

Unpipelined Stages screenshot

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 COA Lab Assignment-2

7. Note down your observation on how the pipeline visually behaved differently
Fetch
Decode
Read Operands
Execute
Write Result
Data Hazard
Stage Busy
Control Hazard
Instruction Sequence Sync

Unpipelined stages values

CPI 1.92

SF 2.6

Inst counts 166

Clks 318

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 COA Lab Assignment-2

Verify that Instruction count= clks/CPI And 𝑆𝐹 = 𝐶𝑃𝐼𝑢𝑛𝑝𝑖𝑝𝑒𝑙𝑖𝑛𝑒𝑑 / 𝐶𝑃𝐼𝑃𝑖𝑝𝑒𝑙𝑖𝑛𝑒

Instruction count = 318/1.92=166

SF= 1.92/5.04 = 0.38

9. Briefly explain why you think there is a difference in the two sets of values:

Pipeline Hazards: There may be a high number of stalls or bubbles in the pipeline due to
dependencies (data hazards) or mispredicted branches (control hazards).
Pipeline Structural Issues: Resource conflicts (e.g., multiple instructions trying to use the same
resource) could also be a reason for the poor performance of the pipelined system.
Misleading Parallelism: If the instruction sequence is not well-suited for pipelining (for example,
many branch instructions or data dependencies), the overhead of managing the pipeline could
outweigh the performance benefits.

10. Enter the following program and compile it with ONLY the Enable optimizer and
Remove redundant code check boxes selected. Load the compiled program in the CPU.

program jmpprdct
i = 0 for p = 1 to 40 i = i + 1 if i = 10 then
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i=0
r=i
end if next
end

Added Program to compiler screenshot

11. Run the program and make a note of the following pipeline stats:

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 COA Lab Assignment-2
CPI 5.03

SF 0.99

Inst counts 297

Clks 1493

12. Now, in the pipeline window select the Enable jump prediction check box. Reset the
program and run it again. Make a note of the following pipeline stats:

CPI 1.96

SF 2.55

Inst counts 297

Clks 582

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13. Try to Explain the difference

Branch Prediction Efficiency: The unpipelined processor benefits from effective jump
prediction, reducing wasted cycles due to mispredictions. The pipelined processor, on the
other hand, is more vulnerable to frequent branch mispredictions, causing costly pipeline
flushes and stalls.
Pipeline Hazards: Pipelining introduces hazards (data, control, structural), leading to stalls
that increase CPI. Poor handling of these hazards in the pipelined processor contributes to
a higher CPI compared to the unpipelined version.
Execution Overhead: In the pipelined processor, stalls and flushes cause it to take more
cycles to complete the same number of instructions (1493 clocks vs. 582 in the
unpipelined processor).

14. Show the jump table and try to explain the terms

V V (Validity Bit) indicates whether the entry in the jump table is valid or invalid.

1: The entry is valid and 0: The entry is invalid.

JInstAddr JInstAddr (Jump Instruction Address)is the address in memory where the jump (or
branch) instruction is located. It specifies which instruction in the program is
attempting to perform a jump.

JTarget JTarget (Jump Target Address) is the target address the program will jump to if the
branch/jump is taken. This is the destination of the jump, where the program will
continue execution if the branch condition is true.

PStat PStat (Prediction Status) represents the branch prediction status or prediction
outcome.

1: The branch or jump was predicted to be taken and 0: The branch or jump was
predicted to be not taken.

Count Count (Prediction Count) tracks how often the prediction status has been correct. It
is typically used in conjunction with dynamic branch prediction mechanisms like 2-
bit saturation counters to improve the accuracy of jump predictions.

A count of 0 typically indicates that the prediction status was incorrect and if the
count is high, it indicates that the branch predictor has made multiple correct
predictions in the past, leading to a higher confidence in future predictions.

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