Microelectronics Journal 115 (2021) 105205

Contents lists available at ScienceDirect

Microelectronics Journal
journal homepage: www.elsevier.com/locate/mejo

Design and implementation of 20-T hybrid full adder for high-performance

arithmetic applications
Jyoti Kandpal *, Abhishek Tomar, Mayur Agarwal
Department of Electronics and Communication, College of Technology, G. B. Pant University of Agriculture and Technology, Pantnagar, Uttarakhand, India

A R T I C L E I N F O A B S T R A C T

Keywords: Most of the full adder (FA) circuits are implemented through a hybrid logic style using three different modules.
Full voltage swing The principal peculiarity of these hybrid logic style-based FA cells is that each module could be optimized
XOR–XNOR individually to improve the circuit performance. A high-performance 1-bit hybrid FA cell is proposed with pass
Full adder
transistor logic and transmission gate logic in the present work. The proposed FA circuit is implemented using
Transmission gate
Pass transistor logic
20-transistors to achieve optimum performance. The proposed circuit is simulated in Cadence virtuoso tool by
using 90-nm process CMOS technology. Comparison of the design matrices for the proposed 1-bit hybrid FA cell
against the five different reported FA circuits is also carried out. The present study reported 13.01–54.93 % and
13.01–59.20 % improvement in terms of delay and power delay product (PDP), respectively, compared to other
FA designs. The proposed circuit is also investigated in different supply voltages (0.6–1.5V). Furthermore, the FA
circuit is verified in different process corner conditions to check the robustness.

1. Introduction voltage scaling. However, the major drawback of this FA design is the
presence of PMOS block, and due to the low mobility of PMOS, perfor­
High performance is one of the essential features in electronic de­ mance is degraded; therefore, to improve the performance, PMOS
vices, like personal digital assistants (PDAs), cellular phones, and transistors are sized up [2].
Internet of Things (IoT) devices [1]. High-speed circuits are needed for Another classical approach to implement the FA design is the com­
high performance to cope with the high operating frequency and com­ plementary pass-transistor logic style (CPL). This CPL logic style uses a
plex designs. In the application-specific electronic devices, digital signal dual rail structure with 32-transistors to implement the FA design. This
processors or microprocessors have Arithmetic and Logic Unit (ALU) as a structure offers a full voltage swing at the output node, high speed, and
primary block. The adder module is the core element of the ALU circuit. good driving capabilities. However, the main demerit of this circuit is
FA is also the fundamental building block for several arithmetic circuit high power dissipation owing to a large number of internal nodes in the
operations, for example, multipliers, compressors, and comparators. cell. Another problem with this FA design is that the layout is complex
Hence, improvement in the performance of the adder circuits is one of because of the irregular transistor arrangement [3].
the leading research areas of the VLSI researchers to enhance the per­ Pass transistor logic (PTL) is also a classical approach that can be
formance of the digital system. Different static logic styles are used, and used to realize the FA design. However, the threshold loss problem arises
these logic styles are generally divided into two groups: conventional when logic "1" and logic "0" pass-through NMOS and PMOS transistors,
logic and hybrid logic styles [2–6]. respectively. Therefore, to resolve the issue of the threshold problem, a
In the conventional style-based full adder, only one logic is used to new logic style is used, which is the transmission gate (TG) logic style.
implement the whole FA design. The complementary metal-oxide- To implement the FA using the TG logic style, 20-transistors are used.
semiconductor (CMOS) based FA is an example of the classical This type of adder has low power consumption; however, the main
approach, which is implemented using pull-up (PMOS) and pull-down demerit of this type of adder is the weak driving capability [2,3].
(NMOS) network. In this approach, 28-transistors are used to realize Subsequently, FA is realized using a hybrid style to overcome the
the full adder. This circuit offers full voltage swing at all the external and problem of conventional style-based FA circuits. In the hybrid style,
internal nodes and provides robustness against the transistor sizing and multiple classical styles optimize the circuit’s performance [5,6].

* Corresponding author.
E-mail addresses: [email protected] (J. Kandpal), [email protected] (A. Tomar), [email protected] (M. Agarwal).

https://doi.org/10.1016/j.mejo.2021.105205
Received 20 January 2021; Received in revised form 26 July 2021; Accepted 8 August 2021
Available online 13 August 2021
0026-2692/© 2021 Published by Elsevier Ltd.
J. Kandpal et al. Microelectronics Journal 115 (2021) 105205

In a hybrid FA structure, three different modules are used. In the first

module, the two input signals (A& B) are applied that deliver full swing
signals (XOR & XNOR) at the output. These XOR-XNOR signals should
have good driving proficiency to drive the SUM and CARRY circuits. The
second and third modules generate the sum and carry output corre­
spondingly using the outputs of the first module and the third carry
input signal (CIN). This type of FA design offers the full voltage swing at
the output node and good driving capability to transmit the signals
further [6–10].
Furthermore, hybrid FA is classified based on its internal structures.
Aguirre [9] presented the internal logic architecture of the FA, which is
shown in Fig. 1 (a). This first module (XOR/XNOR) of FA is realized
using double pass transistor logic (DPL). Module second and module
third are implemented using XOR/XNOR and AND/OR gate, respec­
tively. Another internal configuration of the FA proposed by Kumar [12]
is presented in Fig. 1(b). The first module (XOR/XNOR) of this FA
configuration is realized through swing restored complementary pass
transistor logic (SR-CPL). The second and third modules are imple­
mented using XOR/XNOR and NAND/NOR gates, respectively. One
more internal architecture of the hybrid FA design given by Valashani
[13] is displayed in Fig. 1(c). In this design, the XOR- XNOR functions
are produced through the first module, and these generated signals show
good driving capability and provide the full output swing concurrently.
The second and third modules are the SUM and CARRY circuits realized
using the TG and MUX circuits.
The main advantage of these hybrid logic styles is that one can mend
each module individually and improve performance through good
interfacing among different modules. On the other hand, the perfor­
mance of this type of hybrid logic is degraded if it is implemented
through different cascading stages due to reducing in the driving
capability.
A high-performance XOR-XNOR design is used in this paper, pro­
posed by Kandpal et al., 2018 [14]. The Proposed XOR-XNOR is realized
using CPL logic with one static inverter and has a symmetrical structure
without cross-coupling. Further, XOR-XNOR provides simultaneous
XOR-XNOR logic, balanced output, and exhibits full voltage swing in all
internal and external nodes. The designed XOR-XNOR is used as the first
module of the hybrid FA design. Module II and III are used to implement
sum and carry logic in a FA and can be implemented using different
topologies in CMOS. Therefore, the performance evaluation of the pro­
posed XOR-XNOR module is to be checked in FA. In this paper, the
XOR-XNOR design is used in the FA, which is used to resolve comp­
abilities issues and improve the Full adder’s performance. In the pro­
posed FA design, module II and module III are implemented using the TG
and multiplexer (MUX). It uses only 20-transistors and reported low
power consumption with lesser delay. In the present study, the FA circuit
is simulated using the Cadence Virtuoso tool in 90 nm CMOS technology
at 1.2 VDD.
The rest of this work is organized as follows. Section II gives a brief
introduction to the proposed XOR-XNOR circuits. The hybrid FA design
with module II and Module III is discussed in section III. Section IV ex­
plains the simulation results and analytical comparisons, and Section V
gives the conclusion.
Fig. 1. Three internal configurations of hybrid FA cell (a). Aguirre’s logic
2. XOR-XNOR design structure [9] (b). Kumar’s logic structure [12] (c). Valashani’s logic struc­
ture [13].
There are primarily two methods for designing the XOR-XNOR cir­
cuit in the literature. The XOR function is generated at first in the performance. This configuration is implemented using the CPL and
foremost method, and then the XNOR function is produced by using an feedback restorer transistors, and only six transistors are used to provide
inverter [2,11,20]. XOR and XNOR signals are delivered separately, due full swing at XOR-XNOR outputs. In this design, the slow response
to which false switching and glitches arise in the output of the second problem arises when the AB equals 00 and AB equals 11 inputs are
and third modules. In another method, XOR–XNOR signals are gener­ applied due to the two-step process. Another implementation of the
ated simultaneously at the output; therefore, the delay variation among XOR-XNOR circuit is presented by Valashani [13]. In this design, one
XOR-XNOR signals could be minimized in various designs [13–19]. NMOS and one PMOS transistor are added at the output node (XOR and
An XOR-XNOR circuit presented by Radhakrishnan [4] is shown in XNOR), which have inverted input at the source site, as presented in
Fig. 2. (a), which various researchers modify to improve its

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J. Kandpal et al. Microelectronics Journal 115 (2021) 105205

Fig. 3. XOR-XNOR full swing logic generation.

transistors (P2 & P3) are connected in parallel as PTL logic. In addition,
transistors (N2 & N3) are also implemented with pass transistors where
the source and gate relate inverted input B, respectively. On the other
hand, on the XNOR side, transistors (N4 &N5) are linked in parallel as
PTL, and transistors (P4 & P5) are also implemented with pass transis­
tors the source and gate are connected with inverted input B, respec­
tively. To understand the operation of the proposed design, the
upcoming section presents an overview of the different input
combinations.
When the input AB equals "01", then P2, N5, P4, and P5 transistors
turn "ON." As a result, P2 and N5 transistors give the logic "1" and logic
"0" at the outputs node (XOR-XNOR). Simultaneously, transistors P4 and
P5 get "ON" and pass -Vthp (weak logic) at the XNOR output. Corre­
spondingly, when the input AB equals "10", P3, N2, N3, and N4 tran­
sistors get "ON" and P3, and N4 transistors pass logic "1" and logic "0" at
the output node (XOR-XNOR), individually. At the same time, transis­
tors N2 and N3 turn "ON," these transistors (N2 and N3) pass the VDD-
Vthn (weak logic) on the XOR node. Thus, the input AB equals "01" and
"10", the weak logic outputs do not affect the output swing as the full
swing path is available for outputs.
The input AB equals "00", P2, P3, P4, and N2 transistors get "ON". P2
and P3 pass -Vthp (weak logic) at the XOR output, whereas N2 gives full
logic "1" on the XOR node, and at the same time P4 transistor turns "ON,"
and it passes the logic "1" at the XNOR output. Similarly, when input AB
equals "11", N3, N4, N5, and P5 transistors get "ON." The N4 and N5
transistors pass VDD-Vthn (weak logic) on the XNOR node. In contrast,
transistor P5 gives the complete logic" 1" on the XNOR node, and
simultaneously transistor (N3) gets "ON," and thereby, the logic "1" is
passed at the XNOR node.This circuit facilitates low power consump­
tion, higher speed, and a smaller transistor count with full output swing
and good driving power at all the nodes.

3. Proposed full adder design

The proposed FA circuit is realized as presented in Fig. 1(c) using

three different modules. First, the second and third module generates the
sum and carry output, respectively. Second, each module is imple­
mented independently to optimized the circuit performance in terms of
Fig. 2. XOR/XNOR circuit (a). Radhakrishnan [4] (b). Valashani [13] (c). power consumption, delay, and area. These modules are discussed in the
Kandpal [15]. following section.

Fig. 2(b). This design also reported a higher delay problem due to the 3.1. Module II
two-step transition. Kandpal [15] proposed a 10-transistor based
XOR-XNOR circuit. A higher delay was resolved in their design by using The second module (SUM circuit) of FA is implemented using the
the CPL and restorer circuit, as presented in Fig. 2(c). Furthermore, to input carry signal and the intermediate signals (XOR and XNOR), as
improve the performance of the XOR-XNOR circuit, an independent shown in the equation below. The essential feature of this unit is to
generation of XOR and XNOR designs was done. The method of provide adequate driving power to the subsequent modules.
XOR-XNOR is realized with 10-transistors, as depicted in Fig. 3.
The proposed XOR-XNOR design is realized using the CPL logic with SUM = X⊕CIN = XOR.CIN’+XNOR.CIN (1)
one static inverter. In the proposed circuit, XOR and XNOR output are
Module II (SUM circuit) uses two transmission gates (TG), where the
independently realized. Two PMOS (P2 & P3) and two NMOS (N2 & N3)
P7 & N7 transistor gate is connected with XNOR and XOR signal
are used in the XOR design. Similarly, two NMOS (N4 & N5) and two
generated from the first module. Source and Drain nodes of these tran­
PMOS (P4 & P5) are used in the XNOR design. At the XOR design,
sistors (P7 & N7) are associated with CIN′ and the SUM output,

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respectively. On the other hand, the second TG gate (P8 & N8) is gated
with XOR and XNOR signals. Source and Drain nodes of these P8 & N8
transistors are connected through input carry signal (CIN) and SUM,
respectively.

3.2. Module III

In the proposed FA circuit, the third module is the carry module

(COUT). This module is realized with the TG logic and MUX circuits.
When the A = B, then the COUT =B; if not, COUT=CIN.

3.3. Full adder cell

A new one-bit FA circuit was realized using 20-transistors, as pre­

sented in Fig. 6. The proposed adder is implemented using the XOR-
XNOR circuit, SUM module, and CARRY module, respectively, as
depicted in Figs. 3–5. These three modules are interconnected with each
Fig. 5. Module III (COUT).
other (Fig. 1(c)). In this circuit, the SUM module is implemented using
two TG gates. The P7, P8, N7, and N8 transistors are gated with the first
module’s XNOR and XOR signals. When XOR is on logic "1" (XNOR is at 4. Comparative study of the proposed design
logic "0"), then both the P7 and N7 transistors turn "ON," and SUM
output is directly linked to the inverted input carry signal (CIN′ ). When In this section, comparison results of different designs of XOR-XNOR
CIN is in logic "0," then CIN′ will be on logic "1," and this logic pass and FA are discussed. The results are shown in the upcoming subsection
through the transistor P7 and N7 to the output. On the other hand, when for the performance metrics.
XOR gets logic "0" and XNOR is at logic "1," then both P8 and N8 tran­
sistors turn "ON," and SUM output is connected to the input carry signal 4.1. Simulation setup
(CIN).
In the proposed FA circuit, the CARRY module is implemented using All the proposed circuits have been tested in Cadence software using
TG and MUX. When XOR gets logic "0" at that time, XNOR signal attain 90 nm CMOS GPDK process technology for the transient analysis in the
logic "1", then both the P9 & N9 transistors turn "ON," and they pass the present work. A 1.2V power supply carries out all the simulations. For
value of B and A to the output node (COUT). In another case, when the simulating the circuit in the physical environment, two inverters are
XOR node is at the logic "1," then XNOR is at the logic "0" at the same used at the input of the test circuit. The size of these inverters is selected
time the P10 and N10 transistors turn "ON" and pass the input carry so that there is enough distortion in the real environment, and the
signal (CIN) to the output node. minimum output load of four inverters is used to evaluate the perfor­
Fig. 6 shows the schematic and layout of 1-bit FA designs. The pro­ mance [7]. The generic testbed is presented in Fig. 7 for the simulation
posed FA design uses fewer intermediate nodes than Aguirre’s [9] and of different types of circuits.
Kumar’s [12] structure; therefore, it reduces the switching power Fig. 8 presents the transient analysis of the XOR-XNOR and proposed
component. Furthermore, for high performance, the proposed FA design FA circuit by utilizing the test bench (Fig. 7).
uses independent XOR-XNOR design as module I. In the next section, the
performance of the proposed FA circuit through different simulation 4.2. Simulation results
conditions is investigated.
1) XOR-XNOR Circuit: To check the functionality of the XOR-XNOR
circuit, a piecewise linear (pwl) input signal (A & B) is used. Fig. 8
(a) shows the applied input pattern and corresponding XOR-XNOR
outputs. Table 1 compares the result of the proposed design with
the prior art in terms of worst-case delay, power consumption, and
power delay product (PDP). For the calculation of PDP, the worst-
case delay of XOR/XNOR output is taken. The XOR-XNOR circuit,
presented in Ref. [4], uses the least number of transistors. However,
it has a higher worst-case delay. The proposed XOR-XNOR circuit has
the smaller worst-case delay among all the circuits.
2) FA design: An input wave pattern is shown in Fig. 8(b), in which
three inputs A, B, and C are applied to the inputs of the proposed FA
through the test bench, and SUM and COUT are the output of the
signal. Table 2 represents the simulation result of FA structure
comparing the result of different types of the adder in terms of delay
(input carry to carry output), power consumption, and PDP. By
optimizing transistors’ size, there is a significant reduction in delay
without much increase in power consumption. In addition, minimum
PDP is also achieved by optimization. The following section dis­
played the performance of the FA circuit.

The worst-case delay of carrying signal in different FA designs is

shown in Table 2. It is apparent from the table that the proposed FA
Fig. 4. Module II (SUM). design gives the lowest delay among all reviewed circuits. The proposed

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J. Kandpal et al. Microelectronics Journal 115 (2021) 105205

Fig. 6. (a). Proposed 1-bit hybrid Full adder, and (b). Layout of FA.

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J. Kandpal et al. Microelectronics Journal 115 (2021) 105205

Table 1
Performance of different XOR-XNOR cells in 90 nm CMOS technology at 1.2V
supply voltage.
Design No of Propagation Power PDP
Transistor Delay(ps) Consumption (aJ)
(uW)
XOR XNOR

Radhakrishnan 6 106 96.5 10.9 1155.4

[4]
Valashani [13] 10 73.7 52.2 10.7 788.59
Kandpal [15] 10 48.3 49.4 8.89 439.16
Proposed Design 10 47.3 48.4 8.52 412.36
Fig. 7. Test bench.

fewer transistors. Therefore, the proposed FA design consumes moderate

design offers a 13.01–54.93% improvement in delay when compared to
power when compared to its best counterparts.
existing structures.
Power delay product is a quantitative measure of efficiency, which
From the comparison done in Table 2, it is apparent that Valashani’s
provides 13.01–59.20% improvement in the proposed design compared
design [13] consumed minimal power in their proposed design due to

Fig. 8. Time-domain simulation result (waveform) of (a). XOR-XNOR and (b). Proposed FA circuit.

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J. Kandpal et al. Microelectronics Journal 115 (2021) 105205

Table 2
Performance of different FA cells in 90 nm CMOS technology at 1.2V supply
voltage.
Design No of Propagation Power PDP (aJ)
Transistor Delay(ps) Consumption
(uW)

Aguirre_1 [9] 28 80.1 28.5 2282.85

Aguirre_2 [9] 28 69.2 29.5 2041.40
Kumar [12] 27 68.1 26.7 1818.27
Valashani [13] 18 71.3 25 1782.50
Kandpal [15] 20 41.5 25.8 1070.70
Proposed 20 36.1 25.8 931.38
Design

to the reviewed circuits.

The robustness of the proposed FA circuit is tested by altering the
supply voltage from 0.6V to 1.5V and compared with the existing ar­
chitecture as described in Fig. 9. The performance of various FA circuits
is compared in terms of delay, power, and PDP, as shown in Fig. 9 (a to
c).
In Fig. 9(a), the proposed FA design is compared with the reviewed
FA circuits based on their delay, and it is found that the proposed FA cell
exhibited the best performance amongst available FA cells.
At varying power supply, power consumption of different FA cells is
tested and displayed in Fig. 9(b). Valashani’s design [13] consumes the
lowest power amongst all the other circuits. Moreover, the PDP of the
proposed FA design showed the best results for different supply voltages,
as shown in Fig. 9(c).

4.3. Process corner analysis

The performance of the proposed FA cell is also evaluated in varying

process corners viz. Slow-slow (SS), slow-fast (SF), nominal-nominal
(NN), fast-slow (FS), and fast-fast (FF). Fig. 10 (a, b & c) shows the
performance evaluation of available FA at different process corners. It is
observed that the proposed design operates properly when it is simu­
lated in different process corner conditions and shows the best results in
terms of Delay and PDP.
From Fig. 10(a and b), it is observed that the delay and power con­
sumption are highest on SS and FF corners and lowest on FF and SS
process corners, respectively, in the proposed FA design.
Fig. 10(c) showed minimum PDP in FF and maximum PDP in SS
corner, respectively.

5. Conclusion

The present study mainly focuses on the circuit design level,

choosing a proper logic style for implementing the FA circuit. A hybrid
style gives liberty to VLSI designers to select different modules to
implement the circuit as per their prerequisites. In the present work, a
new design of a 1-bit FA is presented on the hybrid design scheme using
the 20-transistors. The proposed method alleviates the threshold voltage
problem and enhances the driving capability. A comprehensive com­
parison is conducted in the Cadence virtuoso tool at 90 nm technology.
The present study reported 13.01–54.93% and 13.01–59.20%
improvement in delay and PDP, respectively, compared to the best
counterpart circuits. The performance is also tested at different supply
voltage and process corner conditions. From the results, it is revealed
that the proposed design is highly robust in all states. Therefore, the
proposed method is suitable for high-performance VLSI applications.

Author statement

Jyoti Kandpal: Conceptualization; Methodology; Investigation; Fig. 9. (a). Delay (COUT) (b) Power (c) PDP results under varying sup­
Formal analysis; Writing – original draft. Abhishek Tomar: Conceptu­ ply voltage.
alization; Supervision; Validation; Writing – review & editing. Mayur

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J. Kandpal et al. Microelectronics Journal 115 (2021) 105205

Agarwal: Methodology; Supervision; Writing – review & editing.

Declaration of competing interest

The authors declare that they have no known competing financial

interests or personal relationships that could have appeared to influence
the work reported in this manuscript.
No conflict of interest exits in the submission of this manuscript.

Acknowledgment

This work is supported by a fellowship from the Ministry of Human

Resource and Development, Government of India, through the Technical
Education Quality Improvement Programme-III (TEQIP-III), India.

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