386 IEEE ELECTRON DEVICE LETTERS, VOL. 23, NO.

7, JULY 2002

Why is Nonvolatile Ferroelectric Memory

Field-Effect Transistor Still Elusive?
T. P. Ma, Fellow, IEEE, and Jin-Ping Han, Student Member, IEEE

Abstract—In principle, a memory field-effect transistor (FET)

based on the metal–ferroelectric–semiconductor gate stack
could be the building block of an ideal memory technology that
offers random access, high speed, low power, high density and
nonvolatility. In practice, however, so far none of the reported
ferroelectric memory transistors has achieved a memory retention
time of more than a few days, a far cry from the ten-year retention
requirement for a nonvolatile memory device. This work will
examine two major causes of the short retention (assuming
no significant mobile ionic charge motion in the ferroelectric
film): 1) depolarization field and 2) finite gate leakage current. Fig. 1. Schematic MFM structure where the ferroelectric layer is polarized
A possible solution to the memory retention problem will be and a compensating charge is present on each electrode. Provided that there is
suggested, which involves the growth of single-crystal, single complete charge compensation, there should be no depolarization field.
domain ferroelectric on Si. The use of the ferroelectric memory
transistor as a capacitor-less DRAM cell will also be proposed.
Index Terms—Depolarization field, ferroelectrics, FET, leakage
current, retention, nonvolatile memory.

I. INTRODUCTION

I N theory, the ferroelectric memory field-effect transistor

(FEMFET) technology [1] has many desirable features,
including small cell size, low-voltage operation, fast program-
ming/erase speed and nonvolatility, making it an attractive
alternative to flash and other existing nonvolatile semiconductor Fig. 2. Gate stack of the FEMFET transistor is modeled by a ferroelectric
memory technologies. Compared to the existing 1-transistor capacitance (C ) in series with the semiconductor capacitance C , where C
1-capacitor or 1-transistor 2-capacitor ferroelectric memory may be generalized to represent the series combination of an insulating buffer
on top of the semiconductor. A gate voltage V induces a polarization P and a
voltage V across C .
technology [2], the FEMFET approach has the advantage that
its read operation is nondestructive, in addition to having a
smaller cell size.
However, so far no one has demonstrated truly nonvolatile II. DEPOLARIZATION FIELD
FEMFET technology, despite the numerous attempts by many First, let us examine the depolarization field. Fig. 1 shows a
researchers. In recent years, considerable progress has been schematic sketch of a metal-ferroelectric-metal (MFM) struc-
made by leading research groups such as that of Ishiwara [3], ture where the ferroelectric layer is polarized and a compen-
but the state-of-the-art FEMFET typically exhibits a retention sating charge is present on each electrode. Provided that there is
time of a few hours and even the very best FEMFET has not complete charge compensation, then there should be no depolar-
exceeded a few days of memory retention. We attribute the ization field. On the other hand, for the gate stack of a FEMFET,
relatively short memory retention time to two major causes: it can be shown that a depolarization field always exists due to
1) depolarization field [4] and 2) gate leakage current [5]. We the finite dielectric constant of the semiconductor, as presented
have assumed that a high-quality ferroelectric film is used in the following.
such that there is no mobile ionic charge. This paper is our As shown in Fig. 2, the gate stack of the FEMFET transistor
attempt to show why it is extremely difficult for the FEMFET (to be called the FEM gate) is modeled by a ferroelectric capac-
to achieve the ten-year retention time that is required for a itance ( ) in series with the semiconductor capacitance, ,
viable nonvolatile semiconductor memory technology. where may be generalized to represent the series combina-
tion of an insulating buffer on top of the semiconductor. A gate
Manuscript received January 25, 2002; revised April 14, 2002. The review of voltage induces a polarization and a voltage, , across
this letter was arranged by Editor S. Kawamura. the ferroelectric such that
The authors are with the Center for Microelectronic Materials and Structures
and Department of Electrical Engineering, Yale University, New Haven, CT
06520-8284 USA (e-mail: [email protected]).
Publisher Item Identifier S 0741-3106(02)05349-1.
(1)

0741-3106/02$17.00 © 2002 IEEE

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MA AND HAN: WHY IS NONVOLATILE FEMFET STILL ELUSIVE? 387

The expected retention time for a device that has a remnant

polarization , leakage current and a trapping probability of
, may be estimated to be

(5)

assuming that each trapped electron diminishes the effect of an

equal amount of polarization charge.
Let us now assume a remnant polarization of C/cm
and a gate leakage current of A/cm , both are not
a typical values. Then the retention time would depend strongly
on the trapping probability. For the highest possible trapping
probability of 1 (i.e., every injected electron is trapped in
Fig. 3. (a) FEM gate stack has just been programmed such that the ferroelectric the dielectric stack), one would estimate a short retention time
polarization induces an inversion layer in the p-type semiconductor. The
FEMFET is in its “on” state and the electric field distribution favors electron of seconds. On the other hand, for the very low trap-
injection toward the ferroelectric/buffer interface where some electrons are ping probability of (i.e., only 1 electron is trapped
trapped in the dielectric stack and (b) sufficient electron trapping has taken for every 10 injected electrons), one would estimate a relatively
place that results in diminished polarization effect and the semiconductor is no
longer inverted. The FEMFET is in its “off” state. long retention time of days. Typically, the trapping prob-
ability falls in between these two extreme values.
Of course the assumption of a constant leakage current is an
When goes to 0, one has oversimplification, as the current is expected to drop as the ef-
fective field reduces with trapping. For that matter, (5) itself
is also an oversimplification. However, we feel that these sim-
(2) plifications are justified for our purpose, which is to get very
rough estimates of the possible retention times in the presence
which reduces to of leakage currents.
From the previous, one might suggest the use of thick buffer
(3) layers at both interfaces to reduce the leakage current. However,
this will increase the depolarization field, according to (4), as
mentioned earlier (because is decreased), which tends to
leading to a depolarization field
reduce the retention time. In addition, this will also increase the
operating voltage, which decreases the competitiveness of this
technology.
(4) To estimate the required operating voltage for a FEMFET
cell that has sufficiently low leakage current to retain the data
where is the dielectric constant of the ferroelectric film. for ten years, we may refer to the state-of-the-art flash memory
Equation (4) indicates that, for as long as is not infinity, technology where data retention is only limited by the leakage
there is always a finite depolarization field. This depolarization current, where it is well known that the tunnel oxide thickness
field is in the direction of reducing the polarization in the ferro- must be thicker than 7 nm to ensure low enough leakage current
electric and tends to reduce the memory retention time. Equa- to realize a ten-year retention time [6]. Assuming a 7-nm SiO
tion (4) also suggests the use of a larger ratio in order buffer layer on either side of the ferroelectric in the FEMSET
to get a smaller depolarization field. gate stack, a coercive field of 100 kV/cm, a dielectric constant
of 200 for the ferroelectric, then one would need a program-
ming/erase voltage of at least 14 V if the ferroelectric field
III. LEAKAGE CURRENT AND TRAPPING
during programming/erase is required to be at least twice that
Another major cause of the reduced retention time is the gate of the coercive field. Such a large programming/erase voltage
leakage current and trapping of carriers in the gate dielectric is not competitive against many other emerging semiconductor
stack. Fig. 3(a) illustrates the situation where the FEM gate memory technologies.
stack has just been programmed such that the ferroelectric polar- Perhaps theoretically, based on the tunneling current alone,
ization induces an inversion layer in the p-type semiconductor. one might be able to scale down the SiO buffer layers to
Therefore the FEMFET is in its “on” state. Note that an insu- 5 nm on each side, which would then reduce the program/erase
lating buffer layer between the ferroelectric and the semicon- voltage to 10 V. But experimentally the viability of a tunnel
ductor (i.e., a buffer layer) is included for generality. This fer- oxide thinner than 7 nm has not been successfully demonstrated
roelectric polarization, however, attracts electron injection from for nonvolatile floating-gate memory technology, because of
both the gate electrode and the semiconductor side. This elec- excess leakage currents originating from nontunneling mecha-
tron injection is followed by trapping in the gate dielectric stack, nisms in the low-field region, especially after electrical stress.
leading to local charge compensation and gradually diminished There is no good reason to believe that the ferroelectric FET
effect of polarization. will be better off in this regard.

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388 IEEE ELECTRON DEVICE LETTERS, VOL. 23, NO. 7, JULY 2002

The use of high-k buffer layers is in the right direction, but so V. SUMMARY
far in the literature no high-k dielectrics have shown sufficiently In summary, the two major causes for the short retention time
low leakage currents ( 10 A/cm at the operating field) to of FEMFET memory have been identified as being due to 1) the
be a serious contender.
depolarization field and 2) the gate leakage current and trap-
ping in the gate stack. Both are very difficult to eliminate and
contribute to the failure to realize an adequate retention time
IV. A POSSIBLE SOLUTION
needed for a nonvolatile memory technology. A possible solu-
A viable solution must be able to minimize the effects of both tion has been suggested, which involves the growth of single
the depolarization field and the gate leakage current. The former crystal, single domain ferroelectric on Si. A possible applica-
may be circumvented by having a “square” P-E hysteresis curve, tion of the current FEMFET technology with its finite retention
because, if this can be achieved, any depolarization field will not time, the FEDRAM, has been introduced.
affect the remnant polarization unless it exceeds the coercive
field. The latter may be accomplished by having no trapping in REFERENCES
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