MS LOGIC GATES
MS LOGIC GATES
Boolean Logical
SPECIMEN A 2023
B X
1(b) 4
A B C X
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
3(a) One mark for each correct gate, with the correct input(s) as shown. 4
Boolean Logical
A B C Z
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 0
Boolean Logical
JUNE 2023 V2
Question Answer Marks
A B C X
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 0
Boolean Logical
JUNE 2023 V3
5(a) One mark for each correct gate, with the correct input(s) as shown. 4
Boolean Logical
A B C Z
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 0
MARCH 2023
6(a) One mark for each correct gate, with the correct input(s) as shown. 5
6(b) 4
A B C X
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 0
4 marks for 8 correct outputs
3 marks for 6/7 correct outputs
2 marks for 4/5 correct outputs
1 mark for 2/3 correct outputs
Boolean Logical
WORKBOOK EXERCISES
1 a OR gate
b NAND gate
c XOR gate
2 A B C Working area X
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 1
4 a A B Working area X
0 0 0
0 1 1
1 0 1
1 1 1
b OR gate
Boolean Logical
5 a A B C Working area X
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
b As the output X exactly matches input C, the entire logic circuit could be removed and
the output connected directly to the input C.
6 a A B C Working area X
0 0 0 1
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 1
b AND gate
7 a (A AND NOT B) AND (B OR C)
or
(A. ).(B + C)
b
Boolean Logical
c T A P Working area X
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
9 a
Boolean Logical
b A B C Working area X
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
c X Y Z Working area Q
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
A B C Working area X
0 0 0 1
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1
12 a
b A B C Working area X
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1