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FPGA 1

The document describes two experiments involving the design and implementation of Verilog code for counters on an FPGA board using Vivado Xilinx software. The first experiment utilizes a state machine to increment a counter every second, while the second experiment employs an IP catalog for the same purpose. In both cases, the LED output reflects the counter's state as observed on the FPGA board.

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k.k.mishra1881
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3 views

FPGA 1

The document describes two experiments involving the design and implementation of Verilog code for counters on an FPGA board using Vivado Xilinx software. The first experiment utilizes a state machine to increment a counter every second, while the second experiment employs an IP catalog for the same purpose. In both cases, the LED output reflects the counter's state as observed on the FPGA board.

Uploaded by

k.k.mishra1881
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Experiment:04 Date:20/01/24

State Machine
Aim: To design and implement verilog code on FPGA for a counter that
increments every 1 second using state machine.
Equipment: Software – Vivado Xilinx
FPGA board – ARTY A7 100T
Code:
module sm(
input clk,rst, //initializing main clock and reset signal
output reg [3:0] led); //4bit led output register
reg [25:0] count; //counter with clock division
reg clk_1s; // 1Hz clock signal for LED toggling
reg [2:0] state; //3bit state reg
always @ (posedge clk or negedge rst) begin // Sensitive to main clock
rising edge and reset falling edge
if (~rst) begin // Active-low reset condition
count<=26’d0; // Reset counter
clk_1s<=1’b0; // Reset 1-second clock
end else begin
if(count==26’d49999999) begin // Toggles 1-second clock
clk_1s<=~clk_1s; // Toggle 1-second clock
count<=26’d0; // Reset counter
end else begin
count=count+1; // Increment counter
end
end
end
//state machine for control of led
always @ (posedge clk_1s or negedge rst) begin // Sensitive to 1-
second clock and reset
if(~rst) begin // Active-low reset condition
state<=3’b000; //state is reset
end else begin
case (state)
3’b000: state<=3’b001;
3’b001: state<=3’b010;
3’b010: state<=3’b011;
3’b011: state<=3’b100;
3’b100: state<=3’b000;
endcase
end
end
always @ (posedge clk_1s or negedge rst) begin // Sensitive to 1-second
clock and reset
if(~rst) begin // Active-low reset condition
led<=4’b0000; //leds are reset
end else begin
case (state)
3’b000: led<=4’b0000;
3’b001: led<=4’b0001;
3’b010: led<=4’b0101;
3’b011: led<=4’b1001;
3’b100: led<=4’b1011;
endcase
end
end
endmodule

Pin Constraints:

Conclusion:It was observed that when the code is implemented on FPGA


board, LED glows in accordance with the pattern generated by the state
machine.
Experiment:05 Date:23/01/25
Counter using IP Catalog
Aim: To design and implement verilog code on FPGA for a counter using IP
catalog.
Equipment: Software – Vivado Xilinx
FPGA board – ARTY A7 100T
Code:ule IP(
input clk,rst, //initializing main clock and reset signal
output wire [3:0] led); //4bit led output register
reg [25:0] count; //counter with clock division
reg clk_1s; // 1Hz clock signal for LED toggling
always @ (posedge clk or negedge rst) begin // Sensitive to main clock
rising edge and reset falling edge
if (~rst) begin // Active-low reset condition
count<=26’d0; // Reset counter
clk_1s<=1’b0; // Reset 1-second clock
end else begin
if(count==26’d49999999) begin // Toggles 1-second clock
clk_1s<=~clk_1s; // Toggle 1-second clock
count<=26’d0; // Reset counter
end else begin
count=count+1; // Increment counter
end
end
end
counter_ip uut (.CLK(clk_1s),.Q(led));
endmodule

IP catalog generated code(VHDL):

Pin Constraints:

Conclusion:It was observed that when the code is implemented on FPGA


board, LED glows in accordance with the applied clock depicting the value of
incrementing counter.

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