Received: 1 November 2022 Revised: 23 May 2023 Accepted: 19 June 2023 IET Renewable Power Generation

DOI: 10.1049/rpg2.12787

ORIGINAL RESEARCH

Implementation and reliability analysis of a new non-isolated

quadratic buck–boost converter using improved Markov modelling

Ifham H. Malick1 Mohammad Zaid1 Javed Ahmad2 Kazem Varesi3

Chang-Hua Lin2

1
Department of Electrical Engineering, Aligarh Abstract
Muslim University, Aligarh, India
Here, a new buck–boost converter with reliability analysis is proposed. The converter has
2
Department of Electrical Engineering, National utilized a new voltage multiplier cell at the input side to boost the output voltage. It has
Taiwan University of Science and Technology,
Taipei, Taiwan
a continuous input current with a wide range of duty cycle operations. The converter
3
achieves unity gain at 26.8% duty cycle and can also operate in continuous and discon-
Department of Power Engineering, Faculty of
Electrical Engineering, Sahand University of tinuous conduction modes in buck and boost modes. The detailed reliability analysis of the
Technology, Tabriz, Iran proposed converter using improved Markov modelling is also presented by considering
both open circuit and short circuit faults across the semiconductor devices. The variation
Correspondence of reliability and the mean time to failure (MTTF) with different converter parameters like
Kazem Varesi, Sahand University of Technology,
Tabriz, Iran.
the duty cycle and the input voltage is also discussed here. The hardware results of the
Email: [email protected] developed prototype converter are also presented here at varying duty ratios. The power
loss analysis and comparison of the converter with other newly proposed buck–boost
topologies show the advantages of the proposed converter. For checking the stability of
the converter, the state space model of the converter is also discussed in detail of the
proposed converter.

1 INTRODUCTION of heat. These stresses play a significant role in degrading and

reducing the useful life of a device by making it more prone
With the increase in population and changing environmental to failure and thereby causing an earlier replacement of the
and climatic conditions, the need for reliable and eco-friendly component(s) being used in the converter. In literature, various
alternative green energy sources like solar photovoltaic (PV) sys- methods for the estimation of reliability are provided, however,
tems, wind energy systems, and fuel cells is the call of the day. the bathtub model [7] depicted in Figure 1 is the most accept-
The power generated by these sources is often at a lower voltage able model for calculating the failure rates of the electronic
as compared to the grid operating voltage hence DC–DC con- devices used in various applications. The bathtub curve con-
verters [1] are employed to step up or step down the voltages at sists of three intermittent regions over which the component’s
the grid operating level and at a specified bus voltage to meet the life depends over a course of time. The regions are namely,
need of the load voltage respectively. The DC voltage is available infant mortality, constant failure rate, and wear-out period. Dur-
after rectification it needs to be boosted up to be used for var- ing the infant period, the device’s failure rate is abnormally
ious practical applications like solar PV system applications [2, high and hence the reliability is low. Generally, it is due to
3], switch-mode power supplies (SMPS), electric vehicles, and poor installation, design, or misapplication. For normal oper-
fuel-cell applications [3–5]. ation and analysis purposes, the device is assumed in a constant
Apart from the above-mentioned issues, the DC–DC con- failure rate. After a specified useful life of the device, when
verters are also exposed to a variety of stresses ranging from it bears various electrical and thermal stresses, the device is
electrical stresses [6] like voltage and current stresses across in its wear-out period and the failure rate increases as time
the semiconductor elements to thermal stresses in the form progress [7, 8].

This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is
properly cited.
© 2023 The Authors. IET Renewable Power Generation published by John Wiley & Sons Ltd on behalf of The Institution of Engineering and Technology.

IET Renew. Power Gener. 2023;17:2733–2749. wileyonlinelibrary.com/iet-rpg 2733

 17521424, 2023, 11, Downloaded from https://ietresearch.onlinelibrary.wiley.com/doi/10.1049/rpg2.12787, Wiley Online Library on [29/11/2024]. See the Terms and Conditions (https://onlinelibrary.wiley.com/terms-and-conditions) on Wiley Online Library for rules of use; OA articles are governed by the applicable Creative Commons License
2734 MALICK ET AL.

∙ The converter is non-isolated, hence there is no presence of

coupled inductor(s) or transformer which causes no prob-
lem related to leakage inductance and also helps to make to
converter less bulky and highly reliable.
∙ The topology has continuous input current, making it feasible
for renewable and DC micro-grid applications.
∙ The proposed converter operates in the derated state, even
when multiple semiconductor and/or passive elements expe-
rience OC or SC faults. An extensive study of the converter’s
reliability at different faults is also considered in this work.

The paper is divided into five sections and it discusses the

structure and the steady-state analysis of the proposed buck–
FIGURE 1 Bath-tub model curve for reliability analysis [7]. boost converter topology in Section 2. Section 3 consists of
the small signal modelling followed by the controller design and
the suitable bode plots. An extensive comparison of the pro-
In [9–11], an extensive study of reliability is done for vari- posed converter topology is also presented with various similar
ous conventional isolated converters, imparting a clear idea of converters taking into account various parameters in Section
the reliability and performance of the converters over time. The 4. Section 5 presents a detailed reliability analysis of the con-
authors in [10] have claimed that the reliability of the converter verter and the effect of various converter parameters on the
reduces drastically as the converter is operated at higher duty converter’s reliability using improved Markov modelling.
ratios. In [11], the reliability analysis of interleaved converters
is evaluated emphasizing, that the switch(s) take the lion’s share
of degrading the reliability of the converter. The reliability of 2 STEADY-STATE ANALYSIS OF THE
multi-phase DC–DC converters for photovoltaic systems is dis- PROPOSED BUCK–BOOST CONVERTER
cussed in [12]. The effect of adding more parallel stages on total TOPOLOGY
system reliability, its effect is analysed on the failure rates of the
components. The proposed topology as shown in Figure 2, is a quadratic
Various authors have proposed converters both, inverting [2, buck–boost converter consisting of an input DC voltage
13–18] and non-inverting [19–24] type buck–boost converters source (Vin ), two switches (S1 and S2 ), three inductors
in literature. A Cuk converter-based topology in [13] produces (L1 , L2 and L3 ), three capacitors (C0 , C1 and C2 ), four diodes
a higher gain in boost operation as compared to the conven- (D0 , D1 , D2 and D3 ) and a load resistor (R0 ). The proposed
tional Cuk converter however the converter lacked a common topology consists of an input VMC which comprises the com-
ground. Though the buck–boost converter suffers from higher ponents L1 , L2 , D1 , D2 and C1 . For proper operation of the
switch stress [14, 15], the converter in [16] produces low switch- converter, the VMC inductors L1 and L2 must be identical,
ing stress. The converter however suffered from discontinuous otherwise, sudden current changes will be observed across the
input current which inhibits its operation for renewable energy inductors. At first mode, both the inductors are paralleled (with
applications. C1 and Vin ) and both are charged. If L1 and L2 are not identi-
The literature hence contains ample boost, buck–boost, and cal their currents at the end of the mode 1 will be different. At
multilevel converters, but they lack the reliability analysis, and mode two, both inductors will be in series, where their currents
hence it is difficult to define its working stability and the con- must be the same, but is not. All the components are consid-
verter’s operational characteristics over time. Regardless of the ered to be ideal. The converter’s operation is also discussed in
high efficiency, continuous input current, and low voltage and continuous conduction mode (CCM) and discontinuous con-
current stresses across the elements, a converter is bound to duction mode (DCM) modes with various suitable equations
work for a longer amount of time with a minimum mean time and graphical figures.
to failure (MTTF).
This paper hence follows the implementation of a new non-
isolated quadratic gain buck–boost converter along with the 2.1 Operating principle of the proposed
suitable reliability analysis. The attractive advantages of the converter in continuous conduction mode
proposed topology are listed below:
2.1.1 Mode 1 (Both switches ON)
∙ The converter achieves a unity gain at 26.8% duty cycle and
four times the gain as compared to the conventional buck– The diodes D1 and D2 conducts when the switches are in the
boost converter at 50% duty ratio; ON state. The inductors L1 and L2 , and capacitor C1 get
∙ The converter employs two switches which help to increase charged through the supply voltage Vin until they reach the
the system’s reliability as partial power can be fed if either equivalent voltage equal to the supply voltage. The capacitor C2
switch experiences a fault; charges the inductor L3 , and energy transfer takes place from
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MALICK ET AL. 2735

FIGURE 2 Proposed topology of quadratic gain buck–boost converter.

FIGURE 3 (a) Proposed topology of buck–boost DC–DC converter in ON-state node. (b) Proposed topology of buck–boost DC–DC converter in OFF-state
mode.

capacitor C0 to the load R0 as shown in Figure 3a. The voltage The ideal voltage gain of the proposed topology can be cal-
and current equations of the converter in mode 1 are given as: culated by applying the volt-sec balance principle across the
inductors in CCM operation.
⎧V =V = V
⎪ L1 L2 in
⎛ DT T
⎞
⎪ VL3 = VC 2 1 ⎜
⎨ (1) VL ON dt + VL OFF dt ⎟ = 0 (5)
⎪ VC 1 = Vin T ⎜∫ ∫ ⎟
⎝0 DT ⎠
⎪ VC 0 = V0
⎩

⎧ IC 1 = Iin − 2IL1 ⎧ ( DT T ( ) )
⎪ ⎪1 2Vin − VC 2
∫ Vin dt + ∫ dt = 0
⎨ IC 2 = IL3 (2) ⎪T 2
⎪ ⎨ 0 DT (6)
⎩ IC 0 = I0 ⎪ 2Vin
⎪ VC 2 =
(1 − D )
⎩
2.1.2 Mode 2 (Both switches OFF)
⎧ ( DT T
)
The diodes D0 and D3 conducts when the switches are in the ⎪1
⎪T ∫ VC 2 dt + ∫ (V0 ) dt = 0
OFF state. The VMC charges the capacitor C2 . The inductors
⎨ 0 DT (7)
meanwhile transfer the stored energy to the load R0 as shown in ⎪ − (1 − D ) V0
Figure 3b. The voltage and current equations of the converter ⎪ VC 2 =
⎩ D
in mode 2 are given as:
{ Applying the volt-sec principle across the inductor L1 in (6)
Vin + VC 1 − VC 2 2Vin − VC 2
VL1 = VL2 = = and L3 in (7) we get:
2 2 (3)
VL3 = − VC 0 = −V0 Using Equations (6) and (7) we can obtain the voltage
conversion factor as:
{
IC1 = IC2 = IL1
(4) V0 −2D
MCCM = = (8)
IC 0 = I0 − IL3 Vin ( 1 − D )2
 17521424, 2023, 11, Downloaded from https://ietresearch.onlinelibrary.wiley.com/doi/10.1049/rpg2.12787, Wiley Online Library on [29/11/2024]. See the Terms and Conditions (https://onlinelibrary.wiley.com/terms-and-conditions) on Wiley Online Library for rules of use; OA articles are governed by the applicable Creative Commons License
2736 MALICK ET AL.

FIGURE 7 Typical waveforms of the proposed converter in

FIGURE 4 Typical waveforms of the proposed converter in continuous discontinuous conduction mode (DCM).
conduction mode (CCM) operation.

as:
⎧ 2Vin (1 − D ) VO
⎪ VS 1 = =
(1 − D ) D
⎪
⎪ 2Vin VO
⎪ VS 2 = =
⎪ ( 1 − D )2 D
⎪ V ( 1 − D ) VO
⎨ VD1 = VD2 = (1 − D ) =
in
2D
(9)
⎪
⎪ 2Vin ( 1 − D VO
)
⎪ VD3 = =
(1 − D ) D
⎪
⎪ 2DVin
⎪ VDO = = VO
⎩ ( 1 − D )2

⎧ 2
⎪ V = V = (1 − D ) VO
FIGURE 5 Switching voltage stress of the proposed converter in CCM. ⎪ C1 in
2D
⎪
⎨V = 2Vin ( 1 − D ) VO (10)
⎪ C2 =
(1 − D ) D
⎪
⎪ VC O = VO
⎩
The average currents through the switches and inductors can
be easily determined by applying the amp-sec balance principle
in the capacitors.
( DT T
)
1
∫ IC ON dt + ∫ IC OFF dt = 0 (11)
T 0 DT

The average through various components as shown in

Figure 4 is given as:
⎧ 2DIO
FIGURE 6 Boundary normalized inductor time constant vs duty cycle ⎪ IS1avg = 2
(D). ⎪ ( 1 − D)
⎪ IO
⎪ IS2avg =
⎪ ( 1 − D)
⎪ )2
⎪ IL1 = IL2 = 1 − D IO
where D denotes the duty cycle for the switch S . From (8) it can (
be observed that an inverted output buck boost voltage can be ⎪ 2 (1 + D )
obtained from the converter. ⎪ IO
⎨ IL3 = (12)
⎪ (1 − D )
⎪ Iin
⎪ ID1avg = ID2avg = (1 + D )
2.2 Voltage and current across various ⎪
passive elements of the proposed converter ⎪ (1 + D ) Iin
⎪ ID3avg =
⎪ 2D
The peak voltage stress across the switches shown in Figures 4 ⎪ IO
⎪ IDOavg =
and 5, and the average voltage across the capacitors is evaluated ⎩ (1 − D )
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MALICK ET AL. 2737

2.3 Design of inductors and capacitors of (1–β) and ends at a time equal to the period (T) as depicted
the proposed converter in Figure 7.

The ripple current and critical values of the inductors can be The maximum current through the inductor in DCM and the
found as: average current through the output diode is given as:

⎧ V ⎧ V0 (𝛽 − D ) T
⎪ Δ iL1 = Δ iL2 = in DT ⎪ IL3 max =
⎪ L1 ⎨ L3 (17)
⎨ (1 − D )2 V0
(13) ⎪ IDO avg = (𝛽 − D ) IL3 max
⎪L =L D Vin ⎩
= =
⎪ 1Cri 2Cri
ΔiL1 fs 2 ΔiL1 fs
⎩
Applying volt-sec balance across the inductors and using the
⎧Δ i = 2DVin above equation we obtain the DCM gain of the converter as,
⎪ L3
( 1 − D ) L3 f s
⎨ (1 − D ) V0
(14) ⎧
⎪ L3 = ⎪ MDCM =
V0
=
2D
⎩ Cri ΔiL3 fs ⎪ Vin 2
⎪ √ 𝛽 − D)
(
⎨ 𝛽 = D + KDCM (18)
The peak-to-peak ripple voltages across the capacitors can be
given as: ⎪
⎪K L3 2
= = (𝛽 − D )
⎪ DCM R0 T
⎧ ⎩
(1 − D )3 V0
⎪Δ VC 1 =
⎪ 2 (1 + D ) R0C1 fs where k is the normalized inductor time constant. Its varia-
⎪ D V0 tion in boundary conduction mode with duty cycle is shown in
⎨ Δ VC 2 = (15)
⎪ ( 1 − D ) R0C2 fs Figure 6
⎪ D V0
⎪ Δ VC 0 =
⎩ R0C0 fs 2.5 Efficiency and power loss distribution

The efficiency of the converter is determined from both PLECS

2.4 Boundary conduction mode and simulation and experiment. From Figure 9, it is observed that
discontinuous conduction mode operation of the efficiency of the converter increases as the input voltage
the proposed converter is increased. The efficiency gradually decreases as the output
power increases. The converter obtained a maximum efficiency
At the boundary conduction condition, depicted in Figure 6, of 96.8% when the input voltage was 30 V while operating at
the inductor L3 conducts in critical conduction mode. The 12 W power, while an efficiency of 94.5% was obtained when
normalized inductor time constant KBCM is given as: the converter operates at 100 W power with the same input
voltage source. The experimental efficiency of the converter is
⎧ ΔiL3 also plotted with the simulated efficiency. The experimental effi-
⎪ IL3 = ciency of the prototype at 100 W is equal to 93.8% for input
⎪ 2
⎨ (16) voltage of 30 V and 91.4% for input voltage 20 V. Figure 10,
⎪K L 3 (1 − D )2 depicts the percentage contribution of losses by the various
= =
⎪ BCM R0 T 2 elements due to their parasitic resistance; the diodes have the
⎩
maximum contribution of 41% towards the overall losses in the
The proposed converter can also operate in DCM. This converter while capacitors contributed 21% of the total losses.
mode of conduction consists of three different sub-modes of Hence, the diodes and capacitors together contribute to more
operation. than 62% of the total losses. The losses in the converter can
be further minimized by utilizing diodes with lower cut-in volt-
(i) Mode 1: In this mode, both the switches are ON for a duty age and ON-state resistance and choosing capacitors with lesser
cycle D similar to the CCM operation as shown in Figure 7. ESR.
(ii) Mode 2: In this mode, both the switches are OFF and
the inductors starts discharging. The inductor L3 discharge
through the diodes D0 for a duty cycle (β–D) and the mode 3 SMALL SIGNAL MODELLING AND
ends at β. CONTROL OF THE PROPOSED
(iii) Mode 3: In this mode, none of the switches conduct with CONVERTER
the diode D0 ceasing to operate a shown in Figure 8. The
resistor is fed through the output capacitor C0 for this dura- In this section, the small signal modelling of the proposed DC–
tion. The converter operates in this mode for a duration of DC converter is performed. The state variables are inductor
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2738 MALICK ET AL.

FIGURE 8 Proposed Topology of the DC–DC

converter in DCM mode 3.

FIGURE 9 Simulated and experimental efficiency of the converter.

voltage is chosen as the output variable ‘y’. Using space vector

linearization, we get:
{
ẋ = Ax + Bu = Ax + B1 d + B2 vin
(19)
y = Cx + Du

The basic governing equations for the converter in the time

domain and the corresponding signal modelling are represented
as:

⎧ diL1 diL
( vC2
)
⎪L1 = L2 2 = dvin + (1 − d ) vin −
⎪ dt dt 2
FIGURE 10 Losses in the converter across various elements. ⎪ diL3
⎪ L3 = dvC2 + (1 − d ) (−V0 )
⎪ dt
⎪ dvC
⎨ C1 1 = d (2iL1 − iin ) + (1 − d ) iL1 (20)
currents and capacitor voltages (x = [iL1 iL2 iL3 vC1 vC2 vC0 ]T ) ⎪ dt
and ẋ represents the differentiation of ‘x’ with respect to time. ⎪ dvC
They are represented as a sum of a DC term and a small AC ⎪ C2 2 = diL3 + (1 − d ) iL1
⎪ dt
signal. The output voltage and current across the loads are ⎪ dvC ( )
however assumed constant. The duty ratio and input voltage ⎪ CO O = dIO + (1 − d ) I0 − iL3
⎩ dt
are assumed as input variables ‘u’ whereas the output capacitor
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MALICK ET AL. 2739

FIGURE 11 (a) Bode plot for the uncompensated system. (b) Bode plot for the compensated system.

The transfer function of the converter can be obtained using

⎧ d = D + d̂
⎪ the relation mentioned below and then substituting the design
⎪ i = I + iˆ value of the elements as stated in Table 4, in the transfer
⎪ Lj Lj Lj
function.
⎨ (21)
⎪ vC j = VC j + vˆ
Cj vˆ
⎪ C0 −1
= C (sI − A ) B1 + D (22)
⎪ ̂d
⎩ vin = Vin + vˆin
The open loop transfer function as in (22) can be well
Solving the above equations, we can derive the space vector
obtained and is duly plotted in Figure 11a. The gain margin
matrices given below:
(GM) of the uncompensated system being infinite is acceptable,
however the phase margin (PM) of 5.98◦ on the other hand is
⎡ 1−D ⎤
⎢ 0 0 0 0
2L1
0⎥ way too less. The required PM of a system preferably should be
⎢ ⎥ greater than 65◦ so, allow the system with a suitable margin to
⎢ 1−D ⎥
⎢ 0 0 0 0
2L2
0⎥ settle without becoming unstable. The converter needs a com-
⎢ ⎥ pensator with a transfer function (GC ) to improve the PM of
⎢ D ⎥
⎢ 0 0 0 0
L3
0⎥ the system and bring it to suitable values under the guidelines.
A =⎢ ⎥
⎢1 + D ⎥
⎢ C 0 0 0 0 0⎥ 10 (s + 0.01 )
⎢ 1 ⎥ GC = (23)
⎢1 − D D ⎥ (s + 0.001 )
⎢ C 0
C2
0 0 0⎥
⎢ 2 ⎥
⎢ − (1 − D ) ⎥ The closed-loop response of the system is illustrated in
⎢ 0 0 0 0 0⎥ Figure 11b. The GM of the compensated system still stands at
⎣ CO ⎦
infinite whereas the PM of the system is increased to a value
of 84.39◦ , which shows that the converter is perfectly stable in
⎡ 0 ⎤
⎢ ⎥ closed-loop operation.
⎢ ⎥ ⎡1⎤
⎢ 0 ⎥ ⎢ ⎥
⎢ ⎥ ⎢ ⎥
⎢ VC2 + VO ⎥ ⎢1⎥ 4 COMPARISON OF THE PROPOSED
⎢ ⎥ ⎢ ⎥
⎢ L3 ⎥ ⎢0⎥ CONVERTER WITH VARIOUS SIMILAR
⎢ I ⎥ ⎢ ⎥ TOPOLOGIES
B1 = ⎢ L1 ⎥ B2 = ⎢ ⎥
⎢ C1 ⎥ ⎢0⎥
⎢ ⎥ ⎢ ⎥
⎢ IL3 − IL1 ⎥ ⎢ ⎥ In this section, a comparative analysis of the proposed
⎢ C2 ⎥ ⎢0⎥ buck–boost converter with some similar converters like the
⎢ ⎥ ⎢ ⎥
⎢ VCO ⎥ ⎢ ⎥ traditional buck–boost converter (TBBC) and single-ended
⎢ IL3 + ⎥ ⎣0⎦
⎢ R ⎥
primary-inductor converter (SEPIC) is appended. The param-
⎣ CO ⎦ eters taken into consideration for the comparison consists of
[ ] ⎡0⎤ the total number of reactive elements (number of inductors
C = 0 0 0 0 0 1 D = ⎢ ⎥ (NL ), number of capacitors (NC )), the total number of semicon-
⎢ ⎥
⎣0⎦
ductor elements (number of switches (NS ), number of diodes
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2740 MALICK ET AL.

FIGURE 12 (a) Comparison of the voltage gain of the proposed converter with similar converters. (b) Comparison of the voltage gain for an extended range.
(c) Comparison of normalized switch stress of proposed converter with various similar topologies.

(ND )) utilized in the converter, ideal voltage gain, the normal- switching stress with a larger number of elements. The con-
ized semiconductor switch stress, and the duty cycle for which verters presented in [[16, 17]] do not have continuous input
the converter operates at the boundary of buck and boost mode. current and hence are not suitable for renewable energy appli-
as shown in Table 1. The graph for the comparison of the ideal cations. The converter [18] has a continuous input current,
gain of the topologies is shown in Figure 12a,b, and the compar- produces a high gain but less than the proposed topology
ison of normalized switch stress for the topologies is depicted and the same as in [17], however due to a large number of
in Figure 12c. The main advantage of converter is that quadratic elements it produces a lower gain per element. Most of the
buck operation is possible for lower duty cycles whereas, for converters like the ones proposed in [14–15] and [22] includ-
boost operation a larger duty cycle range is available. The pro- ing the TBBC and SEPIC converter, achieves unity gain at
posed converter operates in buck mode for duty cycles lower 50% duty cycle and operate in buck region for half the time.
than 26.8% and in boost mode for higher duty cycles. Further- This buck mode is also a low output power zone and the pro-
more, due to quadratic gain, the boost converter achieves a high posed converter transitions from the buck mode at 26.8% duty
gain at higher duty ratios. cycle.
The proposed topology produces a high gain during its volt- The converter proposed in [2] produces the same gain as
age boosting stage for the duty cycle greater than 26.8%. The the proposed topology. The converter however produces higher
gain is around 4 times at a duty ratio of 50%. The TBB converter switching stress as compared to the first switch of the proposed
has a discontinuous input current unlike the proposed topology topology at a duty ratio of more than 30%. The converter in
and its high gain is also restricted. The SEPIC converter on the [19] neither has a common ground nor continuous input cur-
other hand has a pulsating output current and generally requires rent while the converter in [20] lacks the latter. The converter in
large series capacitors and high current handling capacities. The [21] on the other hand has both but utilizes a large number of
converter proposed in [13] has a lower voltage gain than the elements. The converter [22] produces a large switching stress
TBBC while the switch withstands half the voltage as in the case at lower duty ratios while the converter [23] produces a lower
of TBBC. gain as compared to the proposed topology. The converter [24]
The converters [14, 15] have continuous input current but has a large number of elements as compared to the proposed
the converter in [14] utilizes a single switch but has high topology.
 TABLE 1 Comparative analysis of various similar converters with the proposed converter on basis of various parameters.
MALICK ET AL.

Element(s) CCM Voltage Normalized Switch

Gain Stress Continuous Input Gain per total elements at Boundary operation
V V
Topology NL NC NS ND NT ( O) ( S) Current 60% Duty Ratio (D) point for unity gain
Vin VO
D 1
TBBC 1 1 1 1 4 No 0.375 0.50
1−D D
D 1
SEPIC 2 2 1 1 6 Yes 0.25 0.50
1−D D
2D 1
[13] 3 4 1 2 10 Yes 0.30 0.33
1−D 2D
D 2 1
[14] 3 3 1 5 12 ( ) Yes 0.18 0.50
1−D D2
D 2 1
[15] 2 2 2 2 8 ( ) S1 = Yes 0.28 0.50
1−D D
1−D
S2 =
D
3D 1
[16] 3 5 1 3 12 No 0.37 0.25
1−D 3D
D(2−D) 1
[17] 2 2 1 3 8 No 0.65 0.293
(1−D)2 D(2−D)
D(2−D) 1
[18] 2 5 1 6 14 S1 = Yes 0.37 0.293
(1−D)2 D(2−D)
1−D
S2 =
D(2−D)
2D 1+D
[2] 2 3 2 3 10 S1 = Yes 0.75 0.268
(1−D)2 2D
1−D
S2 =
2D
2D 1
[19] 2 3 1 2 8 No 0.37 0.33
1−D 2D
2D 1
[20] 2 3 1 2 8 No 0.37 0.33
1−D 2D
3D 1
[21] 4 6 1 3 14 Yes 0.32 0.25
1−D 3D
D 2 1
[22] 2 2 2 2 8 ( ) S1 = No 0.28 0.50
1−D D
1−D
S2 =
D2
D
[23] 2 2 2 2 8 S1 = 1 Yes 0.46 0.382
(1−D)2 1−D
S2 =
D
2D(2−D) 1
[24] 4 5 2 3 14 S1 = Yes 0.75 0.183
(1−D)2 2D(2−D)
1−D
S2 =
2D(2−D)
2D 1−D
Proposed 3 3 2 4 12 S1 = Yes/Yes 0.625 0.268
(1−D)2 D
Converter 1
S2 =
D
2741

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2742 MALICK ET AL.

(MTTF) for the case can be given as:

∞ 1
MTTF = ∫ P1 (t ) dt = (25)
t =0 𝜆12

For the Markov model having more than two operating states,
the reliability of the converter is defined as the summation of all
the probabilities of failure of the converter including the healthy
state and the derated states. The reliability hence is given as:

∑
s
R (t ) = Pi (t ) (26)
i=1
FIGURE 13 Markov model representation for the proposed converter.
where s represents all the derated state operation of the con-
verter and Pi (t ) is the probability of failure of the ith state
with 𝜆i j representing the failure rate from state i to state j. The
probability function of the system is defined as:
5 RELIABILITY ANALYSIS OF THE
PROPOSED CONVERTER dPi (t )
= Pi (t ) [A] (27)
dt
5.1 Markov model for the proposed
converter The state space matrix [A] is given as:

Here, an improved Markov model is used to carry out the reli- ⎡𝜆11 𝜆12 𝜆13 𝜆14 ⎤
ability analysis of the proposed buck–boost converter. In the ⎢ ⎥
⎢ 0 𝜆22 0 𝜆24 ⎥
Markov model, the reliability of the converter is obtained by A =⎢ ⎥
studying the effect of faults encountered on various elements ⎢ 0 0 𝜆33 𝜆34 ⎥
of the converter. The semiconductor devices like switches and ⎢ ⎥
diodes used in the topology are assumed to be prone to both, ⎣ 0 0 0 0 ⎦
open circuit (OC) and short circuit (SC) faults. In improved
Markov modelling, the fault probability of the short circuit fault Any path provided between the states i and j in the Markov
is considered as αs . Hence the probability of an open circuit model is represented by its suitable failure rate (𝜆i j ) in the state
fault will be (1–αs ) where the probability of a short circuit fault space matrix at the location corresponding to the ith row and jth
is generally higher than that of an open circuit fault. This means column. Upon solving the above equation of probability func-
the value of αs is kept higher than 0.5. The short circuit prob- tion by substituting the value of the state space matrix, we can
ability factor αs aids in a degree of freedom to determine the obtain the generalized values of probabilities of the different
reliability profile of the converter at different values of short cir- states as:
cuit proneness of the semiconductor elements of the converter. ⎧ e𝜆ii t
⎪ i = 1
The consideration of αs makes improved Markov model supe- Pi (t ) = ⎨ 𝜆1i (𝜆 −𝜆 )t (28)
rior than the conventional Markov model. The capacitors and ⎪ 𝜆11 −𝜆ii e 11 ii i ≠ 1
inductors on the other hand being passive devices are assumed ⎩
to be prone to only short circuit faults. The Markov model
represents different states as shown in Figure 13, where state Initially, the converter is assumed to be working in the healthy
1 corresponds to a healthy operation state of the converter. operating state (State 1) and hence all the probabilities of
States 2 and 3 represent derated operation states where par- derated and absorbing states are considered to be 0.
tial power is fed at the load. The converter hence provides a
[P1 (0 ) , P2 (0 ) , P3 (0 ) , P4 (0 )] = [1 0 0 0] (29)
voltage gain lower than the rated output gain. State 4 corre-
sponds to the absorbing or failure state where no output is
The mean time to failure (MTTF) of the converter is the
obtained.
integration of the reliability function and is stated as:
For a two-state Markov model, where state 1 represents
a healthy state and state 2 represents an absorbing state the
⎧ ∞
reliability R(t) is given as: ⎪ MTTF = ∫ R (t ) dt
⎪ t =0
R (t ) = P1 (t ) = e−𝜆12 t (24) ⎨ ( ) (30)
⎪MTTF = −1 + ∑ 𝜆1i
s
1 1
−
where, 𝜆12 is the summation of failure rates of components ⎪ 𝜆11 i=2 𝜆 −𝜆 𝜆 𝜆11
⎩
11 ii ii

under both OC and SC conditions. The mean time to failure

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MALICK ET AL. 2743

TABLE 2 Effect of fault(s) across elements on the output voltage. The failure rates of the components according to the
Derated output voltage improved Markov model as shown in Table 3 and the equation
Type of fault
VODerated for the constant factors as shown in Table 3 is given as:
Element (OC or SC) ( × 100)%
VORated

S1 OC 29.54 ⎧ 𝜆12 = (1 − 𝛼S ) 𝜆S
⎪
S2 OC 70.45 ⎪ 𝜆13 = (1 − 𝛼S ) 𝜆S
⎪
S1 or S2 SC Failure state ⎪
⎨ 𝜆14 = (2 − 𝛼S ) 𝜆D + 2𝛼S 𝜆S + 𝜆CO + 𝜆L (32)
D1 or D2 OC 50.05 ⎪
D3 or D0 OC or SC Failure state ⎪ 𝜆24 = 4 (1 − 𝛼S ) 𝜆D + (1 − 𝛼S ) 𝜆S + 𝜆C + 𝜆C 0 + 𝜆L
⎪
D1 or D2 SC 75.45 ⎪ 𝜆 = (2 − 𝛼 ) 𝜆 + (1 − 𝛼 ) 𝜆 + 𝜆 + 𝜆 + 𝜆
⎩ 34 S D S S C C0 L
C1 SC 50.17
1 − 𝛼S −(0.206𝛼 +0.205 )t
C2 or C0 SC Failure state R (t ) = e−(0.442−0.014𝛼S )t − e S
𝛼S + 0.995
L1 or L2 or L3 SC Failure state
1 − 𝛼S
− e−(0.249𝛼S +0.176 )t (33)
1.208𝛼S + 0.854

1 1 − 𝛼S
5.2 Operation of proposed converter during MTTF = +
0.263𝛼S − 0.265 (0.442 − 0.014𝛼S ) (1.208𝛼S + 0.854 )
faulty conditions
2 1 − 𝛼S
+ +
(0.442 − 0.014𝛼S ) (0.22𝛼S − 0.237 ) (𝛼S + 0.995 )
In this part of the section, an analysis of the converter’s oper-
ation during faulty conditions is presented. The effect of OC years∕failure (34)
and/or SC on various components of the converter as a per-
centage of the derated output voltage as compared to the The reliability and the MTTF of the converter can be easily
voltage at rated operation is discussed. calculated for any failure probability of the switch or diode(s) by
From Table 2, we can easily see the output voltage decreases varying the value of 𝛼S as per the need. For a short circuit prob-
as faults occur across the switch and passive elements of the ability of 75%, the MTTF of the converter is 5.743 years/failure
converter. The proposed converter fails to operate if either whereas for an SC probability of 85% the MTTF is obtained as
switch undergoes an SC fault, whereas it feeds partial power if 5.647 years/failure.
either of them experiences an OC fault. An occurrence of OC
fault in diode, either D1 or D2 still results in producing a gain
of more than 75% as compared to the rated operation and the
occurrence of SC in the diodes results in a partial gain of 50%. 5.4 Variation of reliability and MTTF of the
An OC or SC fault in either diode D3 or D0 results in the failure converter
of operation of the converter. The short circuit fault in passive
components like capacitor C1 results in partial power operation In the current section of the paper, the effect of different con-
of the converter. However, SC faults in capacitor C2 or C0 or verter parameters on the converter’s reliability is discussed. The
any inductor result in total failure. reliability and MTTF of the proposed converter decrease as the
SC probability (αs ) of the semiconductor devices overpower the
5.3 Reliability analysis of the converter OC probability as shown in Figure 14a. The converter is still
using improved Markov modelling 57% reliable after three million hours of operation with the con-
verter for 75% SC probability while it decreases to 50% when
To proceed with the reliability analysis of the converter, the the SC probability increases to 85%. The MTTF on the other
failure rates for various parameters of the converter like hand lies above 5 years if the SC probability is below 94% as
switches(𝜆S ), diodes(𝜆D ) and capacitors(𝜆C )are to be obtained. shown in Figure 14b. The reliability is evaluated and presented
The failure rates of the various elements are obtained and for- in the form of 3D graphs where different parameters are varied
mulated as presented by the authors in [25, 26] and the equations over time.
for the determination of failure rates are given as:

⎧ 𝜆S = 𝜆B .𝜋T .𝜋A .𝜋Q .𝜋E

⎪ 5.4.1 Effect of duty cycle (D)
⎪ 𝜆 = 𝜆 .𝜋 .𝜋 .𝜋 .𝜋 .𝜋
⎪ D B T S CD Q E
The variation in the output voltage of the converter is generally
⎨ (31)
⎪ 𝜆C = 𝜆B .𝜋T .𝜋C .𝜋V .𝜋SR. 𝜋Q .𝜋E obtained by changing the duty cycle of the converter to facilitate
⎪ the required rated operation of the load. This variation of duty
⎪ cycle hence affects the reliability of the converter as it alters the
⎩ 𝜆L = 𝜆B .𝜋T .𝜋Q .𝜋E
 2744

TABLE 3 Expression for constants of failure rate for various elements.

Failure Constant Switch Diode Capacitor Inductor

𝜆B —Base failure rate 0.012 0.030 0.00037 0.000030

[ ] [ ] [ ] [ ]
−1925× ) −3091× ) −1740× ) −1276.54× )
𝜋T —Temperature factor exp ( 1 1 exp ( 1 1 exp ( 1 1 exp ( 1 1
− − − −
TJ +273 298 TJ +273 298 T +273 298 THS +273 298
TJ is the junction temperature T is the capacitor ambient THS is the hotspot temperature
temperature
𝜋A —Application factor 8 – – –
𝜋Q —Quality factor 1 1 1 1
𝜋E – Environmental factor 1 1 1 1
𝜋S —Electrical stress factor – 0.71 exp(1.1S ) – –
Actual Power dissipation
S =
Rated Power
𝜋CD —Contact construction – 1 – –
factor
𝜋C —Capacitance factor – – C 0.09 –
S 5
𝜋V —Voltage stress factor – – 1+( ) –
0.6
𝜋SR —Series resistance factor – – 𝜋SR = –
E f fective resistance
( between capacitor )
and supply
Voltage across
( )
capacitor
MALICK ET AL.

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MALICK ET AL. 2745

FIGURE 14 (a) Variation of reliability of the converter with time as the short circuit (SC) probability is increased. (b) Variation of mean time to failure (MTTF)
of the converter with SC probability.

FIGURE 15 (a) Variation of reliability with time and duty ratio (D). (b) Variation of MTTF with duty ratio (D) as αs is increased.

voltage switching stress across the switch(s). Here, the variation 50% with high reliability while it depicts a high MTTF while
of reliability of the converter is assessed when the duty cycle operating near a 35% duty ratio. With the suggested improved
(D) of the switch is varied keeping the short circuit probabil- Markov model and converter analysis, the 3D plot is illustrated
ity at 75%. The reliability of the converter is slightly lower at in Figure 15b. Consequently, a lower value of input voltage leads
extreme duty ratios as they result in maximum stress across the to lesser voltage stress on the switch which increases the over-
switch. The variation of failure rate of different components as all reliability of the converter and hence a lower probability for
a function of duty cycle [27] is given in (30): a fault to occur across the switch. Furthermore, the reliabil-
ity of the converter decreases with time due to the aging of
⎧ ⎡ ⎛ ⎞⎤ devices and elements, lack of proper maintenance, manhandling
⎪ ( ) ⎢ ⎜ 1 1 ⎟⎥ of equipment etc. The converter’s reliability decreases from 95%
𝜆 = ⎢−1925 ⎜ −
298 ⎟⎟⎥⎥
⎪ s D 0.48 exp
⎪ ⎢ ⎜ 298 + 42.694D + 2.166 to 78% at the duty ratio of 50% when 0.5 million hours of the
⎪ ⎣ ⎝ D2 ⎠⎦
⎪ 0.0038 converter are completed. The converter however achieves an
𝜆D (D ) =
⎪ (6D )2.38 MTTF of around 5.5 years for αs of 75% and an MTTF of 5.32
⎨ [ ( )] (35)
⎪ exp −3091
1
−
1 years for αs of 85% while operating at a 35% duty ratio.
⎪ 355.968+0.736D 298
⎪ −3 ( )
⎪ 𝜆C (D ) = 7.63 × 10 2.37D 3 + 1
⎪ 5.4.2 Effect of input voltage (Vin )
⎪
⎩ 𝜆CO (D ) = 1.154 × 10−2
The reliability of the converter is often affected by a variation
Reliability of 95% and MTTF of 5.25 years is achieved by in input voltage as it affects the voltage and current stresses
the converter at a duty ratio of 0.5 after 0.05 million hours for of the switch and diodes. In various applications like solar PV
75% SC probability as shown in Figure 15a respectively, while it systems, voltage variations due to reasons like partial shading
has a reliability of 50% while operating closer to extreme duty and unequal load sharing are common. With these fluctuations
ratios. The converter performs optimally for duty ratios near at the input, significant ripples in voltage are introduced in the
 17521424, 2023, 11, Downloaded from https://ietresearch.onlinelibrary.wiley.com/doi/10.1049/rpg2.12787, Wiley Online Library on [29/11/2024]. See the Terms and Conditions (https://onlinelibrary.wiley.com/terms-and-conditions) on Wiley Online Library for rules of use; OA articles are governed by the applicable Creative Commons License
2746 MALICK ET AL.

FIGURE 16 (a) Variation of reliability with time

and input voltage (Vin ). (b) Variation of MTTF with
input voltage (Vin ) as αs is increased.

system which degrades the overall performance and reliability TABLE 4 Experimental values of various parameters of elements used in
of the system by imparting severe voltage and current stresses the converter.
across the semiconductor devices. The variation of failure rates Parameter Symbol Value
of elements with variation in input voltage [27] is given in (31).
Input voltage Vin 20 V
[ ( )] Duty cycle D 0.2, 0.4, 0.6
⎧ 1 1
⎪𝜆s (Vin ) = 0.48 exp −1925 −
⎪ 298 + 2.18 × 10−4Vin2 + 4.47 × 10−2Vin 298 Output power PO 10 W, Buck operation
⎪ 120 W, Boost operation
⎪ 𝜆D (Vin ) = 2.052 × 10−4
⎪ Inductors L1 ,L2 650 μH, ESR = 0.12 Ω
⎪ [ ( )]
⎨ 1 1 L3 400 μH ESR = 0.14 Ω
⎪ exp −3091 −
⎪ 298 + 6.75 × 10−6Vin2 + 0.19Vin 298
Capacitors C1 − C3 50 μF, 200 V
⎪ −3 ( −8 3 )
⎪ 𝜆C (Vin ) = 7.63 × 10 1.89 × 10 D + 1 C0 100 μF, 350 V
⎪
⎪ ( ) Diodes D0 to D6 SF8L60USM
⎩ 𝜆C0 (Vin ) = 7.63 × 10−3 2.96 × 10−7 D 3 + 1
(36) Power MOSFETs S1 , S2 SPW52N50C3

The converter achieves a reliability of 95% when the input Driver TLP250H
voltage is around 20 V at 0.3 million hours as shown in Controller STM32 Nucleo
Figure 16a. However, due to lesser voltage, the converter has Switching frequency fs 50 kHz
lower efficiency. As the input voltage is increased to 50 V, the
converter achieves reliability of 87% and 75% after 0.5 and
0.8 million hours of working respectively. The MTTF of the
converter decrease as the input voltage is increased as seen in
Figure 16b. The converter obtains an MTTF of 3.5 and 3 years 6 EXPERIMENTAL RESULTS OF THE
as the SC probability is increased from 75% to 95% for the 20 V PROPOSED CONVERTER
input voltage operation of the converter.
The experimental hardware results of the 200 W prototype of
the proposed buck–boost converter topology are presented in
5.4.3 Effect of output power (PO ) this section. The results verify the theoretical analysis of the
converter and analyze its practical functionality. The results are
A power converter feeds a load at the output designed for a presented while the converter is operated at 20%, 40%, and
specified power and voltage. Hence, variations in this power 60% duty ratios. The experimental bench setup of the proposed
affect the useful life of various elements of the converter and topology is shown in Figure 18. The parameters of all the ele-
cost the converter its reliability over time. The reliability of ments and devices used for taking the results are mentioned in
the converter decreases as the output power is increased and it Table 4.
achieves reliability of 94% while operating at lower powers like Figure 19a depicts, the waveform of the output voltage, input
50 W after 0.2 million hours of operation, but this operation voltage, and voltage across capacitor C1 at a 20% duty ratio. The
results in poor efficiency and high losses. The converter when input voltage is kept at 20 V to take the value of the results and
operated at higher powers is still 85% reliable while operating measurements of the proposed converter. The converter oper-
at 500 W power after 0.4 million hours as shown in Figure 17a. ates in buck mode during this duty cycle operation and produces
The reliability of the converter decreases to 70% after a million an inverted output of 11 V (taken on positive side) at the output
hours of 500 W operation of the converter. The MTTF of 4 with a voltage of 21 V across the VMC capacitor. Figure 19b,
years is obtained by the converter keeping αs as 75% for 100 W on the other hand, depicts an inductor current of through the
output power operation as shown in Figure 17b. L1 at 20 V input. The maximum current of 1.8 A is achieved
 17521424, 2023, 11, Downloaded from https://ietresearch.onlinelibrary.wiley.com/doi/10.1049/rpg2.12787, Wiley Online Library on [29/11/2024]. See the Terms and Conditions (https://onlinelibrary.wiley.com/terms-and-conditions) on Wiley Online Library for rules of use; OA articles are governed by the applicable Creative Commons License
MALICK ET AL. 2747

FIGURE 17 (a) Variation of reliability with time and output power (PO ). (b) Variation of MTTF with output power (PO ) as αs is increased.

current which increases linearly to a maximum value of 22 A

while charging during the period when the switch is ON, and
then reaches a minimum of 14 A while discharging during the
period when the switch is OFF as shown in Figure 20c.
Figure 21a depicts, the waveform of the output and input
voltages with gate-to-source voltage at a 60% duty cycle. The
output of 140 V is obtained at the output across the resistor at
20 V input. The converter hence produces an output of seven
times the input voltage which is 6.66% lesser than the ideal gain
of the proposed converter. The voltages across the capacitor
C2 and C3 stands at 100 and 140 V respectively as shown in
Figure 21b. The switches bear a voltage stress of 92 and 240 V
respectively during their OFF states.
FIGURE 18 Experimental bench setup of the proposed topology.
For a DC–DC converter the output voltages, capacitor volt-
ages, and inductor currents are checked to verify the working
of the converter. The converter should produce a suitable volt-
in inductor L3 during charging when the switch is ON, while a age gain at different duty ratios while maintaining continuous
minimum value of 0.8 A flows in the discharging state. conduction and constant capacitor voltages. The aspect which is
As shown in Figure 20a, the duty cycle of switches is kept at verified is that the converter can operate in both buck and boost
40% with a gate voltage of 20 V applied at its gate terminal. An modes. The different duty ratios are taken to test whether the
output of 41 V is obtained at the resistor terminals whereas the converter can work at different power levels and can produce
VMC capacitor sustains a voltage of around 18 V. The capacitor different output voltages and currents. It has been experimen-
C2 and C3 have a voltage of 66 and 41 V respectively as shown tally validated that the converter can work at different duty
in Figure 20b. The switch S1 and S2 withstand a voltage of 64 ratios. The capacitor voltages and inductor currents are also
and 108 V respectively across them during their turn OFF state. shown in continuous conduction mode to validate the working
The inductors L1 used at the input side VMC carry a continuous of the converter.

FIGURE 19 (a) Top to bottom: Output voltage, capacitor C1 voltage, input voltage and gate pulse at 20% duty cycle. (b) Inductor L1 and L3 current, and gate
pulses at 20% duty cycle.
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2748 MALICK ET AL.

FIGURE 20 (a) Output voltage, capacitor C1 voltage, input voltage and gate pulse at 40% duty cycle. (b) Capacitor C3 and C2 voltage, Switch voltage stress
and gate pulse at 40% duty cycle. (c) Inductor L1 current, Inductor L3 current and gate pulses at 40% duty cycle.

FIGURE 21 (a) Output voltage, capacitor C1 voltage, input voltage and gate pulse at 60% duty cycle. (b) Capacitor C3 and C2 voltage, switch voltage stress and
gate pulse at 60% duty cycle.

7 CONCLUSION FUNDING INFORMATION

There is no funding received for this work.
The proposed buck–boost converter operates in buck mode
for a duty ratio of less than 26.8% duty cycle and produces a DATA AVAILABILITY STATEMENT
quadratic gain of four times the TBBC at 50% duty cycle along Data sharing is not applicable to this article, since no datasets
with reduced switching stress. The converter operates at high were generated or analyzed during the current study.
efficiency with a maximum operating efficiency of 96.8% and
an efficiency of 94.5% while operating at 100 W output power. ORCID
Furthermore, dual switch operation of the converter, for the Kazem Varesi https://orcid.org/0000-0002-9802-1058
same duty cycle provides better reliability of the converter at
a derated output even when one of the switches experiences an REFERENCES
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