Abstract_2_1mux (1)
Abstract_2_1mux (1)
When the control signal C is low then the upper transmission gate turns OFF and it will not
allow A to pass through it, at the same time the lower transmission gate is 'ON' and it allows
B to pass through it so the output = B.
Schematic diagram:
The circuit schematic of the 2:1 MUX Using Transmission Gate (using 0.5um Technology) in
eSim is as shown below:
1.Ngspice Plots-
References:
1) https://www.electronics-tutorial.net/Digital-CMOS-Design/Pass-
Transistor-Logic/2-1-MUX-using-transmission-gate/
2) https://www.allaboutcircuits.com/technical-articles/implementing-
multiplexers-with-pass-transistor-logic/
3) http://vlsi-iitg.vlabs.ac.in/Multiplexer_theory.html