Madhav Institute of Technology & Science,

Gwalior
Department of Information Technology

COMPUTER SYSTEM ORGANIZATION: 160311

UNIT – II & III
COURSE INCHARGE: MRS. NEHA BHARDWAJ,
ASSISTANT PROFESSOR,
DEPTT. OF IT, MITS, GWALIOR
SYLLABUS

Ò Computer Arithmetic: Addition and Subtraction with Signed-Magnitude,

Multiplication Algorithm, Division Algorithm, Floating-Point, Arithmetic
Operations.

Ò Central Processing Unit (CPU): General Purpose Register Organization, Stack

Organization, Instruction Formats, Addressing Modes, Data Transfer and
Manipulation, Program Control, Reduced Instruction Set Computer (RISC),
Hardwired and Microprogrammed Control.

Course IC-Mrs. Neha Bhardwaj, Deptt. of IT, MITS 2

BINARY NUMBER REPRESENTATION

In signed representation, ‘1’ bit represents ‘sign’ and ‘n-1’ represents

‘magnitude’. ‘1’ at MSB position represents ‘negative sign’ and ‘0’ at MSB
position represents ‘positive sign’.

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Course IC-Mrs. Neha Bhardwaj, Deptt. of IT, MITS
Sign magnitude numbers

Range: -2(n-1) to +2(n-1)

(if n=4, then range of numbers will be -7 to +7)

-1510 as a 6-bit number⇒1011112

+2310 as a 6-bit number⇒0101112
-5610 as a 8-bit number⇒101110002
+8510 as a 8-bit number⇒010101012
-12710 as a 8-bit number⇒111111112
+12710 as a 8-bit number⇒011111112

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Course IC-Mrs. Neha Bhardwaj, Deptt. of IT, MITS
 One’s Complement Number

Range: -2(n-1) to +2(n-1)

(if n=4, then range of numbers will be -7 to +7)

Subtraction: 115 – 27 = 88 (115 à 01110011 & – 27 à11100100)

01110011
+ 11100100
overflow → 1 01010111
Add this overflow bit to the end of the result and discard from MSB
01010111
+1
01011000 à 88 (in decimal)
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Course IC-Mrs. Neha Bhardwaj, Deptt. of IT, MITS
Two’s Complement Number

Range: -2(n-1) to +2(n-1)

(if n=4, then range of numbers will be -8 to +7)

Subtraction: 115 – 27 = 88 (115 à 01110011 & 27 à 00011011)

( -27 à 11100101)

01110011 - 00011011
01110011 + 11100101 = 1 01011000 , discard this 1
answer is 01011000 i.e. 88

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Course IC-Mrs. Neha Bhardwaj, Deptt. of IT, MITS
ADDITION AND SUBTRACTION

Ò Addition and Subtraction of Signed Magnitude Numbers (Eight different

cases, with 2 signed magnitude no. and 2 different operations )

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Ò Hardware Implementation for Signed- magnitude Addition and Subtraction

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 Ò Flow chart for
addition and
subtraction operations

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MULTIPLICATION ALGORITHM

Ò Hardware for multiply operation

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Ò Flow chart for multiply operation

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Ò Numerical Example for Binary Multiplier

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Course IC-Mrs. Neha Bhardwaj, Deptt. of IT, MITS
BOOTH MULTIPLICATION ALGORITHM

Ò Hardware for Booth algorithm

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Ò Booth Multiplication Algorithm for
multiplication of signed 2’s
complement numbers

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Ò Example of Multiplication with Booth Algorithm

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FLOATING POINT ARITHMETIC

Ò The IEEE (Institute of Electrical and Electronics Engineers) has produced a

standard for floating point arithmetic. This standard specifies how single
precision (32 bit) and double precision (64 bit) floating point numbers are to be
represented, as well as how arithmetic should be carried out on them.

Ò The first bit is the sign bit, S, the next eight bits are the exponent bits, ‘E’, and
the final 23 bits are the fraction ‘F’ (Single Precision). Instead of the signed
exponent E, the value stored is an unsigned integer E’ = E + 127, called the
excess -127 format.

Ò 0 10000000 00000000000000000000000
= +1 * 2^(128-127) * 1.0 = 2

Ò 0 10000001 10100000000000000000000
= +1 * 2^(129-127) * 1.101 = 6.5

Course IC-Mrs. Neha Bhardwaj, Deptt. of IT, MITS 16

ADDITION

Example on decimal value given in scientific notation:

3.25 x 10 ^3
+ 2.63 x 10 ^ -1
—————–
first step: align decimal points
second step: add

3.25 x 10 ^ 3
+ 0.000263 x 10 ^ 3
——————–
3.250263 x 10 ^ 3

Course IC-Mrs. Neha Bhardwaj, Deptt. of IT, MITS 17

MULTIPLICATION

Example on decimal values given in scientific notation:

3.0 x 10 ^ 1
+ 0.5 x 10 ^ 2
—————–

Algorithm: multiply mantissas

add exponents

3.0 x 10 ^ 1
+ 0.5 x 10 ^2
—————–
1.50 x 10 ^ 3

Course IC-Mrs. Neha Bhardwaj, Deptt. of IT, MITS 18

GENERAL REGISTER ORGANIZATION

A bus organization for seven CPU registers is shown here (next slide). The output of
each register is connected to two multiplexers (MUX) to form the two buses A and B.

The selection lines in each multiplexer select one register or the input data for the
particular bus.

The A and B buses form the inputs to a common arithmetic logic unit (ALU).

The result of the micro-operation is available for output data and also goes into the
inputs of all the registers.

The register that receives the information from the output bus is selected by a
decoder.

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.

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 SEL A (3 bits) SEL B (3 bits) SEL D (3 bits) OPR (5 bits)

Control Word

Ò The control unit that operates the CPU bus system directs the information
flow through the registers and ALU by selecting the various components in
the system. For example, to perform the operation
R1 <-- R2 + R3
the control must provide binary selection variables to the following selector
inputs:
Ò 1. MUX A selector (SELA): to place the content of R2 into bus A.

Ò 2. MUX B selector (SELB): to place the content o f R3 into bus B.

Ò 3. ALU operation selector (OPR): to provide the arithmetic addition A+ B.

Ò 4. Decoder destination selector (SELD): to transfer the content of the output

bus into R1.
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Course IC-Mrs. Neha Bhardwaj, Deptt. of IT, MITS
Ò Control Word: There are 14 binary selection inputs in the unit, and their
combined value specifies a control word.

Ò The three bits of SELA select a source register for the A input of the ALU. The
three bits of SELB select a register for the B input of the ALU. The three bits
of SELD select a destination register using the decoder and its seven load
outputs. The five bits of OPR select one of the operations in the ALU.

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Course IC-Mrs. Neha Bhardwaj, Deptt. of IT, MITS
STACK ORGANIZATION

SP <- SP + 1 Increment stack pointer

M[SP] <- DR Write item on top of the stack
If (SP = 0) then (FULL <-- 1) heck if stack is full
EMTY <-- 0 Mark the stack not empty

Block Diagram of 64-word Stack

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Course IC-Mrs. Neha Bhardwaj, Deptt. of IT, MITS
INSTRUCTION CATEGORY

Ò Memory Reference Instruction (MRI)

Ò Register Reference Instruction (RRI)
Ò Input Output Instruction (IOI)

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Course IC-Mrs. Neha Bhardwaj, Deptt. of IT, MITS
INSTRUCTION FORMATS

Instruction is of variable length depending upon the number of addresses it

contains. Generally, CPU organization is of three types based on the number of
address fields:

Ò Single Accumulator organization

Ò General register organization
Ò Stack organization

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Based on the number of address, instructions are classified as:
[Expression: X = (A+B)*(C+D)]
PUSH A TOP = A

Zero Address Instructions

PUSH B TOP = B
(Stack based memory)
ADD TOP = A+B

PUSH C TOP = C

PUSH D TOP = D

ADD TOP = C+D

MUL TOP = (C+D)*(A+B)

POP X M[X] = TOP

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Course IC-Mrs. Neha Bhardwaj, Deptt. of IT, MITS
One Address Instructions (Single Accumulator organization)

LOAD A AC = M[A]

ADD B AC = AC + M[B]

STORE T M[T] = AC

LOAD C AC = M[C]

ADD D AC = AC + M[D]

MUL T AC = AC * M[T]

STORE X M[X] = AC

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Two Address Instructions
Three Address Instructions

MOV R1, A R1 = M[A]

ADD R1, B R1 = R1 + M[B]

ADD R1, A, B R1 = M[A] + M[B]

MOV R2, C R2 = C
ADD R2, C, D R2 = M[C] + M[D]

ADD R2, D R2 = R2 + D
MUL X, R1, R2 M[X] = R1 * R2

MUL R1, R2 R1 = R1 * R2

MOV X, R1 M[X] = R1

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ADDRESSING MODES

Ò The term addressing modes refers to the way in which the operand of an
instruction is specified.

Ò The addressing mode specifies a rule for interpreting or modifying the

address field of the instruction before the operand is actually executed.

Types of addressing modes

Ò Immediate Addressing Mode –

In immediate addressing mode the source operand is always data. If the
data is 8-bit, then the instruction will be of 2 bytes, if the data is of 16-bit
then the instruction will be of 3 bytes.
Ò Examples:
MVI B 45 (move the data 45H immediately to register B)
LXI H 3050 (load the H-L pair with the operand 3050H immediately)
JMP address (jump to the operand address immediately)

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Ò Register Addressing Mode –
In register addressing mode, the data to be operated is available inside the
register(s) and register(s) is(are) operands. Therefore the operation is
performed within various registers of the microprocessor.
Ò Examples:
MOV A, B (move the contents of register B to register A)
ADD B (add contents of registers A and B and store the result in register A)
INR A (increment the contents of register A by one)

Ò Direct Addressing Mode –

In direct addressing mode, the data to be operated is available inside a
memory location and that memory location is directly specified as an
operand. The operand is directly available in the instruction itself.
Ò Examples:
LDA 2050 (load the contents of memory location into accumulator A)
LHLD address (load contents of 16-bit memory location into H-L register pair)
IN 35 (read the data from port whose address is 35)

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Ò Register Indirect Addressing Mode –
In register indirect addressing mode, the data to be operated is available
inside a memory location and that memory location is indirectly specified by
a register pair.
Ò Examples:
MOV A, M (move the contents of the memory location pointed by the H-L pair to the
accumulator)
LDAX B (move contents of B-C register to the accumulator)
LXIH 9570 (load immediate the H-L pair with the address of the location 9570)

Ò Implied/Implicit Addressing Mode –

In implied/implicit addressing mode the operand is hidden and the data to
be operated is available in the instruction itself.
Ò Examples:
CMA (finds and stores the 1’s complement of the contents of accumulator A in A)
RRC (rotate accumulator A right by one bit)
RLC (rotate accumulator A left by one bit)
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Course IC-Mrs. Neha Bhardwaj, Deptt. of IT, MITS
INSTRUCTION
ADD R1, LOCA: ADD the contents of memory location LOCA to the contents
of Register R1.
(Assume that the instruction is stored in memory location 2000, the initial
value of R1 is 60 and LOCA is 8000).
Before the instruction is executed, PC contains 2000.
Content of PC is transferred to MAR.
READ request is issued to memory unit.
The instruction is fetched to MDR.
Content of MDR is transferred to IR.
PC is incremented to point to next instruction
The instruction is decoded by Control unit.
LOCA is transferred (from IR) to MAR
READ request is issued to memory unit.
The data is fetched to MDR.
The content of MDR is added to R1.
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Course IC-Mrs. Neha Bhardwaj, Deptt. of IT, MITS
Ò The steps being carried out are called micro-operations
MAR ß PC
MDR ß Mem[MAR]
IR ß MDR
PC ß PC+4
MAR ß IR[Operand]
MDR ß Mem[MAR]
R1 ß R1+ MDR

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INSTRUCTION PHASES

Fetch
Decode
Indirect
Execution

Note : all instructions have Fetch and execution cycles. Some may have indirect
cycle also.

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 UNIT –III: MICROPROCESSOR

SYLLABUS

Ò Microprocessors: Introduction of 8085 Microprocessor: Architecture,

Instruction Set, Addressing Modes, Interrupts and Basic Assembly Language
Programming.

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8085 MICRO PROCESSOR: ARCHITECTURE

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Course IC-Mrs. Neha Bhardwaj, Deptt. of IT, MITS
8085 CONFIGURATION

Ò It has the following configuration −

Ò 8-bit data bus
Ò 16-bit address bus, which can address up to 64KB
Ò A 16-bit program counter
Ò A 16-bit stack pointer
Ò Six 8-bit registers arranged in pairs: BC, DE, HL
Ò Requires +5V supply to operate at 3.2 MHZ single phase clock
Ò It is used in washing machines, microwave ovens, mobile phones, etc.

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Ò 8085 consists of the following functional units
Ò Accumulator: It is an 8-bit register used to perform arithmetic, logical, I/O &
LOAD/STORE operations. It is connected to internal data bus & ALU.

Ò Arithmetic and logic unit: It performs arithmetic and logical operations like
Addition, Subtraction, AND, OR, etc. on 8-bit data.

Ò Flag register: It is an 8-bit register having five 1-bit flip-flops, which holds
either 0 or 1 depending upon the result stored in the accumulator.
Ò These are the set of 5 flip-flops −
Ò Sign (S), Zero (Z), Auxiliary Carry (AC), Parity (P), Carry (C)

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Ò Instruction register and decoder: It is an 8-bit register. When an
instruction is fetched from memory then it is stored in the
Instruction register. Instruction decoder decodes the information
present in the Instruction register.

Ò Timing and control unit: It provides timing and control signal to

the microprocessor to perform operations. Following are the
timing and control signals, which control external and internal
circuits −
Control Signals: READY, RD’, WR’, ALE (add enable latch)
Status Signals: S0, S1, IO/M’
DMA Signals: HOLD, HLDA
RESET Signals: RESET IN, RESET OUT

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ASSEMBLY LANGUAGE PROGRAM
Write 8085 Assembly language
program to multiply two 8-bit numbers
and stored in memory location.

FLOW DIAGRAM à

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PROGRAM

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Course IC-Mrs. Neha Bhardwaj, Deptt. of IT, MITS
Ò Input Address Data
8000 DC
8001 AC

Ò Output
Address Data
8050 93
8051 D0

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REFERENCES…
Ò www.geeksforgeeks.org/
Ò Techtarget
Ò Technopidea
Ò Byjus
Ò Quora
Ò NPTEL
Ò www.learn.computerscienceonline.com
Ò www.tutorialspoint.com
Ò https://www.cs.umd.edu/ -Floating Point Arithmetic
Ò Book: Computer-System-Architecture by Morris Mano

Course IC-Mrs. Neha Bhardwaj, Deptt. of IT, MITS

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