Programmable Digital Circuits

Dr. Eng. Piotr Kurgan

Department of Microelectronic Systems

Faculty of Electronics, Telecommunications and Informatics
Lecture Outline
• Course organization
• Repetition of HDL synthesis (Verilog & SystemVerilog)
• Hardware description (ZYBO Z7 Development Board)
• SoC project architecture
• AXI interface
• Register Description Language
• Work setup/environment
• Petalinux build & configuration
• SVUnit framework in QuestaSim
• Hardware debugging & chipscope
• Outline of laboratory projects. Implementation topics
Presentation Outline
• Introduction to ZYBO Z7 development board
• Xilinx Zynq-7000 SoC architecture
• Processing System overview
• Programmable Logic overview
• System block diagram
• AXI standard
 Digilent ZYBO Z7 Development Board
External Ethernet
power supply port HDMI out port HDMI in port
microSD port (other side)

Power switch

Power select jumper

Programming mode
select jumper
USB JTAG/UART port
power & programming
Xilinx ZYNQ-7000 SoC
ARM Cortex-A9 &
28-nm 7-series FPGA

MIO PMOD port

PS pins

DDR3L Memory

USB 2.0 port XADC PMOD port

Standard PMOD port

High-speed PMOD ports
Source: https://digilent.com/reference/programmable-logic/zybo-z7/reference-manual
Xilinx Zynq-7000 APSoC Simplified Architecture
 Xilinx Zynq-7000 APSoC Architecture

Processing System (PS)

Programmable Logic (PL)

Source: https://digilent.com/reference/programmable-logic/zybo-z7/reference-manual
https://digilent.com/reference/learn/programmable-logic/doc/xilinx/zynq-technical-reference-manual
System Overview
• System components
• Petalinux image (Micro SD card)
• Communication via serial terminal
• Processing system
• PS-to-PL interface (AXI4-Lite)
• Programmable logic
• Register description (PeakRDL)
• User programmable logic
• Lower-level modules
• Periphery module (PMOD)
Baseline Project Overview
• Baseline project directory tree
AMBA AXI Architecture
• AMBA: ARM Advanced Microcontroller Bus Architecture
• AXI: Advanced eXtensible Interface
• AXI protocol features among others separate address/control and data phases
• Channel connections between Master and Slave:

Reference on AMBA AXI protocol specification: https://developer.arm.com/documentation/ihi0022/e

AXI Protocol
• AXI protocol defines independent transaction channels (r address, r data, w address, w data, w reponse)

• Address channel carries control information

• Options for data transfer between Master and Slave :
• Write transaction: using write data channel to transfer data M→S;
S uses write response channel to signal transfer completion
• Read transaction: using read data channel to transfer data S→M.

Channel architecture of write transaction Channel architecture of read transaction

AXI Channel Definition & Basic Transactions
• Each independent channel provides a set of information signals: VALID & READY
• Transaction is driven by a two-way handshake mechanism based on AND of VALID and READY
signals. Transfer occurs only when both VALID and READY are high at ACLK rising edge
• Information source uses VALID signal to show when valid address, data or control information is
available on the given channel. Destination uses READY signal to show when it can accept the
information. Both (read/write data channels) include LAST signal to indicate the final data item

VALID before READY handshake READY before VALID handshake VALID with READY handshake

After T1, source presents address, data or After T1, destination informs it can accept Transfer occurs at T2 when both VALID
control information (asserts VALID signal). information (asserts READY). and READY assertions are recognized.
After T2, destination can accept After T2, source presents address, data or
information (asserts READY signal). control information (asserts VALID).
Transfer occurs at T3 (source must keep its Transfer occurs at T3.
information stable until transfer).
AXI4-Lite Protocol
• AXI protocol includes AXI4-Lite specification with simpler control and register interfaces
• Key features:
• All transactions are of burst length 1
• Data bus of 32 or 64 bits
• No buffering, no modifications
• No exclusive access

AXI4-Lite Interface Signals

Protection type of write transaction [2:0] Indicates valid byte lanes (e.g. if Protection type of read transaction
[2] 0 – data access, 1 – instruction access WSTRB is set to 1010, only 2nd
[1] 0 – secure access, 1 – non-secure access and 4th data word are valid and
[0] 0 – unprivileged access, 1 – privileged access [1:0]
should be written)
0b00 – OKAY; 0b01 – EXOKAY
0b10 – SLVERR; 0b11 – DECERR
AXI4-Lite Protocol: Read Transaction Sequence
• Master device (e.g. a CPU) initiates read transaction, Slave device responds to the request
• Read transaction sequence can be divided into (i) address phase and (ii) data phase
• Read transaction is realized over two separate channels: read address and read data
• Address phase:
• Master sends read address (ARADDR) and control signals (ARVALID, ARPROT) to the Slave
• Slave acknowledges the address with ARREADY
• Data phase:
• Slave sends requested data (RDATA) and response signals (RVALID, RRESP) to the Master
• Master acknowledges the data with RREADY
 AXI4-Lite Protocol: Read Transaction Timing Diagram
Slave asserts
Master puts addr on ARREADY to indicate
Read Addr Channel it is ready to receive
addr on the bys
User-side valid transaction
Master asserts
ARVALID to indicate
addr is valid

Master asserts
RREAD to indicate it is Slave asserts RVALID
Since both ARVALID and Slave puts requested
ready to receive data to indicate data is valid
ARREADY are asserted, data on the Read Data
from Slave handshake occurs at the next CLK channel
rising edge; after that ARVALID
and ARREADY are deasserted
Since both ARVALID and
ARREADY are asserted, the next
CLK rising edge completes the
transaction and RREADY &
Source: https://docs.amd.com/r/en-US/pg165-cmac/User-Side-AXI4-Lite-Write/Read-Transactions RVALID are deasserted
 AXI4-Lite Protocol: Read Transaction Timing Diagram
Slave asserts
Master puts addr on ARREADY to indicate
Read Addr Channel it is ready to receive
addr on the bys
User-side transaction with error code
Master asserts
ARVALID to indicate
addr is valid

Master asserts
RREAD to indicate it is Slave asserts RVALID
Since both ARVALID and Slave puts requested
ready to receive data to indicate data is valid
ARREADY are asserted, data on the Read Data
from Slave handshake occurs at the next CLK channel
rising edge; after that ARVALID
and ARREADY are deasserted
Since both ARVALID and
ARREADY are asserted, the next
CLK rising edge completes the
transaction and RREADY &
Source: https://docs.amd.com/r/en-US/pg165-cmac/User-Side-AXI4-Lite-Write/Read-Transactions RVALID are deasserted
AXI4-Lite Protocol: Write Transaction Sequence
• Master device (e.g. a CPU) initiates write transaction, Slave device responds to the request
• Write transaction sequence can be divided into (i) address phase, (ii) data phase, and (iii) response
phase
• Write transaction is realized over three separate channels: write address, write data, write response
• Address phase:
• Master sends write address (AWADDR) and control signals (AWVALID, AWPROT) to the Slave
• Slave acknowledges the address with AWREADY
• Data phase:
• Master sends write data (WDATA) and strobe signal (WSTRB) to the Slave
• Slave acknowledges the data with WREADY
• Response phase:
• Slave sends write reponse (BVALID, BRESP) to the Master
• Master acknowledges the response with BREADY
 AXI4-Lite Protocol: Write Transaction Timing Diagram
Slave asserts Since both AWVALID and
AWREADY to Write AWREADY are asserted,
Master puts addr on Addr Channel handshake occurs, transaction
Write Addr Channel begins at the rising edge and
AWVALID and AWREADY are
deassered a the next rising edge
Master validated addr
by asserting AWVALID

Master puts data on

Write Data Channel

Master validated data

by asserting WVALID

Since both WVALID and WREADY Tramsactopm is completed with

Slave asserts Slave asserts BVALID to indicate
are asserted, handshake occurs, both BLAVID and BREADY being
WREADY to Write valid response on Write Response
transaction begins at the rising HIGH on the next rising edge
Data Channel Channel (respons is 2’b00 =
edge and WVALID and WREADY OKAY)
are deassered

Source: https://docs.amd.com/r/en-US/pg165-cmac/User-Side-AXI4-Lite-Write/Read-Transactions