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Spring-2021 (1)

EEE411 Quiz 3

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2 views

Spring-2021 (1)

EEE411 Quiz 3

Uploaded by

Little Wizard
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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North South University

Department of Electrical and Computer Engineering


Midterm Quiz: EEE411/CSE435/ETE412 - Section 2: VLSI Design, Date: Apr `12, 2021

Answer any 3:

1. (a) In Brief – any 3 (Formulae & figure where necessary) - i. Line Resistance and Sheet Resistance, ii.
Line Capacitance and Permittivity (iii) Resistively and conductivity (iv) Silicon patterning for series-
connected nFETs and p FETS with Schematic, Surface Pattern, Side View.
(b) Design the circuits and layouts for a CMOS gate that implements the function

g = a.b+c
Start with truth table and then using conventional procedure(s) come up with optimized nFET and
pFET ckt.

2. (a) What are OAI and AOI function? Design a CMOS circuit for the following function with OAI/AOI
structure:
g = ab + cd + ef
(c) Design 4-to-1 MUX using TGs.

3. a) List the masking sequences which are used to define chip regions.
b) Show the cross section and layout view pFET which includes four masks: pSelect,
Active, nWell and Polly. Mention the design rules of nWell and Active.

4. (a) In Brief: (i) DRC and ERC, (ii) Manhattan Rule, (iii) Latch-up Condition and it’s prevention. (iv)
Drawn value and Effective Value. (v) Channel length, width and Aspect Ratio
b) Show the circuit and layout of a NAND3 gate using vertical FETs where series nFETS are 2X
wider than parallel pFETS.

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