3 - Combinational Logic Circuits

3.1 SOP and POS representation, K-Map up to four

3.2 Arithmetic Circuits: Half adder, Full adder, Half

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 Canonical SOP Form

• Y=AB(C+C’)+(A+A’)BC+A(B+B’)C’
• Y=ABC+ABC’+ABC+A’BC+ABC’+AB
’C’
• Each term is called minterm
•

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 Reduced and Canonical SOP Form
• A+B)(A+C)-POS
(

• -->A.A+A.C+B.A+B.C

• -->A+A.C+A.B+B.C

• -->A(1+C+B)+B.C

• A+BC-Reduced Form SOP

• canonical

• A(B+B')(C+C')+B(A+A')C

• AB(C+C')+AB'(C+C')+BAC+BA'C

• ABC+ABC'+AB'C+AB'C'+BAC+BA'C-Cannonical Form SOP

Y=(A+BC)(B+C'A)
USE: A+BC=(A+B)(A+C)
B+C’A=(B+C’)(B+A)
Y=(A+B)(A+C)(B+C’)(B+A)

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Conversion to CANNOICAL POS form
Y=(A+BC)(B+C'A)
USE: A+BC=(A+B)(A+C)
Y=(A+B+CC’)(A+BB’+C)(AA’+B+
C’)(A+B+CC’)
Y=(A+B+C)(A+B+C’)

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Y = F(A,B,C)=A′BC+A′BC′+AB′C′+AB′C

F(A,B,C)=A′BC+A′BC′+AB′C′+AB′C
A'B(C+C') + AB'(C'+C)
A'B(1)+AB'(1)
A'B+AB'

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 3 - Combinational Logic Circuits
3.3 Multiplexer and De-Multiplexer: Multiplexer
operations, cascading of Multiplexer, Boolean
function implementation using MUX, DEMUX and
basic gates, Encoder and Decoder.
(4 hours)

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 3 - Combinational Logic Circuits
3.1 SOP and POS representation, K-Map up to four
variables and Quine-Mc Clusky method for
minimization of logic expressions.
Books referred:
1. John F. Warkerly, “Digital Design Principles and
Practices”, Pearson Education, Fifth Edition
(2018).
2. R. P. Jain, “Modern Digital Electronics”, Tata
McGraw Hill Education, Forth Edition (2010).
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 Standard Representations of Logic
Functions
Nomenclature and notation for Combinational Logic
circuits.
The most basic representation of a logic function is the
truth table. This brute-force representation simply lists
the output of the circuit for every possible input
combination. Traditionally, the input combinations are
arranged in rows in ascending binary counting order,
and the corresponding output values are written in a
column next to the rows.
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 Truth Table
The general structure of a 3-variable truth table is
shown. The rows are numbered 0–7 corresponding to
the binary input combinations, but this numbering is
not an essential part of the truth table.

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 General truth table structure for a
3-variable logic function, F(X,Y,Z)

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 Truth Table
The truth table for a particular 3-variable logic
function is shown on next slide. Each distinct pattern
of 0s and 1s in the output column yields a different
logic function; there are 28 such patterns. Thus, the
logic function in this table is one of 28 different logic
functions of three variables. The truth table for an
n-variable logic function has 2n rows. Obviously, truth
tables are practical to write only for logic functions
with a small number of variables.
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Truth table for a particular 3-variable
logic function, F(X,Y,Z)

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 Some Definitions
The information contained in a truth table can also be
conveyed algebraically.
To do so, we first need some definitions:
• A literal is a variable or the complement of a
variable.
Examples: X, Y, X′,Y′.
• A product term is a single literal or a logical product
of two or more literals.
Examples: Z′, W·X·Y, X·Y′·Z, W′·Y′·Z.
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 Some Definitions
• A sum-of-products expression is a logical sum of
product terms. Example:
Z′ + W · X · Y + X · Y′ · Z + W′ · Y′ · Z.
• A sum term is a single literal or a logical sum of two
or more literals.
Examples: Z′, W + X + Y, X + Y′ + Z, W′ + Y′ + Z.
• A product-of-sums expression is a logical product of
sum terms. Example:
Z′ · (W + X + Y) · (X + Y′ + Z) · (W′ + Y′ + Z).
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 Some Definitions
• A normal term is a product or sum term in which no
variable appears more than once. A non-normal term
can always be simplified to a constant or a normal
term using one of theorems T3, T3′, T5, or T5′.
Examples of non-normal terms: W · X · X · Y′, W +
W + X′ + Y, X · X′ · Y.
Examples of normal terms: W · X · Y′, W + X′ + Y.

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 Some Definitions
• An n-variable minterm is a normal product term with
n literals. There are 2n such product terms. Examples
of 4-variable minterms:
W′ · X′ · Y′ · Z′, W · X · Y′ · Z, W′ · X′ · Y · Z′.
• An n-variable maxterm is a normal sum term with n
literals. There are 2n such sum terms. Examples of
4-variable maxterms: W′ + X′ + Y′ + Z′, W + X′ + Y′
+ Z, W′ + X′ + Y + Z′.

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 Some Definitions
There is a close correspondence between the truth
table and minterms and maxterms. A minterm can be
defined as a product term that is 1 in exactly one row
of the truth table. Similarly, a maxterm can be defined
as a sum term that is
0 in exactly one row of the truth table. Table on next
slide shows this correspondence for a 3-variable truth
table.

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 Minterms and Maxterms for a
3-variable logic function, F(X,Y,Z)

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 Minterm (mi) and Maxterm (Mi)
An n-variable minterm can be represented by an n-bit
integer, the minterm number. We’ll use the name minterm i
to denote the minterm corresponding to row i of the truth
table. In minterm i, represented as mi , a particular variable
appears complemented if the corresponding bit in the
binary representation of i is 0; otherwise, it is
uncomplemented. For example, row 5 has binary
representation 101 and the corresponding minterm, (m5) is
X · Y′ · Z. As you might expect, the correspondence for
maxterms is just the opposite: in maxterm i, represented as
Mi , a variable appears complemented if the corresponding
bit in the binary representation of i is 1. Thus, maxterm 5
(101), M5 is X′ + Y + Z′.

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 Canonical Sum
Based on the correspondence between the truth table
and minterms, we can easily create an algebraic
representation of a logic function from its truth table.
The canonical sum of a logic function is a sum of the
minterms corresponding to truth-table rows (input
combinations) for which the function produces a 1
output. For example, the canonical sum for the logic
function in Table on next slide

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Canonical Sum

F = X′ · Y ′ · Z ′
+X′·Y ·Z
+X·Y′·Z′
+X·Y·Z′
+ X · Y · Z·

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 Canonical Sum
Here, the notation ∑X,Y,Z(0,3,4,6,7) is a minterm list
and means “the sum of minterms 0, 3, 4, 6, and 7 with
variables X, Y, and Z.” The minterm list is also known
as the on-set for the logic function. You can visualize
that each minterm “turns on” the output for exactly
one input combination. Any logic function can be
written as a canonical sum.

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 Canonical Product
The canonical product of a logic function is a product
of the maxterms corresponding to input combinations
for which the function produces a 0 output. For
example, the canonical product for the logic function
in Table is

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Canonical Product

F = (X + Y + Z ′)
· (X + Y ′ + Z )
· (X ′ + Y + Z ′)

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 Canonical Product
Here, the notation ∏X,Y,Z(1,2,5) is a maxterm list and
means “the product of maxterms 1, 2, and 5 with
variables X, Y, and Z.” The maxterm list is also
known as the off-set for the logic function. You can
visualize that each maxterm “turns off” the output for
exactly one input combination. Any logic function can
be
written as a canonical product.

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 Minterm and Maxterm list
It’s easy to convert between a minterm list and a
maxterm list. For a function of n variables, the
possible minterm and maxterm numbers are in the
set{0, 1, … , 2n - 1}; a minterm or maxterm list
contains a subset of these numbers. To switch between
list types, take the set complement, for example,
∑X,Y,Z(0,3,4,6,7) = ∏X,Y,Z(1,2,5)
∑X,Y (1) = ∏X,Y(0,2,3)
∑W,X,Y,Z(0,1,2,3,5,7,11,13) =
∏W,X,Y,Z(4,6,8,9,10,12,14,15)
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 Possible Representations
We have now learned five possible representations for a
combinational logic function:
1. A truth table.
2. An algebraic sum of minterms, the canonical sum.
3. A minterm list using the ∑ notation.
4. An algebraic product of maxterms, the canonical
product.
5. A maxterm list using the ∏ notation.
Each one of these representations specifies exactly the
same information; given any one of them, we can derive
the other four using a simple mechanical process.
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 Combinational Logic Design
Boolean algebra theorems are used for the
manipulations of logic expressions. The number of
gates and the number of input terminals for the gates
required for the realisation of a logic expression, in
general, get reduced considerably if the expression can
be simplified (minimized). The simplification of logic
expression is very important as it saves the hardware
required to design a specific system.

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 Combinational Logic Design
The following methods can be used to simplify the
Boolean functions:
1. Algebraic method,
2. Karnaugh-map technique
3. Quine-McCluskey method

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 Standard Representations
Any arbitrary logic function can be expressed in the
following forms:
1. Sum-of-products form (SOP) and
2. Product -of -sums form (POS)
This does not mean that the logic function cannot be
written in any other form. It can be written in different
forms but the above two forms are conveniently suited
in arriving at the standard methods for designing the
circuits.

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 Combinational Logic Design
Basically digital circuits are divided into two broad
categories: 1. Combinational and 2. Sequential
In combinational circuits, the outputs at any instant of
time depend upon the inputs present at that instant of
time. This means there is no memory in these circuits.
There are other types of circuits in which the outputs
at any instant of time depend upon the present inputs
as well as past inputs/outputs. This means that there
are elements used to store past information. These
elements are known as memory. Such circuits are
known as Sequential circuits.
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 Combinational Logic Design
Given the logic equation Y = (A+BC)·(B+C′A)
a) Design a circuit using gates to realise this function.
b) Find out whether it is possible to design the circuit
with only one type of gates (NAND or NOR). If
yes, design the circuits.
c) Find out whether it is possible to simplify this
equation. If yes, simplify it.
d) Now design the circuit using the simplified
expression obtained in part (c).

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 Combinational Logic Design
e) Compare the circuits obtained in parts (a), (b) and
(d) from the point of view of number of gates,
number of inputs for the gates, types of gates, and
propagation delay.

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 Y = (A+BC)·(B+C′A)
Assuming that the signals corresponding to each
literal is available, i.e. the variables are available in
their uncomplemented and complemented form.
The first term (A) has only one literal A and the
second term (BC) has two literals B and C. The second
term is recognised as an AND operation and can be
realised by using a 2-input AND gate. The
combination of these two terms is realized by using a
2-input OR gate. The complete realization of the first
two terms is shown in figure on next slide.
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Y = (A+BC)·(B+C′A)

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 Y = (A+BC)·(B+C′A)
The third term (B) has only one literal B and the fourth
term (C′A) has two literals B and C. The fourth term is
recognised as an AND operation and can be realised
by using a 2-input AND gate. The combination of
these two terms is realized by using a 2-input OR gate.
The complete realization of these two terms is shown
in figure on next slide.

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Y = (A+BC)·(B+C′A)

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 Y = (A+BC)·(B+C′A)
Now, the complete realization is obtained by using a
2-input AND gate with Y1 and Y2 as the inputs and the
output of this gate will be the required output Y. This
realisation is given in Figure below. The above design
requires three 2-input AND gates and two 2-input OR
gates.

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 Y= AB + AC′ + BC
(b) (i) Sum-of-Products form
The given equation Y = (A+BC)·(B+C′A)
may be written as
Y = (A)·(B+C′A) + (BC)·(B+C′A) by (T8)
Y = AB+AC′A+BCB+BCC′A
Where AC′A = (AA)C′ = AC′, BCB = (BB)C = BC by
(T3′)
and BCC′A = B(CC′)A = B(0)A = 0 by (T5′) and (T2′)
Y= AB + AC′ + BC
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 Y= AB + AC′ + BC
This representation is known as Sum-of-Products
form. This can be realised by using AND–OR
configuration as shown in Figure on next slide. It is a
two-level realisation. The first level consists of AND
gates and the second level consists of the OR gate.

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Y= AB + AC′ + BC

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 Y= AB + AC′ + BC
By making use of De Morgan’s theorem the equation
Y= AB + AC′ + BC may be rewritten as
Y′= (AB + AC′ + BC)′ = (AB)′ · (AC′)′ · (BC)′
Y = (Y1 ·Y2 ·Y3)′
Where
Y1 = (AB)′ , Y2 = (AC′)′, Y3 = (BC)′
This can be realized using NAND gates only as shown
on next slide. This is also a two-level realisation where
only NAND gates are used. SOP form can be designed
using only one type of gates (NAND).
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Y = (Y1 ·Y2 ·Y3)′

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 Y = (A+B)·(A+C)·(B+C′)
(b) (ii) Product-of-sums form
The given equation Y = (A+BC)·(B+C′A)
may be written as
Y = (A+B)·(A+C)·(B+C′)·(B+A) by (T8′)
Where (A+B)·(B+A) = (A+B) by (T6) and (T3′)
Y = (A+B)·(A+C)·(B+C′)
It is known as Product-of-Sums form. This can be realised
by using OR–AND configuration as shown in Figure on
next slide. It is a two-level realisation. The first level
consists of OR gates and the second of the AND gate.
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Y = (A+B)·(A+C)·(B+C′)

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 Y = (A+B)·(A+C)·(B+C′)
By making use of De Morgan’s theorem the equation
Y = (A+B)·(A+C)·(B+C′)
may be rewritten as
Y′= ((A+B)·(A+C)·(B+C′))′ = (A+B)′ + (A+C)′ +
(B+C′)′
Y = (YA + YB + YC)′
Where , YA = (A+B)′ , YB = (A+C)′, YC = (B+C′)′
This can be realized using NOR gates only as shown
on next slide. This is also a two-level realisation where
only NOR gates are used. POS form can be designed
using only one type of gates (NOR).
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Y = (YA + YB + YC)′

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 Y= AC′ + BC, Y= (A+C)·(B+C′)
(c) It is possible to simplify the SOP form
Y= AB + AC′ + BC
It may be written as
Y= AC′ + BC by (T11)
Similarly it is possible to simplify the POS form
Y = (A+B)·(A+C)·(B+C′)
It may be written as
Y= (A+C)·(B+C′) by (T11′)

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 Y= AC′ + BC
(d) Circuit design using simplified expressions in (c)
using NAND gates only.

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 Y= (A+C)·(B+C′)
(d) Circuit design using simplified expressions in (c)
using NOR gates only.

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 Y = (A+BC)·(B+C′A)
e) Compare the circuits obtained in parts (a), (b) and
(d) from the point of view of number of gates,
number of inputs for the gates, types of gates, and
propagation delay.
The gate requirements corresponding to parts (a), (b),
and (d) are given in Table. The realisation of part (a)
needs maximum number of gates and types of gates. It
is a three level realisation which increases the
propagation delay.

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 Y = (A+BC)·(B+C′A)

Part (b)
Part (a) AND–OR / OR–AND / Part (d)
NAND–NAND NOR–NOR
3, 2-i/p AND 3, 2-i/p AND 3, 2-i/p OR 3, 2-i/p
2, 2-i/p OR 1, 3-i/p OR 1, 3-i/p AND NAND
3, 2-i/p NAND 3, 2-i/p NOR 3, 2-i/p
1, 3-i/p NAND 1, 3-i/p NOR NOR

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 Y = (A+BC)·(B+C′A)
Realisations corresponding to (b) and (d) are very
useful since only one type of gates (NAND/NOR) are
required which is very convenient to use when we use
ICs because a number of similar gates are available in
the same package. Realisation corresponding to part
(d) requires minimum number of gates. Therefore , the
simplification of logic expressions is very useful.

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 Canonical forms
We notice that in the SOP form Y= AB + AC′ + BC
and the POS form Y = (A+B)·(A+C)·(B+C′), all the
individual terms do not involve all the three literals. If
each term in SOP and POS forms contains all the
literals then these are known as canonical SOP and
POS, respectively. Each individual term in canonical
SOP form is called as minterm and in canonical POS
form as maxterm. The usefulness of the minterm and
maxterm representations will become clear from the
discussion which follows.
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 Canonical SOP
SOP form can be converted to canonical SOP by
ANDing the terms in the expression with terms formed
by ORing the variable and its complement which are
not present in that term. For example for a three
variable expression with variables A, B, and C, if there
is a term A, where B and C variables are missing, then
we form two terms (B+B′) and (C+C′) and AND them
with A. Therefore we get A · (B+B′) · (C+C′)
= ABC+AB′C+ABC′+AB′C′

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 Canonical SOP
The SOP form Y= AB + AC′ + BC is converted to
canonical SOP as follows:
Y= AB(C+C′) + AC′(B+B′) + BC(A+A′)
= ABC + ABC′ + ABC′ + AB′C′ + ABC + A′BC
= ABC + ABC′ + AB′C′ + A′BC
Similarly the SOP form Y= AC′ + BC is converted to
canonical SOP as follows:
Y= AC′(B+B′) + BC(A+A′)
= ABC′ + AB′C′ + ABC + A′BC
= ABC + ABC′ + AB′C′ + A′BC 60/56
 Canonical SOP
The minterms associated with the canonical SOP
Y= ABC + ABC′ + AB′C′ + A′BC are
m(111), m(110), m(100), m(011)
m7, m6, m4, m3
Y = ∑A,B,C(3,4,6,7)

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 Canonical POS
Similarly POS form can be converted to canonical
POS by ORing the terms in the expression with terms
formed by ANDing the variable and its complement
which are not present in that term. For example for a
three variable expression with variables A, B, and C, if
there is a term A, where B and C variables are missing,
then we form two terms (B·B′) and (C·C′) and OR
them with A. Therefore we get A + (B·B′) + (C·C′)
= (A+B+C) · (A+B′+C) · (A+B+C′) · (A+B′+C′)

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 Canonical POS
The POS form Y = (A+B)·(A+C)·(B+C′) is converted
to canonical POS as follows:
Y= (A+B)+(C·C′) · (A+C)+(B·B′) · (B+C′)+(A·A′)
= (A+B+C)·(A+B+C′)·(A+B+C)·(A+B′+C)·(A+B+C′)
· (A′+B+C′)
= (A+B+C) · (A+B+C′) · (A+B′+C) · (A′+B+C′)
Similarly the POS form Y= (A+C)·(B+C′) is
converted to canonical POS as follows:
Y= (A+C)+(B · B′) · (B+C′)+(A · A′)
= (A+B+C)·(A+B′+C)·(A+B+C′)·(A′+B+C′)
= (A+B+C)·(A+B+C′)·(A+B′+C)·(A′+B+C′) 63/56
 Canonical POS
The maxterms associated with the canonical POS
Y= (A+B+C) · (A+B+C′) · (A+B′+C) · (A′+B+C′)
are
M(000), M(001), M(010), M(101)
M0, M1, M2, M5
Y = ∏A,B,C(0,1,2,5)

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