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HW3

This document outlines a homework assignment for digital logic design, involving various tasks related to flip-flops, counters, and timing diagrams. Students are required to analyze circuits, determine sequences, and design counters using J-K flip-flops and other components. The assignment includes specific questions about counter behavior, state transitions, and design requirements for synchronous counters.

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4 views

HW3

This document outlines a homework assignment for digital logic design, involving various tasks related to flip-flops, counters, and timing diagrams. Students are required to analyze circuits, determine sequences, and design counters using J-K flip-flops and other components. The assignment includes specific questions about counter behavior, state transitions, and design requirements for synchronous counters.

Uploaded by

margate2044
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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DLD Homework 3

Term I – 2024
Student 1’s Name: Lê Tuyết Nhung Student 1’s ID ITITWE22130
Student 2’s Name: Trần Khánh Duy Student 2’s ID ITITWE22132
Student 3’s Name: Trần Võ Thế Vinh Student 3’s ID ITITWE22124

1. The waveforms shown in the following Figure are to be applied to negative-edge-triggered J-K
FF:

Draw the Q waveform response for each of this FF, assuming that Q = 0 initially.

2. In the following circuit, inputs A, B, and C are all initially LOW. Output Y is supposed to go
HIGH only when A, B, and C go HIGH in a certain sequence.
a) Determine the sequence that will make Y go HIGH.
b) Explain why the START pulse is needed.
c) Modify this circuit to use D FFs.

a. When k = 0, Y should be 1
Y can go HIGH only when C goes HIGH while X is already HIGH. X can go
HIGH only if B goes HIGH while A is HIGH. Thus, the correct sequence that
makes Y go HIGH is A, B, C.
b. The start pulse is reset the flops before working on them.
c. We know Qn+1 = JQ’ + K’Q here K = 0
= JQ’ + 0’Q = JQ’ + Q = ( Q+Q’)(Q+J) = J + Q

3. Refer to the following counter circuit and answer the following:


a) If the counter starts at 000, what will be the count after 13 clock pulses? After 99
pulses? After 256 pulses?
b) If the counter starts at 100, what will be the count after 13 pulses? After 99 pulses?
After 256 pulses?
c) Connect a fourth J-K FF (X3) to this counter and draw the state transition diagram for
this 4-bit counter. If the input clock frequency is 80 MHz, what will the waveform at
X3 look like?
Answer:
A. For counter start at 000:
After 13 pulses, the counter will go through 8+5 state changes. So, after 13 pulses
the counter will be at 101 state. Therefore, the counter after 13 cycle is 5.
After 99 pulses, the counter will go through 96+3 state changes. So, after 99 pulses
the counter will be at 011 state. Therefore, the counter after 99 cycle is 3.
After 256 pulses, the counter will go through 256+0 state changes. So, after 256
pulses the counter will be at 000 state. Therefore, the counter after 256 cycle is 0.

B. For counter start at 100:


• After 13 clock pulses:
Binary counter starting at 100 (4 in decimal).
After 13 pulses: 0100+11010100+1101 (13 in binary) = 1000110001.
Since it's a 3-bit counter, we only consider the last 3 bits: 001001.
Count after 13 pulses: 001 (1 in decimal).
• After 99 clock pulses:
Binary counter starting at 100 (4 in decimal).
After 99 pulses: 0100+11000110100+1100011 (99 in binary) = 11001111100111.
Since it's a 3-bit counter, we only consider the last 3 bits: 111111.
Count after 99 pulses: 111 (7 in decimal).
• After 256 clock pulses:
Binary counter starting at 100 (4 in decimal).
After 256 pulses: 0100+1000000000100+100000000 (256 in binary).
Since it's a 3-bit counter, we only consider the last 3 bits: 100100.
Count after 256 pulses: 100 (4 in decimal).
C.

- After connecting 4 JK flipflops the circuit become MOD 24 = MOD 16 counter


0000
1110 0001

1101 0100

1100 0011

1011 0100

1010 0101

1001 0110

1000 0111

- If the input frequency is 80 MHz => the X3 frequency is 80/16 = 5 MHz

4. Draw the circuit diagram for a MOD-32 synchronous up-counter.


5. Draw a synchronous, MOD-32, down counter.

6. Complete the timing diagram in the following figure for a 74ALS161 with the indicated input
waveforms applied. Assume the initial state is 0000.
7. Complete the timing diagram in the following figure for a 74ALS190 with the indicated
input waveforms applied. The DCBA input is 0101
8. Refer to the IC counter circuit in the following figure:

a) Draw the state transition diagram for the counter’s QD QC QB QA outputs.


b) Determine the counter’s modulus.
c) What is the relationship of the output frequency of the MSB to the input CLK
frequency?
9. Refer to the IC counter circuit in the following figure.

a) Draw the timing diagram for outputs QD QC QB QA.


b) What is the counter’s modulus?
c) What is the count sequence? Does it count up or down?
d) Can we produce the same modulus with a 74HC190? Can we produce the same count
sequence with a 74HC190?

10. Analyze the synchronous counter in the following figure. Draw its timing diagram and determine
the counter’s modulus.
11. Design a synchronous counter:
a) Design a synchronous counter using J-K FFs that has the following sequence: 000,
010, 101, 110, and repeat. The undesired (unused) states 001, 011, 100, and 111 must
always go to 000 on the next clock pulse.
b) Redesign the counter of part (a) without any requirement on the unused states; that is,
their NEXT states can be don’t cares. Compare with the design from (a).
12. Draw a schematic to create a recycling, MOD-5 counter that produces the count sequence:
a) 1, 2, 4, 5, 6, and repeats with a 74ALS162
b) 5, 4, 2, 1, 0, and repeats with a 74ALS190
13. Design a MOD-100, BCD counter using either two 74HC160 or two 74HC162 chips and any
necessary gates. The IC counter chips are to be synchronously cascaded together to produce the
BCD count sequence for 0 to 99. The MOD-100 is to have two control inputs, an active-HIGH
count enable (EN) and an active-HIGH, synchronous load (LD). Label the counter outputs Q0,
Q1, Q2, etc., with Q0 = LSB. Which set of outputs represents the 10s digit?

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