634 IEEE JOURNAL OF SOLID-STATE CIRCUITS,VOL.

SC-16,NO, 6,DECEMBER 1981

A 4-Terminal Wide-Band Monolithic Amplifier

ROBERT G. MEYER, FELLOW, IEEE, AND ROBERT A. BLAUSCHILD, MEMBER,IEEE

RO = 500
Abstract-A bipolar monolithic amplifier is described which achieves

+
18 dB gain, 725 MHz-3 dB bandwidth and 4.4 dB noise figure. The
circuit is housed in a 4-lead TO-46 package, consumes 180 mW of dc -F-l
power and requires no external components. Input and output imped-
ances are matched to 50 Q with VSWR less than 1.5 across the band.
A high-power vemion of the circuit consumes 1 W of dc power and gives
152 mW of output power at 200 MHz.
Ri = 500
—

1
J
‘LI
5orr

& RL V.

l--
=

v I 2rl ‘E2

I. INTRODUCTION ‘FI
>

w
=
IDE-BAND amplifiers are used in a variety of modern 140a

electronic systems. In communication receivers, for 12fl

‘El
example, there are applications for wide-band amplifiers with
matched terminal impedances, broad-band gain, and good noise
performance operating from low frequencies to 550 MHz. In
instrumentation circuits, wide-band amplifiers in this frequency 2000”
range are used for buffering and driving other circuits such as VO : RF, + RE1
balanced mixers. This need is currently supplied by relatively
V. - 2 RE1
expensive hybrid circuits.
In this paper, a new monolithic circuit is described which Fig. 1. Simplitled ac circuit schematic.
gives 18 dB gain from dc to 725 MHz with input and output
impedances matched to 50 fl Other monolithic circuits have base resistance of QI should be minimized and resistor RF2
previously been described which achieve similar terminal speci- should be maximized. The resistor values also influence circui~
fications [1] - [3], but these circuits had several drawbacks gain and bias conditions, and compromise values OfRE1 =12 fl
which limited their application. Some of these limitations were and RF2 = 200 Q were used in the low-power circuit. A well-
relatively high noise figures (9-1 8 dB), the need for external specified, low value of RE1 is achieved by use of a resistor
components (such as transformers), and the use of packages geometry with a width of 40 ~m and a length of 4 Mm. In
with large lead inductances which introduced high-frequency order to reduce base resistance, input device Q1 has the largest
deviations from the desired terminal characteristics. The area of the active devices and is fabricated with two 50 X 2 ~m
amplifier described here requires only four connections– base stripes. These measures allowed a narrow-band noise
input, output, power supply, and ground. R is contained in a figure of 4.4 dB to be realized at 500 MHz with abase resistance
4-lead TO-46 can and achieves a noise figure of 4.4 dB. A of40Qin Q1.
high-power version of the circuit is contained in a TO -39 can, In order to achieve good high-frequency performance in an
consumes 1 W of dc power, and gives 152 mW of output power inexpensive package, the low-power circuit was designed for
at 200 MHz. operation in a 4-lead TO-46 can with no external components.
This results in a difficult biasing problem for a single-ended
II. CIRCUIT DESIGN feedback circuit of this topology. A further complication is
A simplified ac circuit schematic is shown in Fig. 1. The de- the need for low noise figure, which precludes use of Zener
sign is based on the use of multiple feedback loops [1] to give diode level shifts. A complete circuit schematic of the low-
broad-band gain together with good noise figure and good power amplifier is shown in Fig. 2, where level-shifting is
terminal impedance matches. The circuit gain is set principally achieved by emitter follower QB and diode Qa which feed
by the ratio (l?Fl + RE1 )/l?El, representing series-shunt feed- shunt feedback to the input emitter via RF1. The use of an
back. Shunt-series feedback due to RF2 and RE2 aids in emitter follower buffer in this feedback loop essentially elimi-
producing broad-band terminal impedances without the need nates problems of shunt feedback loading on the output.
for low value input shunting resistors which would degrade the The value of RF1 = 140 Q is chosen to give nominal gain
noise figure. For optimum noise performance, RE1 and the S21 = 18 dB. The dc output voltage V. can be found from
V. = Vcc - (Icz + 1C6) Rz, and for Vcc = 6 V this is chosen
Manuscript received May 20, 1981; revised July 1, 1981. to 3.2 V to give approximately equal positive and negative out-
R. G. Meyer is with the Department of Electricrd Engineering and put swings. This requires 10 mA of bias current in Q3. Diode
Computer Sciences, University of California, Berkeley, CA 94720.
R. A. Blauschild is with the Signetics Corporation, Sunnyvale, CA
Q5 is included for bias purposes to rdlow direct coupling of
94086. RF2 to the base of QI. Diodes Qq and Q5 must be carefully

001 8-9200/8 1/ 1200-0634$00.75 01981 IEEE

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MEYER AND BLAUSCHILDI:4-TERMINAL AMPLIFIER 635

Vcc = +6V

T~
r
RO L2
‘JO
i 10 3nH
Q2
33
40

L Q4

p._3
d
RE2
hFl
12
140

REI Q5
+ 12
~

VO(dc) ❑ : Vcc ‘(~z + ICIj)RZ

Fig. 2. Compiete low-power amplifier schematic.

designed to minimize collector series resistance and avoid satura-

tion since this would sericusly degrade the high-frequency ac
characteristics of the amplifier. The dual feedback loops
stabilize the dc operating point of the amplifier, and the design
equations for bias conditions in the circuit are derived in the Fig. 3. Low-power amplifier die photograph.
Appendix.
The output stage of the amplifier is realized as a Darlingtofi
pair, Q6 - Q2. This has two beneficial effects. First, the dc RL
bias voltage on the input ~stageQI is increased to a more de-
sirable value. Secondly, thle Darlington increases the feedback =

loop gain and facilitates Miller compensation of the circuit via =

4 b
RF1
capacitor Cl. A compensation capacitor of C’l = 1 pF together () w

with the process fT= 5 GHz yields a -3 dB frequency of 725 RE2

RE1
MHz with a high-frequency peak of about 0.7 dB.
Resistor R. pads the output and raises the output resistance RF2

to its nominal value of 50 S2. Inductors L ~ and Lz are bond- m

I 1
wire and lead inductance which are of the order of 3 nH. These >
inductors improve the highfrequency

capacitance.
matches at input and
output by partially resonating with 0.5 pF of pad and package L
=
L(3nH)

(a)

T 1
HI. LAYOUT AND PACKAGING
The low-power circuit active die size is 18 X 17 roils and a
die photograph is shown in Fig. 3. The input and output pads
on the left are minimum size at 2.5 milsz in order to reduce
-+1 Q2

=
RL

F
e RF1
parasitic capacitance. The upper pad is the input lead con-

E
nected to device Q1, which is the largest of the active devices.
REI RE2
The lower pad is the output connection with the 10$2 resistor
in series with the Darlingtom common collector. The compen- L(lnH)
sation capacitor is also lc)cated in the Darlington isolation
region. The supply voltage pad is shown at the bottom of the
die.
!i
n
L(l nH)

RF2 I
n

In the die photograph of Fig. 3 two large, separate grounds (b)

can be seen on the top right of the die. The need for two ground Fig. 4. Effect of ground lead inductance. (a) Common ground. (b)
pads can be seen by referring to the simplified schematics of Separate grounds.
Fig. 4 which illustrate the effect of common ground lead induc-
tance. In Fig. 4(a) the schematic is shown which results when ing 1 GHz this represents significant feedback coupling from
input and output stages have a common ground on the chip and output to input and has a degrading effect on circuit gain and
this is bonded to the package ground. A common lead induc- terminal impedances. This problem is solved as shown in Fig.
tance of as much as 3 nH can result. At frequencies approach- 4(b) by providing separate ground pads for input and output
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636 IEEE JOURNAL OF SOLID-STATE CIRCUITS,VOL. SC-16,NO. 6,DECEMBER 1981

24

22

20
g
-.
gN 18
g
~
16

14

12

10 20 50 00 200 E@o
FREQI !NCYMHz
Fig. 6. Low-power amplifier frequency response.

TABLE I
LOW-POWER
CIRCUITPERFORMANCE
OVERTEMPERATURE

Quantity -55°C 27°C 125°C

Total bias current (mA) 32.0 30.2 28.4

vo(dc) V 3.3 3.2 3.1
IQz mA 8.0 8.4 8.8
IQ6 mA 7.1 5.4 3.8
IQ% mA 5.5 5.4 5.4
Power gain
S21 (100 MHz) dB 18.1 18.0 17.9
Szl (700 MHz) dB 16.1 15,7 12.7
Fig. 5. Low-power amplifier header photograph.

stages and bonding each pad to the TO-46 header with triple TABLE 11
bond wires. The :resulting inductors of about 1 nH in each lead MEASURED S PARAMETERS FORTHELOW-POWER
CIRCUIT
have a negligible. effect on the circuit performance. This imple-
F(MHz) Sll (dB) S 12(dB) S21 (dB) SZ (dB)
mentation is further illustrated in Fig. 5, which is a photograph
of the low-power chip bonded in the TO-46 header. The ad- 50 -27.8 79° -27.4 0 18.0 5° -16.4 33°
vantages of the T() -46 package for this application are apparent 300 -21.3 159° -28.9 6;0 18.5 23° -13.1 106°
in the close proximity of input and output posts to the die, and 550 -15.0 176° -33,8 130° 17.8 38° -12.6 155°
700 -1S.2 178° -37.2 -153° 15.6 48° -15.0 160°
the use of the TO-46 header itself as a low-inductance ground
plane. The fourth (ground) lead is not visible in this top view.
most of the bias currents and voltages vary by only 10 percent
IV. MONOLITHIC PROCESS or less as temperature varies from - 55°C to 125”C. The ex-
The performance of the circuit is directly dependent on the ception is the Darlington driver Q6, whose current varies by a
characteristics of the IC process used for fabrication. This factor of two due to VBE variation in Qz. However, Qb is
circuit is fabricated using an ion-implanted high-frequency biased with a sufficiently high collector current to ensure that
junction-isolated monolithic process with peak ~T = 5 GHz. this variation has a negligible effect on circuit performance.
Collector and base resistance are minimized using deep n+ and Also shown in Table I is the power gain Szl, which varies only
p+ contacts and minimum feature size is 2 pm. 0.2 dB at 100 MHz due to the stabilizing effect of the feedback
loop gain. At the top of the band (700 MHz) the gain variation
V. MEASUREMENTS is 2.4 dB over temperature due to the much reduced feedback
A number of samples of the low-power amplifier have been loop gain at this frequency. The high-frequency S parameters
extensively chamcterized and performance has been found to of the circuit as a function of frequency are listed in detail in
agree well with computer simulations based on comprehensive Table II. The overall circuit specifications are summarized in
device models. As shown in Fig. 6, the measured gain versus Table HI where the large-signal characteristics at 100 MHz are
frequency response is essentially flat and equal to 18 dB up to specified via the 1 dB gain compression point, saturated output
200 MHz. A gain peak of 0.7 dB occurs at 400 MHz with a power and lkfa intercept. These specifications are largely
-3 dB frequency of 725 MHz. The circuit still has 10 dB of determined by bias current in the output stage. At higher fre-
gain at 1 GHz. quencies the saturated output power decreases due to limita-
The circuit performance over temperature is summarized in tions on the drive available to the output stage. This behavior
Table I. Here the influence of the dc feedback is evident as is summarized in Fig. 7.

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MEYER AND BLAUSCHILD :4-TERMINAL AMPLIFIER 637

TABLE III
LOW-POWER
AMPLIFIER
SPECIFICATIONS

J’& 6V
‘dc 180 mW
N_oisefigure 4.4 dB
RI 50 Q (VSWR < 1.5)
R. 50 ~ (VSWR < 1.5)
Gain 18 dB
-3 dB bandwidth 725 MHz
1 dB gain compression point +3 dB_m
Saturated output power +12 dBm
Z&f3intereept +17 dBm
Active die size 18 X 17mils
Process n-p-n .fT 5 GHz

TEMPERATURE TA = 27°C

;[. ~
Fig. 9. High-power amplifier die photograph,

TABLE IV
MEASURED S PARAMETERS FORTHBHIGH-POWER
AMPLIFIER

F(MHz) Sll (dB) S12(dB) S21(dB) Sn (dB)

2

0, 1 II I 1 [Ill
70
I 1 I I I 1111
100
I 1 I I II
1000
100 -25.6 -14° -30.5 12° 23.0 -39° -11.8 -115°
FREQUENCY (MHz)
200 -24.5 -60° -30.1 8° 23.1 -48: -12.7 -127°
Fig. 7. Saturated output power versus supply voltage and frequency
450 -23.0 -11° -30.1 47° 21.9 -125 -6.9 -155°
650 -17.1 -20° -29.5 65° 19.3 169° -8.0 -155°
for the low-power amplifier.

Vcc = 9V
, The high-power circuit is housed in a 4-lead TO-39 can, and
Q3 RFC
in order to improve the circuit efficiency two external com-
RI 3s00
ponents are added. These are shown in Fig. 8 where the bias
<) resistor RB = 45 Q is external to the chip and connected to
RB 45rl
t Vcc via an RF choke, To further improve the output power
capability, the series matching resistor is omitted at the output
Q4 4
vi RFI
*
and the circuit is designed for an input resistance of 50 ~ and
Zzorl
R3 1Sa
output resistance of 25 fl.
‘El
The die photograph of the high-power amplifier is shown in
v
RFZ Fig. 9. Transistors Qz and Q5 carry the largest currents and
w +
130Q thus have the largest emitter areas. The current and power levels
4.5n RE2 used in the circuit require use of emitter ballasting to prevent
t
second breakdown in the active devices. This is achieved using
5$1 resistors in each emitter finger. These are fabricated using
the low sheet resistance of the deep collector n+ contact and
an effective total resistance of 0.4 fl in the emitter lead of the
Fig. 8. High-power amplWler schematic.
output transistor.
The measured 5’ parameters of the high-power amplifier are
VI. HIGH-POWER AMPLIFIER summarized in Table IV. A low-frequency gain of 23 dB has
The amplifier described above was designed for relatively been achieved with good input match to 50 S2, an output re-
low-power operation with good noise performance. However, sistance close to 25 Cl, and a -3 dB bandwidth of 625 MHz.
there are a number of applications which call for larger amounts The measured output power capability is shown in Fig. 10 and
of saturated output power than is available from this circuit. indicates that 152 mW is available at 200 MHz and 42 mW at
To meet this need, a high-power version of the circuit was 550 MHz.
designed with schematic as shown in Fig. 8. In this case, the
collector of Qb is connected to Vcc to allow miximum output VII. CONCLUSIONS
voltage swing. The supply voltage is raised to 9 V and the bias A wide-band monolithic amplifier has been described which
current in Q2 is raised to 70 mA. Total power dissipation is is housed in a 4-terminal package and needs no external com-
1 W. As explained in the Appendix, this requires RE2 to be ponents in its low-power version. A gain of 18 dB, bandwidth
reduced to 4.5 Cl. of 725 MHz, and noise figure of 4.4 dB are achieved by careful

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638 IEEE JOURNAL OF SOLID-STATE CIRCUITS,VOL. SC-16, NO. 6, DECEMBER 1981

TEMPERATURE TA = 27°C and thus

23 ~ Vcc = 9V
22
RF1 = 9RE1 . (10)
g
3 21
.
Values of RFI and RE1 can now be determined from (9) and
: 20 -
(10). A compromise arises here as a low value of RE1 is de-
:
; 19
sired for low noise figure. This forces a low value of RE1 from
$ ,8
0 (10) which leads to high bias current 1C3 from (9) with con-
R 17
%
sequent cost in dc power dissipation. A compromise value of
g 16
$
RE1 = 12 $2 is chosen giving RF1 = 1080. However, allow-
~ $5
I I I I I Ill I I I I I 1111
ance for losses due to RO requires a value of RF1 of 140 !2,
I I I I I I Ill I
14 -
1 10
FREQUENCY (MHd
100 ~000 giving 1C3 = 13 mA from (9) assuming RE2 << RZ. Equation
(6) then gives RE2 = 15 Cl. ac terminal impedance requirements
Fig. 10. Saturated output power versus frequency for the high-power
amp~ler, V&= 9 V. then dictate RF2 = 200 ~ and R. = 10 Q. The value of RF2
is maximized to optimize noise figure and the value of R ~ is
choice of circuit topology, layout, packaging, ind monolithic minimized to obtain maximum gain and output power. In the
process. A high-power 1 W of dc power and
version consumes final circuit, computer optimization of the above rtominal de-
gives 152 mW of output power at 200 MHz. sign resulted in slightly different design values.
The calculations above were performed using the low-power
APPENDIX amplifier schematic. Similar equations can be derived for the
dc BIAS IN THE AMPLIFIER high-power amplifier. The major design difference is the low
The dc bias equations for the amplifier can be derived from value required for RE2 (4.5 Q) from (6) because of the large
the full schematic of Fig. 2. All variables are dc quantities and bias currents in Q2 and Q6.
base currents are neglected. The dc voltage drop across RF2
is thus assumed negligible. The dc voltage drop across RE1 is ACKNOWLEDGMENT
assumed small compared to Vcc. The authors would like to acknowledge the contributions of
E. Aurand, M. Stevens, and B. Mack to the development of this
~= ~BE1 + (~c~
tzc3)REi (1)
amplifier, and the wafer fabrication expertise of T. Van den
= (IC2 +IC6)RE2 + VjE5 (2) Hurk.

vcc -3 v~E REFERENCES

ICI = (3)
RI
[1] K. H, Chan and R. G. Meyer, “A low-distortion monolithic wide-
band amplifier,” IEEE J. Solid-State Circuits, vol. SC-12, pp. 685-
VBE2
~c6 . — (4) 690, Dec. 1977.
R3 [2] J. B. Coughlin, R. G. Gelsing, P. J. Gocherns, and H. J. M. Van
Derlaak, “A monolithic silicon wide-band amplifier from dc to 1
GHz,” IEEE J. Solid-State Circuits, vol. SC-8, pp. 414-419, Dec.
1973.
Assuming @ QI and Q5 are designed for equal current density, [3] R. L Ollins and S. J. Ratner, “Computer-aided design and optimiza-
we have VBE1E VBE5and from (1) and (2) tion of a broad-band high-frequency monolithic amplifier,” IEEE J.
Solid-State Circuits, vol. SC-7, pp. 487-492, Dec. 1972.

(6)

Now from Fig. 2 Robert G. Meyer (S’64-M’68-SM’7 4-F’81) was

born in Melbourne, AustraHa, on July 21, 1942.
v~ = J’& - (IC2 +Ic6)R~ (7) He received the B.E., M.Eng.Sci., and Ph.D. de-
grees in electrical engineering from the Univer-
=(IC1 +IC3)RE1 +IC3RF1 + 2V~E (8) sity of Melbourne in 1963, 1965, and 1968,
respectively.
and from (6)-(8) In 1968 he was employed as an Assistant Lec-
turer in Electrical Engineering at the University
t& - (lc* +lcb)(R~ +RE2) - 2~~E of Melbourne. Since September 1968, he has
IC3 = (9) been employed in the Department of Electrical
RF1
Engineering and Computer Sciences, University
of California, Berkeley, where he is now a Professor. His current re-
The above equations now allow design of the circuit as fol- search interests are in integrated circuit design and device fabrication.
lows. The choice of Vcc is arbitrary and for the low-power He has been a consultant to Hewlett-Packard, IBM, Exar, and Signetics.
amplifier is 6 V. Noise requirements and output power capabil- He is coauthor of the book Analysis and Design of Analog Integrated
Circuits (Wiley, 1977), and Editor of the book Integrated Circuit Oper-
ity required design vtiues of Ic 1 = 5.5 mA, IC6 = 5 mA, ZC2 = ational Amplifiers (IEEE Press, 1978). He is Vice-President of the
10 mA, and VO= 3.2 V dc. From (3) we fmd Rl = 709 Q and Solid-State Circuits Council of the IEEE and is an Associate Editor of
from (4) R3 = 140 f2 assuming VBE= 0.7 V. Equation (7) the IEEE JOURNAL OFSOLID-STATE CIRCUITS.He is a former Associate
Editor of the IEEE TRANSACTIONS
ONCIRCUITS
AND SYSTEMS.
then gives R2 ‘ 187 G?.
For a nominal gain of 20 dB, we require [1]

RF1 + RE1
= 10 Robert A. Blauschild (S’70-M’74), for a photograph and biography,
R*, see this issue, p. 633.
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