EC311 - Introduction to Logic Design

Fall 2023

Class: MW 12:20pm – 2:05pm in PHO 203

Lab: Section C1, Mon 10:10am – 11:55am in PHO 115
Section C2, Fri 12:20pm – 2:05pm in PHO 115
Section C3, Tue 9:00am – 10:45am in PHO 115
Section C4, Thurs 3:30pm – 5:15pm in PHO 115
Section C5, Wed 4:30pm – 6:15pm in PHO 115
Number of credits: 4, Prerequisites: EK307

Course Objectives

The class covers the theory and practice of digital logic design. Students will learn to formulate real-
world tasks using Boolean algebra and Finite State Machine theory and to apply manual and computer-
aided design (CAD) techniques to solve problems. In addition, they will also learn fundamental circuit
design and verification skills using the Verilog Hardware Description Language (HDL) and Field
Programmable Gate Arrays (FPGAs).

Staff Information

Instructor
Name: Prof. Douglas Densmore
Office: CILSE 403 (NOT Photonics)
Office phone number: 617-358-6238 (better to email)
E-mail address: [email protected] (Best way to contact me - Include EC311 in the subject line)
Office Hours: Fridays 11am-noon or by appointment.
Zoom: https://bostonu.zoom.us/j/4602829913

Graduate Teaching Fellow (GTFs)

Name: Christopher Liao
Lab: Section C1: Monday 10:10am – 11:55am
E-mail address: [email protected] (Include EC311 in the subject line)
Office Hours: Friday 2:05pm-4:05pm - PHO 442
Zoom: https://bostonu.zoom.us/j/6651383856

Name: Shiva Raja

Lab: Section C5: Wednesday 4:30-6:15pm
E-mail address: [email protected] (Include EC311 in the subject line)
Office Hours: Wednesday 2:30pm-4:30pm – PHO 115
Zoom: https://bostonu.zoom.us/j/92144922342?pwd=bWhBYnNnRm1FUjhLVVZXTVJFaytiZz09

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Undergraduate Teaching Fellows (UTFs)
Name: Robert Bona
Lab: Section C2: Friday 12:20pm-2:05pm
Email address: [email protected] (Include EC311 in the subject line)
Office Hours: Tuesday 10:00am to noon - PHO 115 lab or PHO 305/307
Zoom: https://us05web.zoom.us/j/89740068132?pwd=YpT0tmhJate5GVbA4pBZMl9sJjgGcL.1

Name: Fadi Kidess

Lab: Section C4: Thursday 3:30pm-5:15pm
Email address: [email protected] (Include EC311 in the subject line)
Office Hours: Tuesdays 11:00am - 1:00pm - PHO 115 lab, PHO 305/307 lab, or the basement in LSE
Zoom: https://bostonu.zoom.us/j/98352668191?pwd=MzgyNFByMkRWdkhGdDZxSncyNWZLdz09

Name: Colin McDowell

Lab: Section C3: Tuesday 9am-10:45am
Email address: [email protected] (Include EC311 in the subject line)
Office Hours: Thursdays 11:00 am to 1:00 pm in PHO 115
Zoom: https://bostonu.zoom.us/j/95625378936?pwd=MGc1ZFFvUzFrRUU4QWp1WkppY3BVQT09

Course Resources

Required Textbooks

• Digital Design, Sixth Edition, Mano and Ciletti, Pearson (5th edition is also acceptable).

Optional Textbooks – many are harder to find – feel free to ask Prof. Densmore for other options
• Starter’s Guide to Verilog 2001, Ciletti, Pearson (optional).
• Verilog Styles for Synthesis of Digital Systems, Smith and Franzon, Prentice Hall (optional).
• Verilog for Digital Design, Vahid and Lysecky, Wiley (optional).
• Advanced Digital Design with the Verilog HDL, Ciletti, Prentice Hall (optional).
• Verilog HDL – A guide to digital design and synthesis, Samir Palnitkar, SunSoft Press (optional)
• Verilog HDL Basics – Youtube video: https://www.youtube.com/watch?v=PJGvZSlsLKs

Announcements, course material, and other useful links

Will be posted on Blackboard (learn.bu.edu)

• EC311/Fall 2023

Piazza is the best place to post questions, check for course updates, and see updates to labs and HW.
• https://piazza.com/bu/fall2023/ec311/home
• Sign up link - https://piazza.com/bu/fall2023/ec311

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Goals

To provide students with:

• An understanding of the basic theory of digital logic design
• An understanding of the basic software tools of digital logic design
• An understanding of the design methodologies for digital logic design
• An experience with actual hardware implementation and the use of CAD tools involving digital
logic design

Course Outcomes

As an outcome of completing this course, students should be able to:

• Understand the applications of digital logic design
• Understand abstraction and hierarchy in digital logic design
• Understand what components are available for digital logic design
• Understand the use of Boolean algebra in digital logic analysis and design
• Understand logic minimization criteria and methods for use in design
• Understand the concept of “state” in digital systems
• Understand how the concepts of digital logic design may apply to new research areas

• Design combinational digital logic systems given specifications

• Design sequential digital logic systems given specifications

• Implement digital logic designs in hardware and with CAD tools

• Discover component availability and data using the Internet or other resources

• Write brief reports and present results on assigned topics

Evaluation

Grading

Option #1: - Einstein Option #2: - Edison

Two Midterms – 17.5% (each) Two Midterms - 15% (keep best one; must take both)
Final Exam - 25% Final Exam - 15%
Project - 15% Project - 15%
Labs - 20% Labs - 20%
0 Homework Assignments - 0% 8 Homework Assignments - 15%
Class participation – free 5% Class participation – 5%
Support grading (≤ 16 assignments; 1 midterm) – 15%
(Twice the HW of option #1 and help grading)

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Students must decide which option they are going to pursue by 9/15 and send mail to [email protected]
with their decision. If you choose option #2 and do not do all HW assignments or fail to do your
assigned grading you default to Option #1 regardless of how far you have progressed.

Class Participation is increasingly important post-COVID-19 and virtual learning. Class participation
includes but is not limited to answering questions in class, attending office hours, helping others when
appropriate in the lab, answering posts in Piazza, and serving in a leadership role in your project group.

Homework

Homework assignments will be posted on the Blackboard website ahead of their due dates. Homework
is to be submitted as described in the assignment [TBD] as a single PDF file before the beginning of the
class (12:20 sharp) on the date specified. Submissions may be typed or scanned, as long as they are
legible. You can discuss your work in the abstract with other students in the class, but you must write up
the solutions on your own. No credit will be given for late homework.

EC311 Award #1: An award will be given for the best overall homework performance. This is based on
the best overall average.

Labs

Labs will be done in groups of two students. Lab assignments will be posted on the Blackboard website.
Grades will be assigned by demonstrating the lab as a team to the TA, and submitting the Verilog code
and design files as described in the assignment [TBD]. Students are expected to attend their scheduled
lab section every week as assigned, and complete labs outside of lab hours as needed. Request card
access to PHO115 through Zaius (http://www.bu.edu/dbin/eng/zaius/).

EC311 Award #2: An award will be given for the best overall lab performance. This is based on the best
overall average, lab citizenship, as well as the best lab-related piazza posts.

Exams

There will be two mid-term exams and a final exam. See the schedule in this document for the dates.

EC311 Award #3: An award will be given for the best overall exam performance. This is based on the best
overall average.

Project

Work as a team of 4 students. Project presentations will be during the last weeks of classes (see
schedule). Project presentations should be treated as a professional presentation.

EC311 Award #4: An award will be given for the best overall project performance. This will be given to
the team that has the best combination of project progress, project innovation, project presentation, and
project documentation.

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Course Policy

• Homework: The homework assignments must be the result of your individual work.
• Labs: The lab assignments must be the result of you and your partner alone. Do not work with other
groups.

• You may discuss the contents and general approach to a problem with your classmates but not the
detailed solution. You are expected to formulate your approach and to write the solutions to HW
problems by yourself. Copying the solution and/or answer from another student is considered
cheating. Two identical HWs with the same mistakes are considered cheating. No extensions on
homework or labs will be provided.

• Makeup exams: Makeup exams will be provided if the student receives prior permission from the
instructor. Emergencies will be dealt with on a case-by-case basis. Note that oversleeping, being not
ready, or being overloaded due to projects or coursework in other classes are not valid excuses for
requesting a makeup exam.

• Exam/Home/Lab Grade discussion: Grade discussion/corrections should be done within one week
after the graded exam of homework is distributed. No grade changes will be made after one week,
or after the last day of class.

• I and W grades: As per University policy.

• Honor Code: If you are found cheating on HWs, labs, or examinations, you will be brought up on
charges before the Student Academic Conduct Committee whose punishment may include
suspension from the University without the right to transfer credits for courses taken elsewhere.

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 Schedule for EC311 - Lectures, Homework, Labs and Exams
Lecture # Date Topic Description Labs Hw Hw
Out/Due Out Due
1 9/6 (W) Introduction, What is logic design?
Switches as a basis for digital
computation, CMOS technology:
transistors and gates
2 9/11 (M) Number systems and codes, Prelab/NA HW1
Abstraction, Combinational vs. Sequential systems
3 9/13 (W) Combinational logic, Boolean algebra
4 9/18 (M) Canonical forms, Algebraic simplification, Logical HW2 HW1
minimization, Boolean cubes
5 9/20 (W) Verilog Introduction Lab1/Prelab
6 9/25 (M) FPGA design + More Verilog HW3 HW2
7 9/27 (W) Karnaugh maps
8 10/2 (M) K-map manip., Prime implicants, Multilevel logic HW4 HW3
9 10/4 (W) Delay, Timing waveforms, Hazards, Lab2/Lab1
Glitches, Multiplexers and de-multiplexers
10/9 (M) Indigenous People’s Day
10 10/10 (T) Multiplexers as general-purpose logic HW5 HW4
functions, Gate arrays, Look-up tables, PLAʼs
11 10/11 (W) Review for Midterm 1 Lab3/Lab2
12 10/16 (M) Midterm 1
13 10/18 (W) Two's complement, Adder design, Multipliers
14 10/23 (M) Sequential logic, Latches, Flip-flops HW6 HW5
15 10/25 (W) Sequential Components, Registers, Metastability
16 10/30 (M) Counters Lab 4/Lab3 HW7 HW6
17 11/1 (W) Finite State Machine, FSM Design Approaches
18 11/6 (M) Optimization of FSMs HW8 HW7
19 11/8 (W) RTL design, State encoding, Traffic controller
20 11/13 (M) Implementation examples, Lab 5/Lab4 Proj. HW8
Specification of state diagrams
21 11/15 (W) Review for Midterm 2
22 11/20 (M) Midterm 2
Thanksgiving
23 11/27 (M) Memory
24 11/29 (W) Computer organization, processors Lab5 due
25 12/4 (M) Project presentations
26 12/6 (W) Project presentations
27 12/11 (M) Project presentations
28 12/13 (W) Project presentations Proj.
TBD Final exam – TBD

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