Department of Electrical Engineering

Faculty Member: Dr. Shazad Younis Date: 5th February,2025

Semester: 6th (spring 2025) Section:BEE-14-D

EE-421 Digital System Design

Lab 02: Combinational Circuits Design and Dataflow
Modelling

PLO4 PLO4 PLO5 PLO8 PLO9

CLO4 CLO4 CLO5 CLO6 CLO7

Ethics
Viva / Modern
Student Name Reg. No Analysis Individual
Quiz / of Data Tool and
Demo in Report Usage Teamwork

5 Marks 5 Marks 5 Marks 5 Marks 5 Marks

Ahmad Nasir 409959

Sataish Elahi 423621

Irfa Farooq 412564

 Combinational Circuits Design and Dataflow Modelling
Objective
The objective of this lab is to design combinational circuits and implement them on a
DE1-SoC board. The focus of this lab is to describe combinational circuits using the dataflow
method.
Introduction
The objective of this lab is to design combinational circuits and implement them on a
DE1-SoC board using Intel's Quartus Prime software. The focus is on describing combinational
circuits through dataflow modeling, which emphasizes functional descriptions rather than
gate-level structures.
Field-Programmable Gate Arrays (FPGAs) have revolutionized digital design by
enabling the implementation of complex circuits using programmable logic. This lab exercise
provides hands-on experience in designing and implementing digital circuits, utilizing
switches, lights, and multiplexers. By the end of this lab, we will gain a deeper understanding
of combinational circuit design, the use of dataflow modeling in Verilog HDL, and how
fundamental digital components can be integrated into larger systems. Additionally, we will
develop proficiency in using Intel's Quartus Prime software, a leading platform for FPGA-
based digital design

Software
Quartus Prime is a comprehensive design software developed by Intel Corporation for
designing digital circuits using Field-Programmable Gate Arrays (FPGAs). It is a leading
software platform in the field of digital design, offering a range of advanced tools and features
that enable users to easily create, debug, and verify complex digital circuits. With Quartus
Prime, users can benefit from a streamlined design flow that facilitates the creation of digital
circuits from concept to implementation. It provides an intuitive graphical user interface that
allows users to easily design, test, and debug their circuits. Additionally, Quartus Prime
supports a variety of popular programming languages, making it a versatile platform for
digital designers of all levels.
Dataflow Modelling
Dataflow modeling provides the means of describing combinational circuits by their
function rather than by their gate structure. Dataflow modeling uses a number of operators
that act on operands to produce the desired results. Verilog HDL provides about 30 operator
types.
In dataflow modelling, the assign keyword is used to create continuous assignments.
Continuous assignments are used to model combinational logic in hardware description
languages. They specify how signals are related to each other in terms of logic expressions
 Lab Procedure
Task 1 : Understanding FPGA Input/Output using Constraint File
In this task, we will use Quartus system file having .qsf as file extension for pin assignment
for 2 input AND gate.
module andgate(output f, input a, input b);
assign f = a & b;
endmodule

The qsf file describes the pin locations of various peripherals that are connected with FPGA.

Figure 1 Sample QSF File

● To add qsf file, go to Assignments > Export Assignments & then Open *.qsf from 'File'->'Open'
Menu. Once this file is added in the project you will see it in the directory of your project.
● On the same lines navigate to set_location_assignment PIN_V16 -to LEDR[0] and change LEDR[0] with
f.
● Save the file and recompile the design and load it onto the FPGA. Test the functionality of the
AND gate by applying different input combinations of a and b such as (0,0), (0,1), (1,0) and (1,1).
 Figure 2 Uploading File to FPGA

● Analyze the synthesis report to figure out the utilization of FPGA resources. To see how much logic is
used to synthesize the design, select Processing > Compilation Report. Click on Analysis & Synthesis
> Place Stage > Resource Usage Summary. The Analysis & Resource usage summary window will
show the number of resources used after synthesis.

Figure 3 Resource Utilization Summary

● To see how much of the device is used to implement the design, select Processing > Compilation
Report. Click on Fitter > Resource Section > Resource Usage Summary.
Figure 4 Resource utilization summary after implementation

Figure 5 RTL Diagram

Task 2 : Implementation of Half Adder on FPGA
Hardware Implementation:

Figure 6 Implementation of a Half Adder

Task 3 : Binary-2-Seven Segment Converter

● Design a Binary-2-Seven Segment Converter

Truth Table

7-Segment Output
Binary Input (Hex) Binary Input (4-bit)
(abcdefg) Active-High

0 0000 1000000

1 0001 1111001

2 0010 0100100

3 0011 0110000

4 0100 0011001

5 0101 0010010

6 0110 0000010

7 0111 1111000

8 1000 0000000

9 1001 0011000

A 1010 0001000

B 1011 0000011

C 1100 1000110

D 1101 1011110

E 1110 0000110

F 1111 0001110
Equations of the Seven Segment display.
Each segment equation is derived using Sum of Products (SOP) based on rows where the segment is ON
(1).
Equation for Segment a Equation for Segment d

Equation for Segment b Equation for Segment e

Equation for Segment c Equation for Segment f

 Equation for Segment g

Code:

module BCD2HEX(
input a, b, c, d,
output [6:0] ledx
);

assign ledx[0] = ~((~b & ~d) | (~a & c) | (a & ~d) | (b & c) | (a & ~b & ~c) |
(~a & b & d));
assign ledx[1] = ~((~b & ~c) | (~b & ~d) | (~a & ~c & ~d) | (~a & c & d) | (a &
~c & d));
assign ledx[2] = ~((~b & ~c) | (~b & d) | (~c & d) | (~a & b) | (a & ~b));
assign ledx[3] = ~((a & ~c) | (~a & ~b & ~d) | (~b & c & d) | (b & ~c & d) | (b
& c & ~d));
assign ledx[4] = ~((~b & ~d) | (c & ~d) | (a & c) | (a & b));
assign ledx[5] = ~((~c & ~d) | (b & ~d) | (a & ~b) | (a & c) | (~a & b & ~c));
assign ledx[6] = ~((~b & c) | (c & ~d) | (a & ~b) | (a & d) | (~a & b & ~c));
end Module
Test Bench:

`timescale 1ns / 1ps

module BCD2HEX_tb;

reg a, b, c, d;
wire [6:0] ledx;

// Instantiate the module under test

BCD2HEX UUT (
.a(a), .b(b), .c(c), .d(d),
.ledx(ledx)
);
initial begin
$monitor("Time=%0t | BCD=%b%b%b%b | LEDx=%b",
$time, a, b, c, d, ledx);
 a = 0; b = 0; c = 0; d = 0; #10;
a = 0; b = 0; c = 0; d = 1; #10;
a = 0; b = 0; c = 1; d = 0; #10;
a = 0; b = 0; c = 1; d = 1; #10;
a = 0; b = 1; c = 0; d = 0; #10;
a = 0; b = 1; c = 0; d = 1; #10;
a = 0; b = 1; c = 1; d = 0; #10;
a = 0; b = 1; c = 1; d = 1; #10;
a = 1; b = 0; c = 0; d = 0; #10;
a = 1; b = 0; c = 0; d = 1; #10;

// End simulation
$finish;
end
endmodule

Implementation:
Task 4 : 4-bit Adder/Subtractor Output on Single Seven Segment
Display
● Analyze the synthesis report and see whether the resource utilization makes sense.

Code:
module Adder_Subtractor_4bit ( input wire wire [3:0] Sum;
[3:0] A, B, input wire mode, output wire
[3:0] Sum, output wire Carry, Overflow );
Adder_Subtractor_4bit U1 (
.A(A),
wire [3:0] B_modified;
.B(B),
wire Carry_out;
.mode(mode),
.Sum(Sum),
assign B_modified = B ^ {4{mode}}; assign
{Carry_out, Sum} = A + B_modified + mode; .Carry(Carry),

assign Carry = Carry_out; .Overflow(Overflow)

assign Overflow = (A[3] ~^ B_modified[3]) & );

(A[3] ^ Sum[3]);

BCD_to_7Segment U2 (
endmodule .w(Sum[3]), .x(Sum[2]), .y(Sum[1]),
.z(Sum[0]),

module Top_Module ( .a(Display[0]), .b(Display[1]), .c(Display[2]),

.d(Display[3]),
input wire [3:0] A, B, input wire mode,
output wire [6:0] Display, .e(Display[4]), .f(Display[5]), .g(Display[6])

output wire Carry, Overflow );

);
endmodule
Test Bench:

`timescale 1ns / 1ps $time, A, B, mode, UUT.U1.Sum, Carry,

Overflow, Display);
module Top_Module_tb;
mode = 0;
reg [3:0] A, B; A = 4'b0001; B = 4'b0001; #10; // 1 + 1 = 2
reg mode; A = 4'b0011; B = 4'b0010; #10; // 3 + 2 = 5
wire [6:0] Display; A = 4'b0111; B = 4'b0001; #10; // 7 + 1 = 8
wire Carry, Overflow; A = 4'b1001; B = 4'b0001; #10; // 9 + 1 = 10
(overflow case)
Top_Module UUT (
.A(A),
.B(B), mode = 1;
.mode(mode), A = 4'b0100; B = 4'b0001; #10; // 4 - 1 = 3
.Display(Display), A = 4'b0110; B = 4'b0011; #10; // 6 - 3 = 3
.Carry(Carry), A = 4'b0010; B = 4'b0110; #10; // 2 - 6 = -4
.Overflow(Overflow) (overflow case)
);
$finish;
initial begin end
endmodule
$monitor("Time=%0t | A=%b, B=%b,
Mode=%b | Sum=%b, Carry=%b, Overflow=%b,
Display=%b",

QSF file:
set_location_assignment PIN_A1 -to A[0]
set_location_assignment PIN_A2 -to A[1]
set_location_assignment PIN_A3 -to A[2]
set_location_assignment PIN_A4 -to A[3]
set_location_assignment PIN_B1 -to B[0]
set_location_assignment PIN_B2 -to B[1]
set_location_assignment PIN_B3 -to B[2]
set_location_assignment PIN_B4 -to B[3]
set_location_assignment PIN_M1 -to mode
set_location_assignment PIN_C1 -to Carry
set_location_assignment PIN_O1 -to Overflow
set_location_assignment PIN_D1 -to Display[0]
set_location_assignment PIN_D2 -to Display[1]
set_location_assignment PIN_D3 -to Display[2]
set_location_assignment PIN_D4 -to Display[3]
set_location_assignment PIN_D5 -to Display[4]
set_location_assignment PIN_D6 -to Display[5]
set_location_assignment PIN_D7 -to Display[6]
Implementation:
Task 5 : 4-bit Adder/Subtractor Display
Code:
module Top_Adder_Subtractor ( input wire .a(seg1[0]), .b(seg1[1]), .c(seg1[2]),
[3:0] A, B, input wire mode, output wire .d(seg1[3]), .e(seg1[4]), .f(seg1[5]),
[6:0] seg1, .g(seg1[6])
output wire [6:0] seg2 );
);
BCD_to_7Segment U4 (
wire [4:0] result; .w(BCD_tens[3]),
.x(BCD_tens[2]), .y(BCD_tens[1]),
wire [3:0] BCD_units, BCD_tens;
.z(BCD_tens[0]),
wire carry_out, overflow_flag;
.a(seg2[0]), .b(seg2[1]),
.c(seg2[2]), .d(seg2[3]), .e(seg2[4]),
Adder_Subtractor U1 ( .f(seg2[5]), .g(seg2[6])

.A(A), );

.B(B),
.mode(mode), endmodule

.Sum(result),
.Carry(carry_out), module Binary_to_BCD (

.Overflow(overflow_flag) input wire [4:0] binary, output reg

[3:0] tens,
);
output reg [3:0] units
);
Binary_to_BCD U2 (
.binary(result[4:0]),
always @(*) begin
.tens(BCD_tens),
if (binary > 9) begin tens =
.units(BCD_units) 1; units = binary - 10; end else
); begin tens = 0; units = binary;
end end

BCD_to_7Segment U3 (
endmodule
.w(BCD_units[3]), .x(BCD_units[2]),
.y(BCD_units[1]), .z(BCD_units[0]),
Test Bench:
`timescale 1ns / 1ps $monitor("Time=%0t | A=%b, B=%b,
Mode=%b | seg1=%b, seg2=%b", $time, A, B,
module Top_Adder_Subtractor_tb; mode, seg1, seg2);
// Testbench signals
reg [3:0] A, B; // Test addition mode (mode = 0)
reg mode; mode = 0;
wire [6:0] seg1, seg2; A = 4'b0011; B = 4'b0001; #10; // 3 + 1 = 4
A = 4'b0110; B = 4'b0011; #10; // 6 + 3 = 9
// Instantiate the module under test A = 4'b1001; B = 4'b0001; #10; // 9 + 1 = 10
Top_Adder_Subtractor UUT (
.A(A), // Test subtraction mode (mode = 1)
.B(B), mode = 1;
.mode(mode), A = 4'b0110; B = 4'b0011; #10; // 6 - 3 = 3
.seg1(seg1), A = 4'b1000; B = 4'b0001; #10; // 8 - 1 = 7
.seg2(seg2) A = 4'b0100; B = 4'b0101; #10; // 4 - 5 = -1
(BCD should handle negative cases)
);

// End simulation
// Test sequence
$finish;
initial begin
end
// Monitor outputs
endmodule

Implementation:
Conclusion:
This lab offered an in-depth exploration of the FPGA design process, from setting pin constraints
in Quartus to testing fundamental logic modules and integrating advanced circuits like a 4-bit
adder/subtractor with a seven-segment display. Throughout these exercises, we gained hands-on
experience in circuit validation, resource utilization assessment, and addressing real-world challenges
such as BCD decoding limitations and constraints of a single display. Ultimately, this project enhanced our
grasp of digital design and system integration, equipping us for more complex FPGA applications.