Asynchronous SAR ADC: Past,

Present and Beyond

Mike Shuo-Wei Chen

University of Southern California
MWSCAS 2014

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 Roles of ADCs
• Responsibility of ADC is increasing  more BW, more
dynamic range
• Potentially simplify analog pre-conditioning circuits
• Reconfigurable system imposes more weights on ADC

IF Sampling, except IF is becoming RF

Direct RF Sampling

spec/cost of ADC?

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 Who is driving higher speed?

• Low Medium resolution (6bit) with 10-100 GS/s

High speed optical links, instrumentations.
• High Medium resolution (10bit), with 100MS/s to
a few GS/s.
Radars, Commercial Communications, or
wideband radios, such as 60GHz, UWB, SDR,
Cognitive radio.
 Power efficiency is a key issue!

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 Why possible now?

• Cost of such ADCs used to be intimidating,

bounded by Walden wall.
• CMOS technology provides tremendous
opportunity.
• Circuit designers enjoy inventing and polishing
ADC architectures.

 Given the resolution, speed and power efficiency

advanced by orders of magnitude over the past
decade

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 Walden’s ADC Survey

Robert Walden, “Analog-to-Digital Converter Survey and Analysis”, Journal of

selected area in communications, 1999.
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 Optimal ADC Architecture?

• Architecture that promotes mostly digital operation

so it scales with CMOS technology

• No high precision analog requirement

• Tolerate low voltage design

• Take advantage of device speed

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 ADC Architecture Overview

Flash Pipeline SAR

Vin
Vref
Vin
Stage Stage
1 N

Decoder
Decoder

Stage i
S/H +
DAC
ADC DAC

CLK
CLK

Complexity

Conv. time
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 Successive Approximation (SAR) Algorithm

• Binary
searching.
• N-bit resolution
requires N
comparisons, i.e.
1 bit per cycle.

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 Typical SAR Logic

• N-bit SAR requires

at least N+1
cycles.
• Typically, a fast
clock is used to
divide the time into
S/H, and N bit
comparison.
• DAC and SAR
logic change
reference levels.

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 DAC Implementation

• Capacitor array to perform sampling and

charge redistribution  fast and low
power. This is most commonly used.
• However, other DAC implementations are
possible, such as resistor ladder network
or capacitor-resistor hybrid version.

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 Sampling Phase

• Sampling on the capacitive DAC.

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 First MSB comparison

• All capacitors are connected to Vcm.

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 Second MSB Comparison

• If Vin > 0… The rest of bit conversions

follows.

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 Why SAR?

1. Mostly digital components  good for

technology scaling
2. No linear, high precision amplification is
required  fast, low power
3. Minimal hardware  1 comparator is needed
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 Evolving Ecosystem

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 SAR ADC in the past 10 years

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 Limitation of Synchronous SAR
MSB MSB-1 MSB-2 LSB

Tracking Synchronous
Phase Conversion Phase Sampling Instants
Internal
CLK
Jitter

• Cost
– No redundant comparison
– High-speed internal clock

• Speed limitation
– Worst-case cycle time
– Margin for clock jitter
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 Asynchronous SAR ADC Concept
MSB MSB-1 MSB-2 LSB

Tracking Asynchronous
Phase Conversion Phase Sampling Instants

Vref
C VFS
'0' 3 tcmp  ln( )
4 Vref g m VID
Vin
5
'1' 8Vref
1 '1' Full
2 Vref

tcmp
Scale

Conversion Time
Gnd VID
M. S.W. Chen, R. Brodersen, “A 6b 600MS/s 5.3mW
Asynchronous ADC in 0.13µm CMOS,” ISSCC 06. Still uniform sampling…
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 How much time can it save?
• Conv. time between sync. and async. SAR,
assuming regenerative comparator is used.
• It varies with residue voltage profile

Best case

Worst case

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 Best Case

• Peak input value yields larger Vres pattern

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 Worst Case (I)

• Input with alternative polarity  smaller

magnitude

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 Worst Case (II)
• As N increases, it approaches ½, same as the
best case!

• Note that: Since there is no synchronous clock

uncertainty, more saving is possible! Actual time
saving depends on input signal characteristics.
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 First Asynchronous SAR ADC
Prototype

Vin
Non-Binary
Vref+ SR
Capacitor
Network Latch
Vref-

Switch bit0
Pulse Ready Logic
Generator Generator &
Bit SRAM
Clk0 Caches
2-phase
Clk1 clock
iCLK0 bit6
generation Sequencer
(Multi-Phase CLK)
iCLK6

Asynchronous digital circuits

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 Dynamic Comparator
pre-amplifier regenerative latch

2a eq
2a strobe Qn Qp strobe

eq

Vip Vin
Qp Ready

Vb Qn

• Dynamic to save power and generate ready signal

• Reset switches for fast recovery
• Ready signal is generated by NAND gate!
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 Metastable Issue
large vid moderate vid~0
vid (metastable
'1' '1' )

Cmp NAND gate

Outputs threshold

'1' '0' '0' '1' '0' '0' VFS

Ready
Signal

If a comparison is stuck, SAR conversion won’t be complete!

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 Sampling Network
• Series capacitor bank reduces input cap loading
and settling time (C-2C network if α=β=2)

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 Die Micrograph
1.4 mm

240 µm
1.74 mm

250 µm
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 Single Async. SAR ADC
• Resolution naturally tradeoffs with sampling rate!

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 Single Async. SAR w/ RF Input

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 Dual Async. SAR ADCs

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 Performance Summary
Technology 0.13-mm 6M CMOS

Package Chip-on-board

Resolution 6 bits

300-500 MS/s for single ADC

Sampling rate
(600M-1GS/s for dual)

Supply voltage 1.2 V

Input 3dB BW > 4 GHz

Peak SNDR 34 dB (fs = 600MS/s for dual ADC)

INL/DNL 0.5 / -0.5 LSB

Analog 1.2mW
Total (dual ADC):
Power Digital 3.2mW
5.3mW
Clock 0.9mW
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 Comparison with SOA in 2006
• High-speed (>10MS/s, 6-10b) ADCs from ISSCC (00’-05’)

Total_PW
Fs  2ENOB

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 Technology Scaling

Ttrack Tcomp Tdig

RCH~1/S 1/fT~1/S RC~1/S

Panalog Pclk Pdig

IV~1/S fCV2~[1/S-1/S2] fCV2~1/S2

• Constant field scaling (W,L,Vdd ↓ 1/S)

 FOM (joule/conversion step) ↓ 1/S2
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 Asynchronous SAR Advantages

• Asynchronous SAR architecture breaks

the speed limit of conventional
synchronous design methodology.
• Clock generation requirement is
significantly relaxed.
• It was just the starting point… many
variations can be introduced potentially.

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 What’s next?

1. Higher resolution  approaching KT/C

limit regime?

2. Higher speed  1-100 GS/s sampling

rate possible?

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 Higher Resolution Extension

• Traditional Asynchronous SAR

VIN
DAC

Asynchronous
SAR Logic

• Proposed Passive Gained Asynchronous SAR

VIN
DAC GPassive

Asynchronous
SAR Logic

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 Proposed Passive Gained SAR
VN,Comp 1 Input referred
Noise
GPassive
VIN VN,Comp
DAC GPassive

Asynchronous
𝐃𝐎𝐔𝐓
SAR Logic

• Key highlights
1. Passive amplifier(Power-less) ► Comparator noise spec. 
Non-linear distortion
2. Redundant SAR operation ► 
due to parasitic Cap.
3. Passively amplified signal ► Comparison time 
4. Embedding amplifier into DAC ► DAC settling time 
► Full-scaled amplifying O
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 Proposed Passive Gain SAR
VN,Comp Input referred
Noise
GPassive
VIN VN,Comp
DAC GPassive

Asynchronous
𝐃𝐎𝐔𝐓
SAR Logic
Converged to
2
• Key highlights common mode
at the final

1. Passive amplifier(Power-less) ► Comparator noise spec. 

Non-linear distortion
2. Redundant SAR operation ► 
due to parasitic Cap.
3. Passively amplified signal ► Comparison time 
4. Embedding amplifier into DAC ► DAC settling time 
► Full-scaled amplifying O
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 Proposed Passive Gain SAR
VN,Comp Input referred
Noise
GPassive
VIN VN,Comp
DAC GPassive

Asynchronous
𝐃𝐎𝐔𝐓
SAR Logic
xGPassive
• Key highlights 3

1. Passive amplifier(Power-less) ► Comparator noise spec. 

Non-linear distortion
2. Redundant SAR operation ► 
due to parasitic Cap.
3. Passively amplified signal ► Comparison time 
4. Embedding amplifier into DAC ► DAC settling time 
► Full-scaled amplifying O
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 Proposed Passive Gain SAR
VN,Comp Input referred
Noise
GPassive
4 VN,Comp
VIN
DAC GPassive

Asynchronous
𝐃𝐎𝐔𝐓
SAR Logic

• Key highlights
1. Passive amplifier(Power-less) ► Comparator noise spec. 
Non-linear distortion
2. Redundant SAR operation ► 
due to parasitic Cap.
3. Passively amplified signal ► Comparison time 
4. Embedding GPassive into DAC ► DAC settling time 
► Rail-to-rail input swing √
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 Embedded Passive Gain Operation

Split Capacitor Stacked Capacitor

(Double Sampling) (Amplification)

VIN
-2VIN
Passive
MS1 MS2 Gain
CS + +
- CS1 CS2 - - -
+ +
CS1 CS2

CS CS
2 2

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 Embedded Passive Gain Operation

Split Capacitor Stacked Capacitor Subsequent

(Double Sampling) (Amplification) SAR operation

VIN
-2VIN -2VIN+Vtune
Passive
MS1 MS2 Gain
CS + +
- CS2 - SAR
CS1 - - Operation
+ +
CS1 CS2 Vtune
C-DAC

CS CS
2 2

Controlling only CS/2 during SAR operation

► DAC response speed 
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 Voltage Over-range Issue
Φ1’
Φ1 : Sampling VIN to CS1 & CS2
Φ1
Φ2 : Charge Redistribution Φ2

CS2
VIN
CS1 Φ1
VIN VX VOUT
Φ1 – +
Φ1’
– + Φ2
Φ1’
Φ2

+VFS/2 +VFS/2 +VFS/2

0 VIN 0 VX 0 VOUT

- VFS/2 - VFS/2 - VFS/2

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 Voltage Over-range Issue
Φ1’
Φ1 : Sampling VIN to CS1 & CS2
Φ1
Φ2 : Charge Redistribution Φ2

Not properly
CS2 Turned off
VIN
CS1 Φ1
VIN VX VOUT
Φ1 – +
Φ1’
– + Φ2
Φ1’
Φ2
Rail-to-rail [X]
Input Swing

+VFS/2 +VFS/2 +VFS/2

0 VIN 0 VX 0 VOUT

- VFS/2 - VFS/2 - VFS/2

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 Proposed Level Shifting

Comparator
VIN CS2
CS1 Φ1
VIN VX VOUT
Φ1 – +
Φ1’
– + Φ2
Φ1’ Level Shifting
Φ2
Circuit

• Procedures
(1) MSB decision by using CS2
(2) Performing Level shifting

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 Level Shift Up [MSB>0]
[MSB-1]
CASE – I : VIN = [ -VFS/2, 0 ] VFS/2
Decision range

Level shift up

0 x2
Φ1’ VIN
Φ1 VFS/2
Φ2
Performing at once
Φ1
Φ3 doubled VIN
VOUT
CS2
Comp.
– +

Φ3 Φ1’
– +
VIN
Φ1 MSB (=D[1])
Φ1’ Φ2
CS1 Φ3 CBAT
Φ3
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 Level Shift Down [MSB<0]
[MSB-1]
CASE – II : VIN = [ 0, VFS/2 ] VFS/2
Decision range

VIN
0 x2
Φ1’
Φ1 VFS/2 Level shift down
Φ2
Performing at once
Φ1
Φ3 doubled VIN
VOUT
CS2
Comp.
– +

Φ3 Φ1’
– +
VIN
Φ1 MSB (=D[1])
Φ1’ Φ2
CS1 Φ3 CBAT
Φ3
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 Free of Voltage Clipping
+ VFS/2 + VFS/2 + VFS/2 + VFS/2

VOUT
VIN VX VY
0 0 0 0

- VFS/2 - VFS/2 - VFS/2 - VFS/2

VIN
Φ1
CS2 VOUT
Comp.
– +
VX
Φ3 Φ1’
– +
VIN
Φ1
Φ1’
CS1 Φ3 CBAT Φ2
VY
Φ3

• Allowing rail-to-rail input signal swing

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 Subsequent SAR Operation
𝟏𝟐
𝐃𝐎𝐔𝐓 [𝒊]
𝐕𝐃𝐀𝐂 = ∙ 𝑽𝑹𝑬𝑭
𝐑𝐱[𝒊]𝒊
𝒊=𝟐 VOUT
CS1 CS2

VIN VIN
VREF CBAT
Φ2 Φ1’

Φ1’
D[2:12] D[1]
12 Asynchronous
SAR Logic

• CS1 consists of non-binary weighted Cap arrays.

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 KT/C Noise Analysis

Sampling Phase Amplifying Phase

𝑽𝐈𝐍
𝐒𝐍𝐑 𝐢 ≝
𝑲𝑻
VBAT VIN - 2VIN±VBAT 𝐂𝒔
Passive
Gain Signal Amplitude: 2VIN
CBAT - - + + 𝑲𝑻
RMS V[ KT/C Noise ] : 𝟐
𝐂𝒔
+ + - -
SNRO = SNRi

CS CS CS CS Selecting large size of CBAT

CBAT CBAT (SNR drops due to CBAT) < 0.5dB
2 2 2 2

• Sufficiently large sized CBAT to prevent SNR degradation

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 Comparator
VDD
MP3 MP4 MP5 MP6 CKAMP
MP1 MP2
CKRS
R1 R2
Equalize Amplify S1 >> S2

1st Stage 2nd Stage

CKAMP S2
S1 : ON OFF
VO2P VO2N S2 : ON ON
VO1N VO1P
Latch
CKRS S1 CKRS
CKAMP

CKRS VOUTP VOUTN

VINP VINN
CKRS

MN1 MN2 MN3 MN4

MN5 MN6
IS1 IS2
CKAMP

• Dual sized switches ► Fast Reset (S1)

► Amplifying (S2)
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 Time-out Scheme

Sampling Clock

VINP
DAC Earlier arrived pulse
VINN Vdata_ready detected Normal Operation Loop
Time-out operation Loop
SW_CTRL CKAMP, CKRS

CKRS
Delay T time-out Vtime-out

Asynchronous SAR logic

• Forcing the advancement of asynchronous

conversion if comparator is stuck.
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 Time-out Timing Diagram
SCLK

Env_Conv T Conv
1st 2nd 3rd 4th Nth

CKAmp T time-out
…

Vdata_ready
Time-out
detect
…

Vtime-out …
Comparator’s
threshold level
Vcomp …
Code 1 0 1 1 0

• Vtime-out forces next conversion

(Ttime-out designed for worst case)
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 Chip Micrograph

Bootstrap
SW

Comparator
CDAC CDAC

280um
CBAT P N CBAT
(CS1) (CS1)
260um CS2 CS2

Async.
SAR Logic

Decimator

• Active Area: 280μm X 260μm

J. Nam, D. Chiong, M. S.W. Chen, “A 95-MS/s 11-bit 1.36-mW Asynchronous SAR
ADC with Embedded Passive Gain in 65nm CMOS”, CICC 2013.
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 Static Performance

+1.0
DNL (+0.70/-0.84 LSB)
[LSB]

0.0

-1.0
0 [CODE] 2047

+1.0
INL (+0.79/-0.84 LSB)
[LSB]

0.0

-1.0
0 [CODE] 2047

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 Dynamic Performance
After Radix Calibration*
0
fIN = 1.0 MHz, fS = 95 MHz SNDR = 63.1 dB
Power (dB)

ENOB = 10.2 SFDR = 75.2 dB

-40

HD2 HD3 HD5

-80

-120
fS 2 fS 3 fS 4 fS
0
32 32 32 32
(ADC output decimated by 4x)
Normalized Frequency

80
Power (dB)

SFDR
70
57.8 dB
60
fS = 95 MHz SNDR
50
0 10M 20M 30M 40M 50M
Input Frequency (Hz)
0 Group
Mike Chen’s IC fIN = 1.0 MHz, fS = 95 MHz SNDR = 63.1 dB
)

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Performance Summary

Asynchronous SAR
ADC Topology
with Passive Gain
fsampling 95-MS/s
Resolution 11-bit
Signal Bandwidth 47.5 MHz
Supply (V) 1.1 V
SFDR (dB) 75.2 dB
SNDR (dB) 63.1 dB
Power (mW) 1.36 mW
Area (mm2) 0.073 mm2
Process (nm) 65 nm CMOS
FoM
22 fJ/conv.-step @ Nyquist
14 fJ/conv.-step @ Low Freq.

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 Comparison to prior art

Filtering with > 10.0 ENOB, > 10MS/s

80.0
ISSCC 1997-2013
VLSI 1997-2013
FoM [fJ/step]

60.0

This work
40.0 10.2 ENOB
(@ Nyquist)

20.0 (@ Low Freq.)

0.0
0 20M 40M 60M 80M 100M
fsample

• Achieves the lowest FoM among recently published ADCs

( >10ENOB, > 10MS/s )
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 Higher Speed Extension

• What if higher speed is demanded?

1. Unrolled comparators
2. Asynchronous DAC settling
3. Multi-bit/cycle
4. Pipelining
5. Time interleaving

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 Unrolled Comparators
• Unroll the comparators  No comparator reset
 No DAC settling

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 Unrolled Asynchronous SAR

G. Van der Plas, et al, “A 150 MS/s 133 uW 7 bit ADC in 90 nm Digital CMOS
“, JSSC, 2008

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 Asynchronous DAC Settling
• DAC settling can also be asynchronous

R. Kapusta, et al., “A 14b 80MS/s SAR ADC with 73.6dB

SNDR in 65nm CMOS,“ ISSCC 2013.

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 Multi-bit/cycle Conversion
- Fewer cycles
required for
conversion
- Time-to-digital
converter can
assist bit
comparison
But…
-Give away the
offset tolerance
-Opportunities for
calibration

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 Pipelining
• Residue voltage is available on capacitor
network for free

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 Time Interleaving
• Sampling rate scale
proportionally to the
number of interleaved
channels

• Calibration is required
for inter-channel
mismatch

• Relaxed clock
distribution

• For example:
8bit 56GS/s
 320 of 175MS/s SAR
(Fujitsu)

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 90GS/s 8bit with 64x Time Interleave
• Two comparators ping pong in two consecutive
conversions implemented in 32nm SOI

L. Kull, et al., “A 90GS/s 8b 667mW 64x Interleaved

SAR ADC in 32nm Digital SOI CMOS,” ISSCC 14.
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 Family of Asynchronous SAR
• High-speed (>10MS/s, 5-10b) ADCs from ISSCC (00’-10’)
• Asynchronous SAR has been widely adopted since 2006.
• Benefit from technology scaling!

Total_PW
Fs  2ENOB

Latest: 8b, 90GS/s,

200 fJ/conv-step
ISSCC 2014
Family of Async. Enabled ADC

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 Future Asynchronous SAR
• The trend is going towards 1-100GS/s ADC.
• Power efficiency is going towards the order of 1-10
fJ/conv-step.

Total_PW
Fs  2ENOB

Latest: 8b, 90GS/s,

200 fJ/conv-step
ISSCC 2014

Mike Chen’s IC Group Future Breakthroughs! 68

 Conclusion

• Low-power, high-speed ADCs are in great needs.

New opportunities and breakthroughs are
expected in accelerated rate.

• Asynchronous SAR ADC architecture provides

power efficient platform for achieving this goal.
The record high-speed (90GS/s) ADC also
leverages this topology.

• More variations of asynchronous SAR ADC

architecture will come from all of you!

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 Acknowledgements

• All PhD students involved in these

projects: Jaewon Nam, Praveen Sharma
and David Chiong.

• ONR for funding supports.

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