Scribd
Upload
3 views

dsy_assignment1

The document presents a digital systems lab assignment focused on designing a full adder using half adders and a two-bit multiplier. It includes Verilog code for both the full adder and the two-bit multiplier, along with testbench code to simulate their functionality. Simulation outputs and schematics are also referenced but not included in the text.

Uploaded by

alihussain11746
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
3 views

dsy_assignment1

The document presents a digital systems lab assignment focused on designing a full adder using half adders and a two-bit multiplier. It includes Verilog code for both the full adder and the two-bit multiplier, along with testbench code to simulate their functionality. Simulation outputs and schematics are also referenced but not included in the text.

Uploaded by

alihussain11746
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 7

DIGITAL SYSTEMS LAB HUSSAIN ALI

ASSIGNMENT – 1

(24UCC209) FULL ADDER USING HALF

ADDERS

Design code : -

module FA_usingHA(

input a,

input b,

input c,

output sum,

output carry);

wire w1,w2,w3;

half_adder_dataflow i1(a,b,w2,w1);

half_adder_dataflow i2(w2,c,sum,w3);

or i3(carry,w1,w3);

Testbench Code : -

module tb_FA(

);

reg A,B,C;
wire sum,carry;

FA_usingHA dut(.a(A),.b(B),.c(C),.sum(sum),.carry(carry));

initial begin
A=0;B=0;C=0; #10;

A=0;B=1;C=0; #10;

A=0;B=0;C=1; #10;

A=0;B=1;C=1; #10;

A=1;B=0;C=0; #10;

A=1;B=1;C=0; #10;

A=1;B=0;C=1; #10;

A=1;B=1;C=1; #10;

$finish;

end

endmodule

Full adder simulation output:-


Full adder schematic ouput:-
Two-Bit Multiplier

Desgin Code : -

module twob_mul(
input [1:0] a,
input [1:0] b,
output [3:0] p
);

assign p[0] = a[0] &

b[0]; wire pin1, pin2,

pin3, pcarry;

assign pin1 = a[1] &


b[0]; assign pin2 = a[0]
& b[1];

half_adder ha1(
.a(pin1),
.b(pin2),
.sum(p[1]),
.carry(pcarry)
);

assign pin3 = a[1] &

b[1]; half_adder ha2(


.a(pin3),
.b(pcarry),
.sum(p[2]),
.carry(p[3])
);

endmodule
Testbench Code : -

module
twob_mul_tb; reg
[1:0] a;
reg [1:0] b;
wire [3:0] p;

twob_mul tb(
.a(a),
.b(b),
.p(p)
);

initial begin
a = 2'b00; b = 2'b00;
#10; a = 2'b00; b =
2'b01; #10;
a = 2'b00; b = 2'b10;
#10; a = 2'b00; b =
2'b11; #10; a =
2'b01; b = 2'b00;
#10; a = 2'b01; b =
2'b01; #10; a =
2'b01; b = 2'b10;
#10; a = 2'b01; b =
2'b11; #10; a =
2'b10; b = 2'b00;
#10; a = 2'b10; b =
2'b01; #10; a =
2'b10; b = 2'b10;
#10; a = 2'b10; b =
2'b11; #10; a =
2'b11; b = 2'b00;
#10; a = 2'b11; b =
2'b01; #10; a =
2'b11; b = 2'b10;
#10; a = 2'b11; b =
2'b11; #10;
$finis
h; end
endmodule
Two bit multiplier Simulation Output

Two-Bit Multiplier Schematic

You might also like